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Quelle  vega10_enum.h   Sprache: C

 
/*
 * Copyright (C) 2017  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#if !defined (_vega10_ENUM_HEADER)
#define _vega10_ENUM_HEADER

#ifndef _DRIVER_BUILD
#ifndef GL_ZERO
#define GL__ZERO                      BLEND_ZERO
#define GL__ONE                       BLEND_ONE
#define GL__SRC_COLOR                 BLEND_SRC_COLOR
#define GL__ONE_MINUS_SRC_COLOR       BLEND_ONE_MINUS_SRC_COLOR
#define GL__DST_COLOR                 BLEND_DST_COLOR
#define GL__ONE_MINUS_DST_COLOR       BLEND_ONE_MINUS_DST_COLOR
#define GL__SRC_ALPHA                 BLEND_SRC_ALPHA
#define GL__ONE_MINUS_SRC_ALPHA       BLEND_ONE_MINUS_SRC_ALPHA
#define GL__DST_ALPHA                 BLEND_DST_ALPHA
#define GL__ONE_MINUS_DST_ALPHA       BLEND_ONE_MINUS_DST_ALPHA
#define GL__SRC_ALPHA_SATURATE        BLEND_SRC_ALPHA_SATURATE
#define GL__CONSTANT_COLOR            BLEND_CONSTANT_COLOR
#define GL__ONE_MINUS_CONSTANT_COLOR  BLEND_ONE_MINUS_CONSTANT_COLOR
#define GL__CONSTANT_ALPHA            BLEND_CONSTANT_ALPHA
#define GL__ONE_MINUS_CONSTANT_ALPHA  BLEND_ONE_MINUS_CONSTANT_ALPHA
#endif
#endif

/*******************************************************
 * GDS DATA_TYPE Enums
 *******************************************************/


#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
#define ENUMS_GDS_PERFCOUNT_SELECT_H
typedef enum GDS_PERFCOUNT_SELECT {
 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
 GDS_PERF_SEL_DS_BANK_CONFL = 1,
 GDS_PERF_SEL_WBUF_FLUSH = 2,
 GDS_PERF_SEL_WR_COMP = 3,
 GDS_PERF_SEL_WBUF_WR = 4,
 GDS_PERF_SEL_RBUF_HIT = 5,
 GDS_PERF_SEL_RBUF_MISS = 6,
 GDS_PERF_SEL_SE0_SH0_NORET = 7,
 GDS_PERF_SEL_SE0_SH0_RET = 8,
 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
 GDS_PERF_SEL_SE0_SH1_NORET = 21,
 GDS_PERF_SEL_SE0_SH1_RET = 22,
 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
 GDS_PERF_SEL_SE1_SH0_NORET = 35,
 GDS_PERF_SEL_SE1_SH0_RET = 36,
 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
 GDS_PERF_SEL_SE1_SH1_NORET = 49,
 GDS_PERF_SEL_SE1_SH1_RET = 50,
 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
 GDS_PERF_SEL_SE2_SH0_NORET = 63,
 GDS_PERF_SEL_SE2_SH0_RET = 64,
 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
 GDS_PERF_SEL_SE2_SH1_NORET = 77,
 GDS_PERF_SEL_SE2_SH1_RET = 78,
 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
 GDS_PERF_SEL_SE3_SH0_NORET = 91,
 GDS_PERF_SEL_SE3_SH0_RET = 92,
 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
 GDS_PERF_SEL_SE3_SH1_NORET = 105,
 GDS_PERF_SEL_SE3_SH1_RET = 106,
 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
 GDS_PERF_SEL_GWS_RELEASED = 119,
 GDS_PERF_SEL_GWS_BYPASS = 120,
} GDS_PERFCOUNT_SELECT;
#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/

/*******************************************************
 * Chip Enums
 *******************************************************/


/*
 * MEM_PWR_FORCE_CTRL enum
 */


typedef enum MEM_PWR_FORCE_CTRL {
NO_FORCE_REQUEST                         = 0x00000000,
FORCE_LIGHT_SLEEP_REQUEST                = 0x00000001,
FORCE_DEEP_SLEEP_REQUEST                 = 0x00000002,
FORCE_SHUT_DOWN_REQUEST                  = 0x00000003,
} MEM_PWR_FORCE_CTRL;

/*
 * MEM_PWR_FORCE_CTRL2 enum
 */


typedef enum MEM_PWR_FORCE_CTRL2 {
NO_FORCE_REQ                             = 0x00000000,
FORCE_LIGHT_SLEEP_REQ                    = 0x00000001,
} MEM_PWR_FORCE_CTRL2;

/*
 * MEM_PWR_DIS_CTRL enum
 */


typedef enum MEM_PWR_DIS_CTRL {
ENABLE_MEM_PWR_CTRL                      = 0x00000000,
DISABLE_MEM_PWR_CTRL                     = 0x00000001,
} MEM_PWR_DIS_CTRL;

/*
 * MEM_PWR_SEL_CTRL enum
 */


typedef enum MEM_PWR_SEL_CTRL {
DYNAMIC_SHUT_DOWN_ENABLE                 = 0x00000000,
DYNAMIC_DEEP_SLEEP_ENABLE                = 0x00000001,
DYNAMIC_LIGHT_SLEEP_ENABLE               = 0x00000002,
} MEM_PWR_SEL_CTRL;

/*
 * MEM_PWR_SEL_CTRL2 enum
 */


typedef enum MEM_PWR_SEL_CTRL2 {
DYNAMIC_DEEP_SLEEP_EN                    = 0x00000000,
DYNAMIC_LIGHT_SLEEP_EN                   = 0x00000001,
} MEM_PWR_SEL_CTRL2;

/*
 * RowSize enum
 */


typedef enum RowSize {
ADDR_CONFIG_1KB_ROW                      = 0x00000000,
ADDR_CONFIG_2KB_ROW                      = 0x00000001,
ADDR_CONFIG_4KB_ROW                      = 0x00000002,
} RowSize;

/*
 * SurfaceEndian enum
 */


typedef enum SurfaceEndian {
ENDIAN_NONE                              = 0x00000000,
ENDIAN_8IN16                             = 0x00000001,
ENDIAN_8IN32                             = 0x00000002,
ENDIAN_8IN64                             = 0x00000003,
} SurfaceEndian;

/*
 * ArrayMode enum
 */


typedef enum ArrayMode {
ARRAY_LINEAR_GENERAL                     = 0x00000000,
ARRAY_LINEAR_ALIGNED                     = 0x00000001,
ARRAY_1D_TILED_THIN1                     = 0x00000002,
ARRAY_1D_TILED_THICK                     = 0x00000003,
ARRAY_2D_TILED_THIN1                     = 0x00000004,
ARRAY_PRT_TILED_THIN1                    = 0x00000005,
ARRAY_PRT_2D_TILED_THIN1                 = 0x00000006,
ARRAY_2D_TILED_THICK                     = 0x00000007,
ARRAY_2D_TILED_XTHICK                    = 0x00000008,
ARRAY_PRT_TILED_THICK                    = 0x00000009,
ARRAY_PRT_2D_TILED_THICK                 = 0x0000000a,
ARRAY_PRT_3D_TILED_THIN1                 = 0x0000000b,
ARRAY_3D_TILED_THIN1                     = 0x0000000c,
ARRAY_3D_TILED_THICK                     = 0x0000000d,
ARRAY_3D_TILED_XTHICK                    = 0x0000000e,
ARRAY_PRT_3D_TILED_THICK                 = 0x0000000f,
} ArrayMode;

/*
 * NumPipes enum
 */


typedef enum NumPipes {
ADDR_CONFIG_1_PIPE                       = 0x00000000,
ADDR_CONFIG_2_PIPE                       = 0x00000001,
ADDR_CONFIG_4_PIPE                       = 0x00000002,
ADDR_CONFIG_8_PIPE                       = 0x00000003,
ADDR_CONFIG_16_PIPE                      = 0x00000004,
ADDR_CONFIG_32_PIPE                      = 0x00000005,
} NumPipes;

/*
 * NumBanksConfig enum
 */


typedef enum NumBanksConfig {
ADDR_CONFIG_1_BANK                       = 0x00000000,
ADDR_CONFIG_2_BANK                       = 0x00000001,
ADDR_CONFIG_4_BANK                       = 0x00000002,
ADDR_CONFIG_8_BANK                       = 0x00000003,
ADDR_CONFIG_16_BANK                      = 0x00000004,
} NumBanksConfig;

/*
 * PipeInterleaveSize enum
 */


typedef enum PipeInterleaveSize {
ADDR_CONFIG_PIPE_INTERLEAVE_256B         = 0x00000000,
ADDR_CONFIG_PIPE_INTERLEAVE_512B         = 0x00000001,
ADDR_CONFIG_PIPE_INTERLEAVE_1KB          = 0x00000002,
ADDR_CONFIG_PIPE_INTERLEAVE_2KB          = 0x00000003,
} PipeInterleaveSize;

/*
 * BankInterleaveSize enum
 */


typedef enum BankInterleaveSize {
ADDR_CONFIG_BANK_INTERLEAVE_1            = 0x00000000,
ADDR_CONFIG_BANK_INTERLEAVE_2            = 0x00000001,
ADDR_CONFIG_BANK_INTERLEAVE_4            = 0x00000002,
ADDR_CONFIG_BANK_INTERLEAVE_8            = 0x00000003,
} BankInterleaveSize;

/*
 * NumShaderEngines enum
 */


typedef enum NumShaderEngines {
ADDR_CONFIG_1_SHADER_ENGINE              = 0x00000000,
ADDR_CONFIG_2_SHADER_ENGINE              = 0x00000001,
ADDR_CONFIG_4_SHADER_ENGINE              = 0x00000002,
ADDR_CONFIG_8_SHADER_ENGINE              = 0x00000003,
} NumShaderEngines;

/*
 * NumRbPerShaderEngine enum
 */


typedef enum NumRbPerShaderEngine {
ADDR_CONFIG_1_RB_PER_SHADER_ENGINE       = 0x00000000,
ADDR_CONFIG_2_RB_PER_SHADER_ENGINE       = 0x00000001,
ADDR_CONFIG_4_RB_PER_SHADER_ENGINE       = 0x00000002,
} NumRbPerShaderEngine;

/*
 * NumGPUs enum
 */


typedef enum NumGPUs {
ADDR_CONFIG_1_GPU                        = 0x00000000,
ADDR_CONFIG_2_GPU                        = 0x00000001,
ADDR_CONFIG_4_GPU                        = 0x00000002,
ADDR_CONFIG_8_GPU                        = 0x00000003,
} NumGPUs;

/*
 * NumMaxCompressedFragments enum
 */


typedef enum NumMaxCompressedFragments {
ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS   = 0x00000000,
ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS   = 0x00000001,
ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS   = 0x00000002,
ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS   = 0x00000003,
} NumMaxCompressedFragments;

/*
 * ShaderEngineTileSize enum
 */


typedef enum ShaderEngineTileSize {
ADDR_CONFIG_SE_TILE_16                   = 0x00000000,
ADDR_CONFIG_SE_TILE_32                   = 0x00000001,
} ShaderEngineTileSize;

/*
 * MultiGPUTileSize enum
 */


typedef enum MultiGPUTileSize {
ADDR_CONFIG_GPU_TILE_16                  = 0x00000000,
ADDR_CONFIG_GPU_TILE_32                  = 0x00000001,
ADDR_CONFIG_GPU_TILE_64                  = 0x00000002,
ADDR_CONFIG_GPU_TILE_128                 = 0x00000003,
} MultiGPUTileSize;

/*
 * NumLowerPipes enum
 */


typedef enum NumLowerPipes {
ADDR_CONFIG_1_LOWER_PIPES                = 0x00000000,
ADDR_CONFIG_2_LOWER_PIPES                = 0x00000001,
} NumLowerPipes;

/*
 * ColorTransform enum
 */


typedef enum ColorTransform {
DCC_CT_AUTO                              = 0x00000000,
DCC_CT_NONE                              = 0x00000001,
ABGR_TO_A_BG_G_RB                        = 0x00000002,
BGRA_TO_BG_G_RB_A                        = 0x00000003,
} ColorTransform;

/*
 * CompareRef enum
 */


typedef enum CompareRef {
REF_NEVER                                = 0x00000000,
REF_LESS                                 = 0x00000001,
REF_EQUAL                                = 0x00000002,
REF_LEQUAL                               = 0x00000003,
REF_GREATER                              = 0x00000004,
REF_NOTEQUAL                             = 0x00000005,
REF_GEQUAL                               = 0x00000006,
REF_ALWAYS                               = 0x00000007,
} CompareRef;

/*
 * ReadSize enum
 */


typedef enum ReadSize {
READ_256_BITS                            = 0x00000000,
READ_512_BITS                            = 0x00000001,
} ReadSize;

/*
 * DepthFormat enum
 */


typedef enum DepthFormat {
DEPTH_INVALID                            = 0x00000000,
DEPTH_16                                 = 0x00000001,
DEPTH_X8_24                              = 0x00000002,
DEPTH_8_24                               = 0x00000003,
DEPTH_X8_24_FLOAT                        = 0x00000004,
DEPTH_8_24_FLOAT                         = 0x00000005,
DEPTH_32_FLOAT                           = 0x00000006,
DEPTH_X24_8_32_FLOAT                     = 0x00000007,
} DepthFormat;

/*
 * ZFormat enum
 */


typedef enum ZFormat {
Z_INVALID                                = 0x00000000,
Z_16                                     = 0x00000001,
Z_24                                     = 0x00000002,
Z_32_FLOAT                               = 0x00000003,
} ZFormat;

/*
 * StencilFormat enum
 */


typedef enum StencilFormat {
STENCIL_INVALID                          = 0x00000000,
STENCIL_8                                = 0x00000001,
} StencilFormat;

/*
 * CmaskMode enum
 */


typedef enum CmaskMode {
CMASK_CLEAR_NONE                         = 0x00000000,
CMASK_CLEAR_ONE                          = 0x00000001,
CMASK_CLEAR_ALL                          = 0x00000002,
CMASK_ANY_EXPANDED                       = 0x00000003,
CMASK_ALPHA0_FRAG1                       = 0x00000004,
CMASK_ALPHA0_FRAG2                       = 0x00000005,
CMASK_ALPHA0_FRAG4                       = 0x00000006,
CMASK_ALPHA0_FRAGS                       = 0x00000007,
CMASK_ALPHA1_FRAG1                       = 0x00000008,
CMASK_ALPHA1_FRAG2                       = 0x00000009,
CMASK_ALPHA1_FRAG4                       = 0x0000000a,
CMASK_ALPHA1_FRAGS                       = 0x0000000b,
CMASK_ALPHAX_FRAG1                       = 0x0000000c,
CMASK_ALPHAX_FRAG2                       = 0x0000000d,
CMASK_ALPHAX_FRAG4                       = 0x0000000e,
CMASK_ALPHAX_FRAGS                       = 0x0000000f,
} CmaskMode;

/*
 * QuadExportFormat enum
 */


typedef enum QuadExportFormat {
EXPORT_UNUSED                            = 0x00000000,
EXPORT_32_R                              = 0x00000001,
EXPORT_32_GR                             = 0x00000002,
EXPORT_32_AR                             = 0x00000003,
EXPORT_FP16_ABGR                         = 0x00000004,
EXPORT_UNSIGNED16_ABGR                   = 0x00000005,
EXPORT_SIGNED16_ABGR                     = 0x00000006,
EXPORT_32_ABGR                           = 0x00000007,
EXPORT_32BPP_8PIX                        = 0x00000008,
EXPORT_16_16_UNSIGNED_8PIX               = 0x00000009,
EXPORT_16_16_SIGNED_8PIX                 = 0x0000000a,
EXPORT_16_16_FLOAT_8PIX                  = 0x0000000b,
} QuadExportFormat;

/*
 * QuadExportFormatOld enum
 */


typedef enum QuadExportFormatOld {
EXPORT_4P_32BPC_ABGR                     = 0x00000000,
EXPORT_4P_16BPC_ABGR                     = 0x00000001,
EXPORT_4P_32BPC_GR                       = 0x00000002,
EXPORT_4P_32BPC_AR                       = 0x00000003,
EXPORT_2P_32BPC_ABGR                     = 0x00000004,
EXPORT_8P_32BPC_R                        = 0x00000005,
} QuadExportFormatOld;

/*
 * ColorFormat enum
 */


typedef enum ColorFormat {
COLOR_INVALID                            = 0x00000000,
COLOR_8                                  = 0x00000001,
COLOR_16                                 = 0x00000002,
COLOR_8_8                                = 0x00000003,
COLOR_32                                 = 0x00000004,
COLOR_16_16                              = 0x00000005,
COLOR_10_11_11                           = 0x00000006,
COLOR_11_11_10                           = 0x00000007,
COLOR_10_10_10_2                         = 0x00000008,
COLOR_2_10_10_10                         = 0x00000009,
COLOR_8_8_8_8                            = 0x0000000a,
COLOR_32_32                              = 0x0000000b,
COLOR_16_16_16_16                        = 0x0000000c,
COLOR_RESERVED_13                        = 0x0000000d,
COLOR_32_32_32_32                        = 0x0000000e,
COLOR_RESERVED_15                        = 0x0000000f,
COLOR_5_6_5                              = 0x00000010,
COLOR_1_5_5_5                            = 0x00000011,
COLOR_5_5_5_1                            = 0x00000012,
COLOR_4_4_4_4                            = 0x00000013,
COLOR_8_24                               = 0x00000014,
COLOR_24_8                               = 0x00000015,
COLOR_X24_8_32_FLOAT                     = 0x00000016,
COLOR_RESERVED_23                        = 0x00000017,
COLOR_RESERVED_24                        = 0x00000018,
COLOR_RESERVED_25                        = 0x00000019,
COLOR_RESERVED_26                        = 0x0000001a,
COLOR_RESERVED_27                        = 0x0000001b,
COLOR_RESERVED_28                        = 0x0000001c,
COLOR_RESERVED_29                        = 0x0000001d,
COLOR_RESERVED_30                        = 0x0000001e,
COLOR_2_10_10_10_6E4                     = 0x0000001f,
} ColorFormat;

/*
 * SurfaceFormat enum
 */


typedef enum SurfaceFormat {
FMT_INVALID                              = 0x00000000,
FMT_8                                    = 0x00000001,
FMT_16                                   = 0x00000002,
FMT_8_8                                  = 0x00000003,
FMT_32                                   = 0x00000004,
FMT_16_16                                = 0x00000005,
FMT_10_11_11                             = 0x00000006,
FMT_11_11_10                             = 0x00000007,
FMT_10_10_10_2                           = 0x00000008,
FMT_2_10_10_10                           = 0x00000009,
FMT_8_8_8_8                              = 0x0000000a,
FMT_32_32                                = 0x0000000b,
FMT_16_16_16_16                          = 0x0000000c,
FMT_32_32_32                             = 0x0000000d,
FMT_32_32_32_32                          = 0x0000000e,
FMT_RESERVED_4                           = 0x0000000f,
FMT_5_6_5                                = 0x00000010,
FMT_1_5_5_5                              = 0x00000011,
FMT_5_5_5_1                              = 0x00000012,
FMT_4_4_4_4                              = 0x00000013,
FMT_8_24                                 = 0x00000014,
FMT_24_8                                 = 0x00000015,
FMT_X24_8_32_FLOAT                       = 0x00000016,
FMT_RESERVED_33                          = 0x00000017,
FMT_11_11_10_FLOAT                       = 0x00000018,
FMT_16_FLOAT                             = 0x00000019,
FMT_32_FLOAT                             = 0x0000001a,
FMT_16_16_FLOAT                          = 0x0000001b,
FMT_8_24_FLOAT                           = 0x0000001c,
FMT_24_8_FLOAT                           = 0x0000001d,
FMT_32_32_FLOAT                          = 0x0000001e,
FMT_10_11_11_FLOAT                       = 0x0000001f,
FMT_16_16_16_16_FLOAT                    = 0x00000020,
FMT_3_3_2                                = 0x00000021,
FMT_6_5_5                                = 0x00000022,
FMT_32_32_32_32_FLOAT                    = 0x00000023,
FMT_RESERVED_36                          = 0x00000024,
FMT_1                                    = 0x00000025,
FMT_1_REVERSED                           = 0x00000026,
FMT_GB_GR                                = 0x00000027,
FMT_BG_RG                                = 0x00000028,
FMT_32_AS_8                              = 0x00000029,
FMT_32_AS_8_8                            = 0x0000002a,
FMT_5_9_9_9_SHAREDEXP                    = 0x0000002b,
FMT_8_8_8                                = 0x0000002c,
FMT_16_16_16                             = 0x0000002d,
FMT_16_16_16_FLOAT                       = 0x0000002e,
FMT_4_4                                  = 0x0000002f,
FMT_32_32_32_FLOAT                       = 0x00000030,
FMT_BC1                                  = 0x00000031,
FMT_BC2                                  = 0x00000032,
FMT_BC3                                  = 0x00000033,
FMT_BC4                                  = 0x00000034,
FMT_BC5                                  = 0x00000035,
FMT_BC6                                  = 0x00000036,
FMT_BC7                                  = 0x00000037,
FMT_32_AS_32_32_32_32                    = 0x00000038,
FMT_APC3                                 = 0x00000039,
FMT_APC4                                 = 0x0000003a,
FMT_APC5                                 = 0x0000003b,
FMT_APC6                                 = 0x0000003c,
FMT_APC7                                 = 0x0000003d,
FMT_CTX1                                 = 0x0000003e,
FMT_RESERVED_63                          = 0x0000003f,
} SurfaceFormat;

/*
 * BUF_DATA_FORMAT enum
 */


typedef enum BUF_DATA_FORMAT {
BUF_DATA_FORMAT_INVALID                  = 0x00000000,
BUF_DATA_FORMAT_8                        = 0x00000001,
BUF_DATA_FORMAT_16                       = 0x00000002,
BUF_DATA_FORMAT_8_8                      = 0x00000003,
BUF_DATA_FORMAT_32                       = 0x00000004,
BUF_DATA_FORMAT_16_16                    = 0x00000005,
BUF_DATA_FORMAT_10_11_11                 = 0x00000006,
BUF_DATA_FORMAT_11_11_10                 = 0x00000007,
BUF_DATA_FORMAT_10_10_10_2               = 0x00000008,
BUF_DATA_FORMAT_2_10_10_10               = 0x00000009,
BUF_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
BUF_DATA_FORMAT_32_32                    = 0x0000000b,
BUF_DATA_FORMAT_16_16_16_16              = 0x0000000c,
BUF_DATA_FORMAT_32_32_32                 = 0x0000000d,
BUF_DATA_FORMAT_32_32_32_32              = 0x0000000e,
BUF_DATA_FORMAT_RESERVED_15              = 0x0000000f,
} BUF_DATA_FORMAT;

/*
 * IMG_DATA_FORMAT enum
 */


typedef enum IMG_DATA_FORMAT {
IMG_DATA_FORMAT_INVALID                  = 0x00000000,
IMG_DATA_FORMAT_8                        = 0x00000001,
IMG_DATA_FORMAT_16                       = 0x00000002,
IMG_DATA_FORMAT_8_8                      = 0x00000003,
IMG_DATA_FORMAT_32                       = 0x00000004,
IMG_DATA_FORMAT_16_16                    = 0x00000005,
IMG_DATA_FORMAT_10_11_11                 = 0x00000006,
IMG_DATA_FORMAT_11_11_10                 = 0x00000007,
IMG_DATA_FORMAT_10_10_10_2               = 0x00000008,
IMG_DATA_FORMAT_2_10_10_10               = 0x00000009,
IMG_DATA_FORMAT_8_8_8_8                  = 0x0000000a,
IMG_DATA_FORMAT_32_32                    = 0x0000000b,
IMG_DATA_FORMAT_16_16_16_16              = 0x0000000c,
IMG_DATA_FORMAT_32_32_32                 = 0x0000000d,
IMG_DATA_FORMAT_32_32_32_32              = 0x0000000e,
IMG_DATA_FORMAT_RESERVED_15              = 0x0000000f,
IMG_DATA_FORMAT_5_6_5                    = 0x00000010,
IMG_DATA_FORMAT_1_5_5_5                  = 0x00000011,
IMG_DATA_FORMAT_5_5_5_1                  = 0x00000012,
IMG_DATA_FORMAT_4_4_4_4                  = 0x00000013,
IMG_DATA_FORMAT_8_24                     = 0x00000014,
IMG_DATA_FORMAT_24_8                     = 0x00000015,
IMG_DATA_FORMAT_X24_8_32                 = 0x00000016,
IMG_DATA_FORMAT_8_AS_8_8_8_8             = 0x00000017,
IMG_DATA_FORMAT_ETC2_RGB                 = 0x00000018,
IMG_DATA_FORMAT_ETC2_RGBA                = 0x00000019,
IMG_DATA_FORMAT_ETC2_R                   = 0x0000001a,
IMG_DATA_FORMAT_ETC2_RG                  = 0x0000001b,
IMG_DATA_FORMAT_ETC2_RGBA1               = 0x0000001c,
IMG_DATA_FORMAT_RESERVED_29              = 0x0000001d,
IMG_DATA_FORMAT_RESERVED_30              = 0x0000001e,
IMG_DATA_FORMAT_6E4                      = 0x0000001f,
IMG_DATA_FORMAT_GB_GR                    = 0x00000020,
IMG_DATA_FORMAT_BG_RG                    = 0x00000021,
IMG_DATA_FORMAT_5_9_9_9                  = 0x00000022,
IMG_DATA_FORMAT_BC1                      = 0x00000023,
IMG_DATA_FORMAT_BC2                      = 0x00000024,
IMG_DATA_FORMAT_BC3                      = 0x00000025,
IMG_DATA_FORMAT_BC4                      = 0x00000026,
IMG_DATA_FORMAT_BC5                      = 0x00000027,
IMG_DATA_FORMAT_BC6                      = 0x00000028,
IMG_DATA_FORMAT_BC7                      = 0x00000029,
IMG_DATA_FORMAT_16_AS_32_32              = 0x0000002a,
IMG_DATA_FORMAT_16_AS_16_16_16_16        = 0x0000002b,
IMG_DATA_FORMAT_16_AS_32_32_32_32        = 0x0000002c,
IMG_DATA_FORMAT_FMASK                    = 0x0000002d,
IMG_DATA_FORMAT_ASTC_2D_LDR              = 0x0000002e,
IMG_DATA_FORMAT_ASTC_2D_HDR              = 0x0000002f,
IMG_DATA_FORMAT_ASTC_2D_LDR_SRGB         = 0x00000030,
IMG_DATA_FORMAT_ASTC_3D_LDR              = 0x00000031,
IMG_DATA_FORMAT_ASTC_3D_HDR              = 0x00000032,
IMG_DATA_FORMAT_ASTC_3D_LDR_SRGB         = 0x00000033,
IMG_DATA_FORMAT_N_IN_16                  = 0x00000034,
IMG_DATA_FORMAT_N_IN_16_16               = 0x00000035,
IMG_DATA_FORMAT_N_IN_16_16_16_16         = 0x00000036,
IMG_DATA_FORMAT_N_IN_16_AS_16_16_16_16   = 0x00000037,
IMG_DATA_FORMAT_RESERVED_56              = 0x00000038,
IMG_DATA_FORMAT_4_4                      = 0x00000039,
IMG_DATA_FORMAT_6_5_5                    = 0x0000003a,
IMG_DATA_FORMAT_RESERVED_59              = 0x0000003b,
IMG_DATA_FORMAT_RESERVED_60              = 0x0000003c,
IMG_DATA_FORMAT_8_AS_32                  = 0x0000003d,
IMG_DATA_FORMAT_8_AS_32_32               = 0x0000003e,
IMG_DATA_FORMAT_32_AS_32_32_32_32        = 0x0000003f,
} IMG_DATA_FORMAT;

/*
 * BUF_NUM_FORMAT enum
 */


typedef enum BUF_NUM_FORMAT {
BUF_NUM_FORMAT_UNORM                     = 0x00000000,
BUF_NUM_FORMAT_SNORM                     = 0x00000001,
BUF_NUM_FORMAT_USCALED                   = 0x00000002,
BUF_NUM_FORMAT_SSCALED                   = 0x00000003,
BUF_NUM_FORMAT_UINT                      = 0x00000004,
BUF_NUM_FORMAT_SINT                      = 0x00000005,
BUF_NUM_FORMAT_UNORM_UINT                = 0x00000006,
BUF_NUM_FORMAT_FLOAT                     = 0x00000007,
} BUF_NUM_FORMAT;

/*
 * IMG_NUM_FORMAT enum
 */


typedef enum IMG_NUM_FORMAT {
IMG_NUM_FORMAT_UNORM                     = 0x00000000,
IMG_NUM_FORMAT_SNORM                     = 0x00000001,
IMG_NUM_FORMAT_USCALED                   = 0x00000002,
IMG_NUM_FORMAT_SSCALED                   = 0x00000003,
IMG_NUM_FORMAT_UINT                      = 0x00000004,
IMG_NUM_FORMAT_SINT                      = 0x00000005,
IMG_NUM_FORMAT_UNORM_UINT                = 0x00000006,
IMG_NUM_FORMAT_FLOAT                     = 0x00000007,
IMG_NUM_FORMAT_RESERVED_8                = 0x00000008,
IMG_NUM_FORMAT_SRGB                      = 0x00000009,
IMG_NUM_FORMAT_RESERVED_10               = 0x0000000a,
IMG_NUM_FORMAT_RESERVED_11               = 0x0000000b,
IMG_NUM_FORMAT_RESERVED_12               = 0x0000000c,
IMG_NUM_FORMAT_RESERVED_13               = 0x0000000d,
IMG_NUM_FORMAT_RESERVED_14               = 0x0000000e,
IMG_NUM_FORMAT_RESERVED_15               = 0x0000000f,
} IMG_NUM_FORMAT;

/*
 * IMG_NUM_FORMAT_FMASK enum
 */


typedef enum IMG_NUM_FORMAT_FMASK {
IMG_NUM_FORMAT_FMASK_8_2_1               = 0x00000000,
IMG_NUM_FORMAT_FMASK_8_4_1               = 0x00000001,
IMG_NUM_FORMAT_FMASK_8_8_1               = 0x00000002,
IMG_NUM_FORMAT_FMASK_8_2_2               = 0x00000003,
IMG_NUM_FORMAT_FMASK_8_4_2               = 0x00000004,
IMG_NUM_FORMAT_FMASK_8_4_4               = 0x00000005,
IMG_NUM_FORMAT_FMASK_16_16_1             = 0x00000006,
IMG_NUM_FORMAT_FMASK_16_8_2              = 0x00000007,
IMG_NUM_FORMAT_FMASK_32_16_2             = 0x00000008,
IMG_NUM_FORMAT_FMASK_32_8_4              = 0x00000009,
IMG_NUM_FORMAT_FMASK_32_8_8              = 0x0000000a,
IMG_NUM_FORMAT_FMASK_64_16_4             = 0x0000000b,
IMG_NUM_FORMAT_FMASK_64_16_8             = 0x0000000c,
IMG_NUM_FORMAT_FMASK_RESERVED_13         = 0x0000000d,
IMG_NUM_FORMAT_FMASK_RESERVED_14         = 0x0000000e,
IMG_NUM_FORMAT_FMASK_RESERVED_15         = 0x0000000f,
} IMG_NUM_FORMAT_FMASK;

/*
 * IMG_NUM_FORMAT_N_IN_16 enum
 */


typedef enum IMG_NUM_FORMAT_N_IN_16 {
IMG_NUM_FORMAT_N_IN_16_RESERVED_0        = 0x00000000,
IMG_NUM_FORMAT_N_IN_16_UNORM_10          = 0x00000001,
IMG_NUM_FORMAT_N_IN_16_UNORM_9           = 0x00000002,
IMG_NUM_FORMAT_N_IN_16_RESERVED_3        = 0x00000003,
IMG_NUM_FORMAT_N_IN_16_UINT_10           = 0x00000004,
IMG_NUM_FORMAT_N_IN_16_UINT_9            = 0x00000005,
IMG_NUM_FORMAT_N_IN_16_RESERVED_6        = 0x00000006,
IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10     = 0x00000007,
IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9      = 0x00000008,
IMG_NUM_FORMAT_N_IN_16_RESERVED_9        = 0x00000009,
IMG_NUM_FORMAT_N_IN_16_RESERVED_10       = 0x0000000a,
IMG_NUM_FORMAT_N_IN_16_RESERVED_11       = 0x0000000b,
IMG_NUM_FORMAT_N_IN_16_RESERVED_12       = 0x0000000c,
IMG_NUM_FORMAT_N_IN_16_RESERVED_13       = 0x0000000d,
IMG_NUM_FORMAT_N_IN_16_RESERVED_14       = 0x0000000e,
IMG_NUM_FORMAT_N_IN_16_RESERVED_15       = 0x0000000f,
} IMG_NUM_FORMAT_N_IN_16;

/*
 * IMG_NUM_FORMAT_ASTC_2D enum
 */


typedef enum IMG_NUM_FORMAT_ASTC_2D {
IMG_NUM_FORMAT_ASTC_2D_4x4               = 0x00000000,
IMG_NUM_FORMAT_ASTC_2D_5x4               = 0x00000001,
IMG_NUM_FORMAT_ASTC_2D_5x5               = 0x00000002,
IMG_NUM_FORMAT_ASTC_2D_6x5               = 0x00000003,
IMG_NUM_FORMAT_ASTC_2D_6x6               = 0x00000004,
IMG_NUM_FORMAT_ASTC_2D_8x5               = 0x00000005,
IMG_NUM_FORMAT_ASTC_2D_8x6               = 0x00000006,
IMG_NUM_FORMAT_ASTC_2D_8x8               = 0x00000007,
IMG_NUM_FORMAT_ASTC_2D_10x5              = 0x00000008,
IMG_NUM_FORMAT_ASTC_2D_10x6              = 0x00000009,
IMG_NUM_FORMAT_ASTC_2D_10x8              = 0x0000000a,
IMG_NUM_FORMAT_ASTC_2D_10x10             = 0x0000000b,
IMG_NUM_FORMAT_ASTC_2D_12x10             = 0x0000000c,
IMG_NUM_FORMAT_ASTC_2D_12x12             = 0x0000000d,
IMG_NUM_FORMAT_ASTC_2D_RESERVED_14       = 0x0000000e,
IMG_NUM_FORMAT_ASTC_2D_RESERVED_15       = 0x0000000f,
} IMG_NUM_FORMAT_ASTC_2D;

/*
 * IMG_NUM_FORMAT_ASTC_3D enum
 */


typedef enum IMG_NUM_FORMAT_ASTC_3D {
IMG_NUM_FORMAT_ASTC_3D_3x3x3             = 0x00000000,
IMG_NUM_FORMAT_ASTC_3D_4x3x3             = 0x00000001,
IMG_NUM_FORMAT_ASTC_3D_4x4x3             = 0x00000002,
IMG_NUM_FORMAT_ASTC_3D_4x4x4             = 0x00000003,
IMG_NUM_FORMAT_ASTC_3D_5x4x4             = 0x00000004,
IMG_NUM_FORMAT_ASTC_3D_5x5x4             = 0x00000005,
IMG_NUM_FORMAT_ASTC_3D_5x5x5             = 0x00000006,
IMG_NUM_FORMAT_ASTC_3D_6x5x5             = 0x00000007,
IMG_NUM_FORMAT_ASTC_3D_6x6x5             = 0x00000008,
IMG_NUM_FORMAT_ASTC_3D_6x6x6             = 0x00000009,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_10       = 0x0000000a,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_11       = 0x0000000b,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_12       = 0x0000000c,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_13       = 0x0000000d,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_14       = 0x0000000e,
IMG_NUM_FORMAT_ASTC_3D_RESERVED_15       = 0x0000000f,
} IMG_NUM_FORMAT_ASTC_3D;

/*
 * TileType enum
 */


typedef enum TileType {
ARRAY_COLOR_TILE                         = 0x00000000,
ARRAY_DEPTH_TILE                         = 0x00000001,
} TileType;

/*
 * NonDispTilingOrder enum
 */


typedef enum NonDispTilingOrder {
ADDR_SURF_MICRO_TILING_DISPLAY           = 0x00000000,
ADDR_SURF_MICRO_TILING_NON_DISPLAY       = 0x00000001,
} NonDispTilingOrder;

/*
 * MicroTileMode enum
 */


typedef enum MicroTileMode {
ADDR_SURF_DISPLAY_MICRO_TILING           = 0x00000000,
ADDR_SURF_THIN_MICRO_TILING              = 0x00000001,
ADDR_SURF_DEPTH_MICRO_TILING             = 0x00000002,
ADDR_SURF_ROTATED_MICRO_TILING           = 0x00000003,
ADDR_SURF_THICK_MICRO_TILING             = 0x00000004,
} MicroTileMode;

/*
 * TileSplit enum
 */


typedef enum TileSplit {
ADDR_SURF_TILE_SPLIT_64B                 = 0x00000000,
ADDR_SURF_TILE_SPLIT_128B                = 0x00000001,
ADDR_SURF_TILE_SPLIT_256B                = 0x00000002,
ADDR_SURF_TILE_SPLIT_512B                = 0x00000003,
ADDR_SURF_TILE_SPLIT_1KB                 = 0x00000004,
ADDR_SURF_TILE_SPLIT_2KB                 = 0x00000005,
ADDR_SURF_TILE_SPLIT_4KB                 = 0x00000006,
} TileSplit;

/*
 * SampleSplit enum
 */


typedef enum SampleSplit {
ADDR_SURF_SAMPLE_SPLIT_1                 = 0x00000000,
ADDR_SURF_SAMPLE_SPLIT_2                 = 0x00000001,
ADDR_SURF_SAMPLE_SPLIT_4                 = 0x00000002,
ADDR_SURF_SAMPLE_SPLIT_8                 = 0x00000003,
} SampleSplit;

/*
 * PipeConfig enum
 */


typedef enum PipeConfig {
ADDR_SURF_P2                             = 0x00000000,
ADDR_SURF_P2_RESERVED0                   = 0x00000001,
ADDR_SURF_P2_RESERVED1                   = 0x00000002,
ADDR_SURF_P2_RESERVED2                   = 0x00000003,
ADDR_SURF_P4_8x16                        = 0x00000004,
ADDR_SURF_P4_16x16                       = 0x00000005,
ADDR_SURF_P4_16x32                       = 0x00000006,
ADDR_SURF_P4_32x32                       = 0x00000007,
ADDR_SURF_P8_16x16_8x16                  = 0x00000008,
ADDR_SURF_P8_16x32_8x16                  = 0x00000009,
ADDR_SURF_P8_32x32_8x16                  = 0x0000000a,
ADDR_SURF_P8_16x32_16x16                 = 0x0000000b,
ADDR_SURF_P8_32x32_16x16                 = 0x0000000c,
ADDR_SURF_P8_32x32_16x32                 = 0x0000000d,
ADDR_SURF_P8_32x64_32x32                 = 0x0000000e,
ADDR_SURF_P8_RESERVED0                   = 0x0000000f,
ADDR_SURF_P16_32x32_8x16                 = 0x00000010,
ADDR_SURF_P16_32x32_16x16                = 0x00000011,
} PipeConfig;

/*
 * SeEnable enum
 */


typedef enum SeEnable {
ADDR_CONFIG_DISABLE_SE                   = 0x00000000,
ADDR_CONFIG_ENABLE_SE                    = 0x00000001,
} SeEnable;

/*
 * NumBanks enum
 */


typedef enum NumBanks {
ADDR_SURF_2_BANK                         = 0x00000000,
ADDR_SURF_4_BANK                         = 0x00000001,
ADDR_SURF_8_BANK                         = 0x00000002,
ADDR_SURF_16_BANK                        = 0x00000003,
} NumBanks;

/*
 * BankWidth enum
 */


typedef enum BankWidth {
ADDR_SURF_BANK_WIDTH_1                   = 0x00000000,
ADDR_SURF_BANK_WIDTH_2                   = 0x00000001,
ADDR_SURF_BANK_WIDTH_4                   = 0x00000002,
ADDR_SURF_BANK_WIDTH_8                   = 0x00000003,
} BankWidth;

/*
 * BankHeight enum
 */


typedef enum BankHeight {
ADDR_SURF_BANK_HEIGHT_1                  = 0x00000000,
ADDR_SURF_BANK_HEIGHT_2                  = 0x00000001,
ADDR_SURF_BANK_HEIGHT_4                  = 0x00000002,
ADDR_SURF_BANK_HEIGHT_8                  = 0x00000003,
} BankHeight;

/*
 * BankWidthHeight enum
 */


typedef enum BankWidthHeight {
ADDR_SURF_BANK_WH_1                      = 0x00000000,
ADDR_SURF_BANK_WH_2                      = 0x00000001,
ADDR_SURF_BANK_WH_4                      = 0x00000002,
ADDR_SURF_BANK_WH_8                      = 0x00000003,
} BankWidthHeight;

/*
 * MacroTileAspect enum
 */


typedef enum MacroTileAspect {
ADDR_SURF_MACRO_ASPECT_1                 = 0x00000000,
ADDR_SURF_MACRO_ASPECT_2                 = 0x00000001,
ADDR_SURF_MACRO_ASPECT_4                 = 0x00000002,
ADDR_SURF_MACRO_ASPECT_8                 = 0x00000003,
} MacroTileAspect;

/*
 * GATCL1RequestType enum
 */


typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL                       = 0x00000000,
GATCL1_TYPE_SHOOTDOWN                    = 0x00000001,
GATCL1_TYPE_BYPASS                       = 0x00000002,
} GATCL1RequestType;

/*
 * UTCL1RequestType enum
 */


typedef enum UTCL1RequestType {
UTCL1_TYPE_NORMAL                        = 0x00000000,
UTCL1_TYPE_SHOOTDOWN                     = 0x00000001,
UTCL1_TYPE_BYPASS                        = 0x00000002,
} UTCL1RequestType;

/*
 * UTCL1FaultType enum
 */


typedef enum UTCL1FaultType {
UTCL1_XNACK_SUCCESS                      = 0x00000000,
UTCL1_XNACK_RETRY                        = 0x00000001,
UTCL1_XNACK_PRT                          = 0x00000002,
UTCL1_XNACK_NO_RETRY                     = 0x00000003,
} UTCL1FaultType;

/*
 * TCC_CACHE_POLICIES enum
 */


typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU                     = 0x00000000,
TCC_CACHE_POLICY_STREAM                  = 0x00000001,
} TCC_CACHE_POLICIES;

/*
 * MTYPE enum
 */


typedef enum MTYPE {
MTYPE_NC                                 = 0x00000000,
MTYPE_WC                                 = 0x00000001,
MTYPE_RW                                 = 0x00000001,
MTYPE_CC                                 = 0x00000002,
MTYPE_UC                                 = 0x00000003,
} MTYPE;

/*
 * RMI_CID enum
 */


typedef enum RMI_CID {
RMI_CID_CC                               = 0x00000000,
RMI_CID_FC                               = 0x00000001,
RMI_CID_CM                               = 0x00000002,
RMI_CID_DC                               = 0x00000003,
RMI_CID_Z                                = 0x00000004,
RMI_CID_S                                = 0x00000005,
RMI_CID_TILE                             = 0x00000006,
RMI_CID_ZPCPSD                           = 0x00000007,
} RMI_CID;

/*
 * PERFMON_COUNTER_MODE enum
 */


typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM               = 0x00000000,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES       = 0x00000001,
PERFMON_COUNTER_MODE_MAX                 = 0x00000002,
PERFMON_COUNTER_MODE_DIRTY               = 0x00000003,
PERFMON_COUNTER_MODE_SAMPLE              = 0x00000004,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT  = 0x00000005,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT  = 0x00000006,
PERFMON_COUNTER_MODE_CYCLES_GE_HI        = 0x00000007,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI        = 0x00000008,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES     = 0x00000009,
PERFMON_COUNTER_MODE_RESERVED            = 0x0000000f,
} PERFMON_COUNTER_MODE;

/*
 * PERFMON_SPM_MODE enum
 */


typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF                     = 0x00000000,
PERFMON_SPM_MODE_16BIT_CLAMP             = 0x00000001,
PERFMON_SPM_MODE_16BIT_NO_CLAMP          = 0x00000002,
PERFMON_SPM_MODE_32BIT_CLAMP             = 0x00000003,
PERFMON_SPM_MODE_32BIT_NO_CLAMP          = 0x00000004,
PERFMON_SPM_MODE_RESERVED_5              = 0x00000005,
PERFMON_SPM_MODE_RESERVED_6              = 0x00000006,
PERFMON_SPM_MODE_RESERVED_7              = 0x00000007,
PERFMON_SPM_MODE_TEST_MODE_0             = 0x00000008,
PERFMON_SPM_MODE_TEST_MODE_1             = 0x00000009,
PERFMON_SPM_MODE_TEST_MODE_2             = 0x0000000a,
} PERFMON_SPM_MODE;

/*
 * SurfaceTiling enum
 */


typedef enum SurfaceTiling {
ARRAY_LINEAR                             = 0x00000000,
ARRAY_TILED                              = 0x00000001,
} SurfaceTiling;

/*
 * SurfaceArray enum
 */


typedef enum SurfaceArray {
ARRAY_1D                                 = 0x00000000,
ARRAY_2D                                 = 0x00000001,
ARRAY_3D                                 = 0x00000002,
ARRAY_3D_SLICE                           = 0x00000003,
} SurfaceArray;

/*
 * ColorArray enum
 */


typedef enum ColorArray {
ARRAY_2D_ALT_COLOR                       = 0x00000000,
ARRAY_2D_COLOR                           = 0x00000001,
ARRAY_3D_SLICE_COLOR                     = 0x00000003,
} ColorArray;

/*
 * DepthArray enum
 */


typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH                       = 0x00000000,
ARRAY_2D_DEPTH                           = 0x00000001,
} DepthArray;

/*
 * ENUM_NUM_SIMD_PER_CU enum
 */


typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU                          = 0x00000004,
} ENUM_NUM_SIMD_PER_CU;

/*
 * DSM_ENABLE_ERROR_INJECT enum
 */


typedef enum DSM_ENABLE_ERROR_INJECT {
DSM_ENABLE_ERROR_INJECT_FED_IN           = 0x00000000,
DSM_ENABLE_ERROR_INJECT_SINGLE           = 0x00000001,
DSM_ENABLE_ERROR_INJECT_DOUBLE           = 0x00000002,
DSM_ENABLE_ERROR_INJECT_DOUBLE_LIMITED   = 0x00000003,
} DSM_ENABLE_ERROR_INJECT;

/*
 * DSM_SELECT_INJECT_DELAY enum
 */


typedef enum DSM_SELECT_INJECT_DELAY {
DSM_SELECT_INJECT_DELAY_NO_DELAY         = 0x00000000,
DSM_SELECT_INJECT_DELAY_DELAY_ERROR      = 0x00000001,
} DSM_SELECT_INJECT_DELAY;

/*
 * SWIZZLE_TYPE_ENUM enum
 */


typedef enum SWIZZLE_TYPE_ENUM {
SW_Z                                     = 0x00000000,
SW_S                                     = 0x00000001,
SW_D                                     = 0x00000002,
SW_R                                     = 0x00000003,
SW_L                                     = 0x00000004,
} SWIZZLE_TYPE_ENUM;

/*
 * TC_MICRO_TILE_MODE enum
 */


typedef enum TC_MICRO_TILE_MODE {
MICRO_TILE_MODE_LINEAR                   = 0x00000000,
MICRO_TILE_MODE_ROTATED                  = 0x00000001,
MICRO_TILE_MODE_STD_2D                   = 0x00000002,
MICRO_TILE_MODE_STD_3D                   = 0x00000003,
MICRO_TILE_MODE_DISPLAY_2D               = 0x00000004,
MICRO_TILE_MODE_DISPLAY_3D               = 0x00000005,
MICRO_TILE_MODE_Z_2D                     = 0x00000006,
MICRO_TILE_MODE_Z_3D                     = 0x00000007,
} TC_MICRO_TILE_MODE;

/*
 * SWIZZLE_MODE_ENUM enum
 */


typedef enum SWIZZLE_MODE_ENUM {
SW_LINEAR                                = 0x00000000,
SW_256B_S                                = 0x00000001,
SW_256B_D                                = 0x00000002,
SW_256B_R                                = 0x00000003,
SW_4KB_Z                                 = 0x00000004,
SW_4KB_S                                 = 0x00000005,
SW_4KB_D                                 = 0x00000006,
SW_4KB_R                                 = 0x00000007,
SW_64KB_Z                                = 0x00000008,
SW_64KB_S                                = 0x00000009,
SW_64KB_D                                = 0x0000000a,
SW_64KB_R                                = 0x0000000b,
SW_VAR_Z                                 = 0x0000000c,
SW_VAR_S                                 = 0x0000000d,
SW_VAR_D                                 = 0x0000000e,
SW_VAR_R                                 = 0x0000000f,
SW_RESERVED_16                           = 0x00000010,
SW_RESERVED_17                           = 0x00000011,
SW_RESERVED_18                           = 0x00000012,
SW_RESERVED_19                           = 0x00000013,
SW_4KB_Z_X                               = 0x00000014,
SW_4KB_S_X                               = 0x00000015,
SW_4KB_D_X                               = 0x00000016,
SW_4KB_R_X                               = 0x00000017,
SW_64KB_Z_X                              = 0x00000018,
SW_64KB_S_X                              = 0x00000019,
SW_64KB_D_X                              = 0x0000001a,
SW_64KB_R_X                              = 0x0000001b,
SW_VAR_Z_X                               = 0x0000001c,
SW_VAR_S_X                               = 0x0000001d,
SW_VAR_D_X                               = 0x0000001e,
SW_VAR_R_X                               = 0x0000001f,
SW_RESERVED_12                           = 0x00000020,
SW_RESERVED_13                           = 0x00000021,
SW_RESERVED_14                           = 0x00000022,
SW_RESERVED_15                           = 0x00000023,
} SWIZZLE_MODE_ENUM;

/*
 * PipeTiling enum
 */


typedef enum PipeTiling {
CONFIG_1_PIPE                            = 0x00000000,
CONFIG_2_PIPE                            = 0x00000001,
CONFIG_4_PIPE                            = 0x00000002,
CONFIG_8_PIPE                            = 0x00000003,
} PipeTiling;

/*
 * BankTiling enum
 */


typedef enum BankTiling {
CONFIG_4_BANK                            = 0x00000000,
CONFIG_8_BANK                            = 0x00000001,
} BankTiling;

/*
 * GroupInterleave enum
 */


typedef enum GroupInterleave {
CONFIG_256B_GROUP                        = 0x00000000,
CONFIG_512B_GROUP                        = 0x00000001,
} GroupInterleave;

/*
 * RowTiling enum
 */


typedef enum RowTiling {
CONFIG_1KB_ROW                           = 0x00000000,
CONFIG_2KB_ROW                           = 0x00000001,
CONFIG_4KB_ROW                           = 0x00000002,
CONFIG_8KB_ROW                           = 0x00000003,
CONFIG_1KB_ROW_OPT                       = 0x00000004,
CONFIG_2KB_ROW_OPT                       = 0x00000005,
CONFIG_4KB_ROW_OPT                       = 0x00000006,
CONFIG_8KB_ROW_OPT                       = 0x00000007,
} RowTiling;

/*
 * BankSwapBytes enum
 */


typedef enum BankSwapBytes {
CONFIG_128B_SWAPS                        = 0x00000000,
CONFIG_256B_SWAPS                        = 0x00000001,
CONFIG_512B_SWAPS                        = 0x00000002,
CONFIG_1KB_SWAPS                         = 0x00000003,
} BankSwapBytes;

/*
 * SampleSplitBytes enum
 */


typedef enum SampleSplitBytes {
CONFIG_1KB_SPLIT                         = 0x00000000,
CONFIG_2KB_SPLIT                         = 0x00000001,
CONFIG_4KB_SPLIT                         = 0x00000002,
CONFIG_8KB_SPLIT                         = 0x00000003,
} SampleSplitBytes;

/*******************************************************
 * AZSTREAM Enums
 *******************************************************/


/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;

/*
 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ  = 0x00000001,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2  = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED  = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4  = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED  = 0x00000004,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED  = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3  = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED  = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED  = 0x00000004,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED  = 0x00000005,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED  = 0x00000006,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED  = 0x00000007,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16  = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20  = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24  = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED  = 0x00000004,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED  = 0x00000005,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;

/*
 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
 */


typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1  = 0x00000000,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2  = 0x00000001,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3  = 0x00000002,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4  = 0x00000003,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5  = 0x00000004,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6  = 0x00000005,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7  = 0x00000006,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8  = 0x00000007,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED  = 0x00000008,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED  = 0x00000009,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED  = 0x0000000a,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED  = 0x0000000b,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED  = 0x0000000c,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED  = 0x0000000d,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED  = 0x0000000e,
OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED  = 0x0000000f,
} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;

/*******************************************************
 * BLNDV Enums
 *******************************************************/


/*
 * BLNDV_CONTROL_BLND_MODE enum
 */


typedef enum BLNDV_CONTROL_BLND_MODE {
BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY = 0x00000000,
BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY  = 0x00000001,
BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE = 0x00000002,
BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE = 0x00000003,
} BLNDV_CONTROL_BLND_MODE;

/*
 * BLNDV_CONTROL_BLND_STEREO_TYPE enum
 */


typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO = 0x00000000,
BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO = 0x00000001,
BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO = 0x00000002,
BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED    = 0x00000003,
} BLNDV_CONTROL_BLND_STEREO_TYPE;

/*
 * BLNDV_CONTROL_BLND_STEREO_POLARITY enum
 */


typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW   = 0x00000000,
BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH  = 0x00000001,
} BLNDV_CONTROL_BLND_STEREO_POLARITY;

/*
 * BLNDV_CONTROL_BLND_FEEDTHROUGH_EN enum
 */


typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE  = 0x00000000,
BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE   = 0x00000001,
} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;

/*
 * BLNDV_CONTROL_BLND_ALPHA_MODE enum
 */


typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x00000000,
BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY = 0x00000002,
BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED     = 0x00000003,
} BLNDV_CONTROL_BLND_ALPHA_MODE;

/*
 * BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY enum
 */


typedef enum BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY {
BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_FALSE  = 0x00000000,
BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY_TRUE  = 0x00000001,
} BLNDV_CONTROL_BLND_ACTIVE_OVERLAP_ONLY;

/*
 * BLNDV_CONTROL_BLND_MULTIPLIED_MODE enum
 */


typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE = 0x00000000,
BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE  = 0x00000001,
} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;

/*
 * BLNDV_SM_CONTROL2_SM_MODE enum
 */


typedef enum BLNDV_SM_CONTROL2_SM_MODE {
BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE   = 0x00000000,
BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
} BLNDV_SM_CONTROL2_SM_MODE;

/*
 * BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE enum
 */


typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE = 0x00000000,
BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE = 0x00000001,
} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;

/*
 * BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE enum
 */


typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE = 0x00000000,
BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE = 0x00000001,
} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;

/*
 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL enum
 */


typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;

/*
 * BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL enum
 */


typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;

/*
 * BLNDV_CONTROL2_PTI_ENABLE enum
 */


typedef enum BLNDV_CONTROL2_PTI_ENABLE {
BLNDV_CONTROL2_PTI_ENABLE_FALSE          = 0x00000000,
BLNDV_CONTROL2_PTI_ENABLE_TRUE           = 0x00000001,
} BLNDV_CONTROL2_PTI_ENABLE;

/*
 * BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN enum
 */


typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE = 0x00000000,
BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE = 0x00000001,
} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;

/*
 * BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN enum
 */


typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE = 0x00000000,
BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE = 0x00000001,
} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;

/*
 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK enum
 */


typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE = 0x00000000,
BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE = 0x00000001,
} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;

/*
 * BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK enum
 */


typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE = 0x00000000,
BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE = 0x00000001,
} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;

/*
 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK enum
 */


typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;

/*
 * BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK enum
 */


typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;

/*
 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK enum
 */


typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;

/*
 * BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK enum
 */


typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;

/*
 * BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK enum
 */


typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;

/*
 * BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK enum
 */


typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;

/*
 * BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE enum
 */


typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x00000000,
BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x00000001,
} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;

/*
 * BLNDV_DEBUG_BLND_CNV_MUX_SELECT enum
 */


typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW      = 0x00000000,
BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH     = 0x00000001,
} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;

/*
 * BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN enum
 */


typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;

/*******************************************************
 * LBV Enums
 *******************************************************/


/*
 * LBV_PIXEL_DEPTH enum
 */


typedef enum LBV_PIXEL_DEPTH {
PIXEL_DEPTH_30BPP                        = 0x00000000,
PIXEL_DEPTH_24BPP                        = 0x00000001,
PIXEL_DEPTH_18BPP                        = 0x00000002,
PIXEL_DEPTH_38BPP                        = 0x00000003,
} LBV_PIXEL_DEPTH;

/*
 * LBV_PIXEL_EXPAN_MODE enum
 */


typedef enum LBV_PIXEL_EXPAN_MODE {
PIXEL_EXPAN_MODE_ZERO_EXP                = 0x00000000,
PIXEL_EXPAN_MODE_DYN_EXP                 = 0x00000001,
} LBV_PIXEL_EXPAN_MODE;

/*
 * LBV_INTERLEAVE_EN enum
 */


typedef enum LBV_INTERLEAVE_EN {
INTERLEAVE_DIS                           = 0x00000000,
INTERLEAVE_EN                            = 0x00000001,
} LBV_INTERLEAVE_EN;

/*
 * LBV_PIXEL_REDUCE_MODE enum
 */


typedef enum LBV_PIXEL_REDUCE_MODE {
PIXEL_REDUCE_MODE_TRUNCATION             = 0x00000000,
PIXEL_REDUCE_MODE_ROUNDING               = 0x00000001,
} LBV_PIXEL_REDUCE_MODE;

/*
 * LBV_DYNAMIC_PIXEL_DEPTH enum
 */


typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
DYNAMIC_PIXEL_DEPTH_36BPP                = 0x00000000,
DYNAMIC_PIXEL_DEPTH_30BPP                = 0x00000001,
} LBV_DYNAMIC_PIXEL_DEPTH;

/*
 * LBV_DITHER_EN enum
 */


typedef enum LBV_DITHER_EN {
DITHER_DIS                               = 0x00000000,
DITHER_EN                                = 0x00000001,
} LBV_DITHER_EN;

/*
 * LBV_DOWNSCALE_PREFETCH_EN enum
 */


typedef enum LBV_DOWNSCALE_PREFETCH_EN {
DOWNSCALE_PREFETCH_DIS                   = 0x00000000,
DOWNSCALE_PREFETCH_EN                    = 0x00000001,
} LBV_DOWNSCALE_PREFETCH_EN;

/*
 * LBV_MEMORY_CONFIG enum
 */


typedef enum LBV_MEMORY_CONFIG {
MEMORY_CONFIG_0                          = 0x00000000,
MEMORY_CONFIG_1                          = 0x00000001,
MEMORY_CONFIG_2                          = 0x00000002,
MEMORY_CONFIG_3                          = 0x00000003,
} LBV_MEMORY_CONFIG;

/*
 * LBV_SYNC_RESET_SEL2 enum
 */


typedef enum LBV_SYNC_RESET_SEL2 {
SYNC_RESET_SEL2_VBLANK                   = 0x00000000,
SYNC_RESET_SEL2_VSYNC                    = 0x00000001,
} LBV_SYNC_RESET_SEL2;

/*
 * LBV_SYNC_DURATION enum
 */


typedef enum LBV_SYNC_DURATION {
SYNC_DURATION_16                         = 0x00000000,
SYNC_DURATION_32                         = 0x00000001,
SYNC_DURATION_64                         = 0x00000002,
SYNC_DURATION_128                        = 0x00000003,
} LBV_SYNC_DURATION;

/*******************************************************
 * CRTC Enums
 *******************************************************/


/*
 * CRTC_CONTROL_CRTC_START_POINT_CNTL enum
 */


typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL = 0x00000000,
CRTC_CONTROL_CRTC_START_POINT_CNTL_DP    = 0x00000001,
} CRTC_CONTROL_CRTC_START_POINT_CNTL;

/*
 * CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL enum
 */


typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP   = 0x00000001,
} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;

/*
 * CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL enum
 */


typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE  = 0x00000000,
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT  = 0x00000001,
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED  = 0x00000002,
CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST  = 0x00000003,
} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;

/*
 * CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY enum
 */


typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
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