// SPDX-License-Identifier: GPL-2.0 /* * Copyright: 2017 Cadence Design Systems, Inc. * * Author: Boris Brezillon <boris.brezillon@bootlin.com> #include <drm/drm_atomic_helper.h>#include <drm/drm_drv.h>#include <drm/drm_probe_helper.h>#include <video/mipi_display.h>#include <linux/clk.h>#include <linux/interrupt.h>#include <linux/iopoll.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_graph.h>#include <linux/platform_device.h>#include <linux/pm_runtime.h>#include <linux/reset.h>#include <linux/phy/phy-mipi-dphy.h>#include "cdns-dsi-core.h" #ifdef CONFIG_DRM_CDNS_DSI_J721E#include "cdns-dsi-j721e.h" #endif #define IP_CONF 0x0#define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26)#define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21)#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16)#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13)#define SDI_IFACE_32 BIT(12)#define INTERNAL_DATAPATH_32 (0 << 10)#define INTERNAL_DATAPATH_16 (1 << 10)#define INTERNAL_DATAPATH_8 (3 << 10)#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))#define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1)#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6)#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0))#define MCTL_MAIN_DATA_CTL 0x4#define TE_MIPI_POLLING_EN BIT(25)#define TE_HW_POLLING_EN BIT(24)#define DISP_EOT_GEN BIT(18)#define HOST_EOT_GEN BIT(17)#define DISP_GEN_CHECKSUM BIT(16)#define DISP_GEN_ECC BIT(15)#define BTA_EN BIT(14)#define READ_EN BIT(13)#define REG_TE_EN BIT(12)#define IF_TE_EN(x) BIT(8 + (x))#define TVG_SEL BIT(6)#define VID_EN BIT(5)#define IF_VID_SELECT(x) ((x) << 2)#define IF_VID_SELECT_MASK GENMASK(3, 2)#define IF_VID_MODE BIT(1)#define LINK_EN BIT(0)#define MCTL_MAIN_PHY_CTL 0x8#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2))#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2))#define HS_INVERT_CLK BIT(17)#define SWAP_PINS_CLK BIT(16)#define HS_SKEWCAL_EN BIT(15)#define WAIT_BURST_TIME(x) ((x) << 10)#define DATA_ULPM_EN(x) BIT(6 + (x))#define CLK_ULPM_EN BIT(5)#define CLK_CONTINUOUS BIT(4)#define DATA_LANE_EN(x) BIT((x) - 1)#define MCTL_MAIN_EN 0xc#define DATA_FORCE_STOP BIT(17)#define CLK_FORCE_STOP BIT(16)#define IF_EN(x) BIT(13 + (x))#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l))#define CLK_LANE_ULPM_REQ BIT(8)#define DATA_LANE_START(x) BIT(4 + (x))#define CLK_LANE_EN BIT(3)#define PLL_START BIT(0)#define MCTL_DPHY_CFG0 0x10#define DPHY_C_RSTB BIT(20)#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16)#define DPHY_PLL_PDN BIT(10)#define DPHY_CMN_PDN BIT(9)#define DPHY_C_PDN BIT(8)#define DPHY_D_PDN(x) GENMASK(3 + (x), 4)#define DPHY_ALL_D_PDN GENMASK(7, 4)#define DPHY_PLL_PSO BIT(1)#define DPHY_CMN_PSO BIT(0)#define MCTL_DPHY_TIMEOUT1 0x14#define HSTX_TIMEOUT(x) ((x) << 4)#define HSTX_TIMEOUT_MAX GENMASK(17, 0)#define CLK_DIV(x) (x)#define CLK_DIV_MAX GENMASK(3, 0)#define MCTL_DPHY_TIMEOUT2 0x18#define LPRX_TIMEOUT(x) (x)#define MCTL_ULPOUT_TIME 0x1c#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9)#define CLK_LANE_ULPOUT_TIME(x) (x)#define MCTL_3DVIDEO_CTL 0x20#define VID_VSYNC_3D_EN BIT(7)#define VID_VSYNC_3D_LR BIT(5)#define VID_VSYNC_3D_SECOND_EN BIT(4)#define VID_VSYNC_3DFORMAT_LINE (0 << 2)#define VID_VSYNC_3DFORMAT_FRAME (1 << 2)#define VID_VSYNC_3DFORMAT_PIXEL (2 << 2)#define VID_VSYNC_3DMODE_OFF 0#define VID_VSYNC_3DMODE_PORTRAIT 1#define VID_VSYNC_3DMODE_LANDSCAPE 2#define MCTL_MAIN_STS 0x24#define MCTL_MAIN_STS_CTL 0x130#define MCTL_MAIN_STS_CLR 0x150#define MCTL_MAIN_STS_FLAG 0x170#define HS_SKEWCAL_DONE BIT(11)#define IF_UNTERM_PKT_ERR(x) BIT(8 + (x))#define LPRX_TIMEOUT_ERR BIT(7)#define HSTX_TIMEOUT_ERR BIT(6)#define DATA_LANE_RDY(l) BIT(2 + (l))#define CLK_LANE_RDY BIT(1)#define PLL_LOCKED BIT(0)#define MCTL_DPHY_ERR 0x28#define MCTL_DPHY_ERR_CTL1 0x148#define MCTL_DPHY_ERR_CLR 0x168#define MCTL_DPHY_ERR_FLAG 0x188#define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l))#define ERR_CONTROL(l) BIT(14 + (l))#define ERR_SYNESC(l) BIT(10 + (l))#define ERR_ESC(l) BIT(6 + (l))#define MCTL_DPHY_ERR_CTL2 0x14c#define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l))#define ERR_CONTROL_EDGE(l) BIT(8 + (l))#define ERR_SYN_ESC_EDGE(l) BIT(4 + (l))#define ERR_ESC_EDGE(l) BIT(0 + (l))#define MCTL_LANE_STS 0x2c#define PPI_C_TX_READY_HS BIT(18)#define DPHY_PLL_LOCK BIT(17)#define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12)#define LANE_STATE_START 0#define LANE_STATE_IDLE 1#define LANE_STATE_WRITE 2#define LANE_STATE_ULPM 3#define LANE_STATE_READ 4#define DATA_LANE_STATE(l, val) \#define CLK_LANE_STATE_HS 2#define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0))#define DSC_MODE_CTL 0x30#define DSC_MODE_EN BIT(0)#define DSC_CMD_SEND 0x34#define DSC_SEND_PPS BIT(0)#define DSC_EXECUTE_QUEUE BIT(1)#define DSC_PPS_WRDAT 0x38#define DSC_MODE_STS 0x3c#define DSC_PPS_DONE BIT(1)#define DSC_EXEC_DONE BIT(2)#define CMD_MODE_CTL 0x70#define IF_LP_EN(x) BIT(9 + (x))#define IF_VCHAN_ID(x, c) ((c) << ((x) * 2))#define CMD_MODE_CTL2 0x74#define TE_TIMEOUT(x) ((x) << 11)#define FILL_VALUE(x) ((x) << 3)#define ARB_IF_WITH_HIGHEST_PRIORITY(x) ((x) << 1)#define ARB_ROUND_ROBIN_MODE BIT(0)#define CMD_MODE_STS 0x78#define CMD_MODE_STS_CTL 0x134#define CMD_MODE_STS_CLR 0x154#define CMD_MODE_STS_FLAG 0x174#define ERR_IF_UNDERRUN(x) BIT(4 + (x))#define ERR_UNWANTED_READ BIT(3)#define ERR_TE_MISS BIT(2)#define ERR_NO_TE BIT(1)#define CSM_RUNNING BIT(0)#define DIRECT_CMD_SEND 0x80#define DIRECT_CMD_MAIN_SETTINGS 0x84#define TRIGGER_VAL(x) ((x) << 25)#define CMD_LP_EN BIT(24)#define CMD_SIZE(x) ((x) << 16)#define CMD_VCHAN_ID(x) ((x) << 14)#define CMD_DATATYPE(x) ((x) << 8)#define CMD_LONG BIT(3)#define WRITE_CMD 0#define READ_CMD 1#define TE_REQ 4#define TRIGGER_REQ 5#define BTA_REQ 6#define DIRECT_CMD_STS 0x88#define DIRECT_CMD_STS_CTL 0x138#define DIRECT_CMD_STS_CLR 0x158#define DIRECT_CMD_STS_FLAG 0x178#define RCVD_ACK_VAL(val) ((val) >> 16)#define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11)#define READ_COMPLETED_WITH_ERR BIT(10)#define BTA_FINISHED BIT(9)#define BTA_COMPLETED BIT(8)#define TE_RCVD BIT(7)#define TRIGGER_RCVD BIT(6)#define ACK_WITH_ERR_RCVD BIT(5)#define ACK_RCVD BIT(4)#define READ_COMPLETED BIT(3)#define TRIGGER_COMPLETED BIT(2)#define WRITE_COMPLETED BIT(1)#define SENDING_CMD BIT(0)#define DIRECT_CMD_STOP_READ 0x8c#define DIRECT_CMD_WRDATA 0x90#define DIRECT_CMD_FIFO_RST 0x94#define DIRECT_CMD_RDDATA 0xa0#define DIRECT_CMD_RD_PROPS 0xa4#define RD_DCS BIT(18)#define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0))#define RD_SIZE(val) ((val) & GENMASK(15, 0))#define DIRECT_CMD_RD_STS 0xa8#define DIRECT_CMD_RD_STS_CTL 0x13c#define DIRECT_CMD_RD_STS_CLR 0x15c#define DIRECT_CMD_RD_STS_FLAG 0x17c#define ERR_EOT_WITH_ERR BIT(8)#define ERR_MISSING_EOT BIT(7)#define ERR_WRONG_LENGTH BIT(6)#define ERR_OVERSIZE BIT(5)#define ERR_RECEIVE BIT(4)#define ERR_UNDECODABLE BIT(3)#define ERR_CHECKSUM BIT(2)#define ERR_UNCORRECTABLE BIT(1)#define ERR_FIXED BIT(0)#define VID_MAIN_CTL 0xb0#define VID_IGNORE_MISS_VSYNC BIT(31)#define VID_FIELD_SW BIT(28)#define VID_INTERLACED_EN BIT(27)#define RECOVERY_MODE(x) ((x) << 25)#define RECOVERY_MODE_NEXT_HSYNC 0#define RECOVERY_MODE_NEXT_STOP_POINT 2#define RECOVERY_MODE_NEXT_VSYNC 3#define REG_BLKEOL_MODE(x) ((x) << 23)#define REG_BLKLINE_MODE(x) ((x) << 21)#define REG_BLK_MODE_NULL_PKT 0#define REG_BLK_MODE_BLANKING_PKT 1#define REG_BLK_MODE_LP 2#define SYNC_PULSE_HORIZONTAL BIT(20)#define SYNC_PULSE_ACTIVE BIT(19)#define BURST_MODE BIT(18)#define VID_PIXEL_MODE_MASK GENMASK(17, 14)#define VID_PIXEL_MODE_RGB565 (0 << 14)#define VID_PIXEL_MODE_RGB666_PACKED (1 << 14)#define VID_PIXEL_MODE_RGB666 (2 << 14)#define VID_PIXEL_MODE_RGB888 (3 << 14)#define VID_PIXEL_MODE_RGB101010 (4 << 14)#define VID_PIXEL_MODE_RGB121212 (5 << 14)#define VID_PIXEL_MODE_YUV420 (8 << 14)#define VID_PIXEL_MODE_YUV422_PACKED (9 << 14)#define VID_PIXEL_MODE_YUV422 (10 << 14)#define VID_PIXEL_MODE_YUV422_24B (11 << 14)#define VID_PIXEL_MODE_DSC_COMP (12 << 14)#define VID_DATATYPE(x) ((x) << 8)#define VID_VIRTCHAN_ID(iface, x) ((x) << (4 + (iface) * 2))#define STOP_MODE(x) ((x) << 2)#define START_MODE(x) (x)#define VID_VSIZE1 0xb4#define VFP_LEN(x) ((x) << 12)#define VBP_LEN(x) ((x) << 6)#define VSA_LEN(x) (x)#define VID_VSIZE2 0xb8#define VACT_LEN(x) (x)#define VID_HSIZE1 0xc0#define HBP_LEN(x) ((x) << 16)#define HSA_LEN(x) (x)#define VID_HSIZE2 0xc4#define HFP_LEN(x) ((x) << 16)#define HACT_LEN(x) (x)#define VID_BLKSIZE1 0xcc#define BLK_EOL_PKT_LEN(x) ((x) << 15)#define BLK_LINE_EVENT_PKT_LEN(x) (x)#define VID_BLKSIZE2 0xd0#define BLK_LINE_PULSE_PKT_LEN(x) (x)#define VID_PKT_TIME 0xd8#define BLK_EOL_DURATION(x) (x)#define VID_DPHY_TIME 0xdc#define REG_WAKEUP_TIME(x) ((x) << 17)#define REG_LINE_DURATION(x) (x)#define VID_ERR_COLOR1 0xe0#define COL_GREEN(x) ((x) << 12)#define COL_RED(x) (x)#define VID_ERR_COLOR2 0xe4#define PAD_VAL(x) ((x) << 12)#define COL_BLUE(x) (x)#define VID_VPOS 0xe8#define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2)#define LINE_POS(val) ((val) & GENMASK(1, 0))#define VID_HPOS 0xec#define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3)#define HORIZ_POS(val) ((val) & GENMASK(2, 0))#define VID_MODE_STS 0xf0#define VID_MODE_STS_CTL 0x140#define VID_MODE_STS_CLR 0x160#define VID_MODE_STS_FLAG 0x180#define VSG_RECOVERY BIT(10)#define ERR_VRS_WRONG_LEN BIT(9)#define ERR_LONG_READ BIT(8)#define ERR_LINE_WRITE BIT(7)#define ERR_BURST_WRITE BIT(6)#define ERR_SMALL_HEIGHT BIT(5)#define ERR_SMALL_LEN BIT(4)#define ERR_MISSING_VSYNC BIT(3)#define ERR_MISSING_HSYNC BIT(2)#define ERR_MISSING_DATA BIT(1)#define VSG_RUNNING BIT(0)#define VID_VCA_SETTING1 0xf4#define BURST_LP BIT(16)#define MAX_BURST_LIMIT(x) (x)#define VID_VCA_SETTING2 0xf8#define MAX_LINE_LIMIT(x) ((x) << 16)#define EXACT_BURST_LIMIT(x) (x)#define TVG_CTL 0xfc#define TVG_STRIPE_SIZE(x) ((x) << 5)#define TVG_MODE_MASK GENMASK(4, 3)#define TVG_MODE_SINGLE_COLOR (0 << 3)#define TVG_MODE_VSTRIPES (2 << 3)#define TVG_MODE_HSTRIPES (3 << 3)#define TVG_STOPMODE_MASK GENMASK(2, 1)#define TVG_STOPMODE_EOF (0 << 1)#define TVG_STOPMODE_EOL (1 << 1)#define TVG_STOPMODE_NOW (2 << 1)#define TVG_RUN BIT(0)#define TVG_IMG_SIZE 0x100#define TVG_NBLINES(x) ((x) << 16)#define TVG_LINE_SIZE(x) (x)#define TVG_COLOR1 0x104#define TVG_COL1_GREEN(x) ((x) << 12)#define TVG_COL1_RED(x) (x)#define TVG_COLOR1_BIS 0x108#define TVG_COL1_BLUE(x) (x)#define TVG_COLOR2 0x10c#define TVG_COL2_GREEN(x) ((x) << 12)#define TVG_COL2_RED(x) (x)#define TVG_COLOR2_BIS 0x110#define TVG_COL2_BLUE(x) (x)#define TVG_STS 0x114#define TVG_STS_CTL 0x144#define TVG_STS_CLR 0x164#define TVG_STS_FLAG 0x184#define TVG_STS_RUNNING BIT(0)#define STS_CTL_EDGE(e) ((e) << 16)#define DPHY_LANES_MAP 0x198#define DAT_REMAP_CFG(b, l) ((l) << ((b) * 8))#define DPI_IRQ_EN 0x1a0#define DPI_IRQ_CLR 0x1a4#define DPI_IRQ_STS 0x1a8#define PIXEL_BUF_OVERFLOW BIT(0)#define DPI_CFG 0x1ac#define DPI_CFG_FIFO_DEPTH(x) ((x) >> 16)#define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0))#define TEST_GENERIC 0x1f0#define TEST_STATUS(x) ((x) >> 16)#define TEST_CTRL(x) (x)#define ID_REG 0x1fc#define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20)#define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12)#define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8)#define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4)#define REV_MINOR(x) ((x) & GENMASK(3, 0))#define DSI_OUTPUT_PORT 0#define DSI_INPUT_PORT(inputid) (1 + (inputid))#define DSI_HBP_FRAME_OVERHEAD 12#define DSI_HSA_FRAME_OVERHEAD 14#define DSI_HFP_FRAME_OVERHEAD 6#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4#define DSI_BLANKING_FRAME_OVERHEAD 6#define DSI_NULL_FRAME_OVERHEAD 6#define DSI_EOT_PKT_SIZE 4struct cdns_dsi_bridge_state {struct drm_bridge_state base;struct cdns_dsi_cfg dsi_cfg;static inline struct cdns_dsi_bridge_state *struct drm_bridge_state *bridge_state)return container_of(bridge_state, struct cdns_dsi_bridge_state, base);static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)return container_of(input, struct cdns_dsi, input);static inline struct cdns_dsi *to_cdns_dsi(struct mipi_dsi_host *host)return container_of(host, struct cdns_dsi, base);static inline struct cdns_dsi_input *struct drm_bridge *bridge)return container_of(bridge, struct cdns_dsi_input, bridge);static unsigned int mode_to_dpi_hfp(const struct drm_display_mode *mode,bool mode_valid_check)if (mode_valid_check)return mode->hsync_start - mode->hdisplay;return mode->crtc_hsync_start - mode->crtc_hdisplay;static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing,unsigned int dpi_bpp,unsigned int dsi_pkt_overhead)unsigned int dsi_timing = DIV_ROUND_UP(dpi_timing * dpi_bpp, 8);if (dsi_timing < dsi_pkt_overhead)else return dsi_timing;static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,const struct drm_display_mode *mode,struct cdns_dsi_cfg *dsi_cfg,bool mode_valid_check)struct cdns_dsi_output *output = &dsi->output;unsigned int tmp;bool sync_pulse = false ;int bpp;sizeof (*dsi_cfg));if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)true ;if (mode_valid_check)else if (sync_pulse) {if (mode_valid_check)else return 0;static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,struct cdns_dsi_cfg *dsi_cfg,struct phy_configure_opts_mipi_dphy *phy_cfg,const struct drm_display_mode *mode,bool mode_valid_check)struct cdns_dsi_output *output = &dsi->output;unsigned long long dlane_bps;unsigned long adj_dsi_htotal;unsigned long dsi_htotal;unsigned long dpi_htotal;unsigned long dpi_hz;unsigned int dsi_hfp_ext;unsigned int lanes = output->dev->lanes;if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)/* * Make sure DSI htotal is aligned on a lane boundary when calculating * the expected data rate. This is done by extending HFP in case of * misalignment. if (dsi_htotal % lanes)unsigned long long )dpi_hz * adj_dsi_htotal;/* data rate in bytes/sec is not an integer, refuse the mode. */ if (do_div(dlane_bps, lanes * dpi_htotal))return -EINVAL;/* data rate was in bytes/sec, convert to bits/sec. */ return 0;static int cdns_dsi_check_conf(struct cdns_dsi *dsi,const struct drm_display_mode *mode,struct cdns_dsi_cfg *dsi_cfg,bool mode_valid_check)struct cdns_dsi_output *output = &dsi->output;struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;unsigned long dsi_hss_hsa_hse_hbp;unsigned int nlanes = output->dev->lanes;int mode_clock = (mode_valid_check ? mode->clock : mode->crtc_clock);int ret;if (ret)return ret;if (ret)return ret;if (ret)return ret;if (ret)return ret;if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)/* * Make sure DPI(HFP) > DSI(HSS+HSA+HSE+HBP) to guarantee that the FIFO * is empty before we start a receiving a new line on the DPI * interface. if ((u64)phy_cfg->hs_clk_rate *return -EINVAL;return 0;static int cdns_dsi_bridge_attach(struct drm_bridge *bridge,struct drm_encoder *encoder,enum drm_bridge_attach_flags flags)struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);struct cdns_dsi *dsi = input_to_dsi(input);struct cdns_dsi_output *output = &dsi->output;if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {"cdns-dsi driver is only compatible with DRM devices supporting atomic updates" );return -ENOTSUPP;return drm_bridge_attach(encoder, output->bridge, bridge,static enum drm_mode_statusstruct drm_bridge *bridge,const struct drm_display_info *info,const struct drm_display_mode *mode)struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);struct cdns_dsi *dsi = input_to_dsi(input);struct cdns_dsi_output *output = &dsi->output;struct cdns_dsi_cfg dsi_cfg;int bpp, ret;/* * VFP_DSI should be less than VFP_DPI and VFP_DSI should be at * least 1. if (mode->vtotal - mode->vsync_end < 2)return MODE_V_ILLEGAL;/* VSA_DSI = VSA_DPI and must be at least 2. */ if (mode->vsync_end - mode->vsync_start < 2)return MODE_V_ILLEGAL;/* HACT must be 32-bits aligned. */ if ((mode->hdisplay * bpp) % 32)return MODE_H_ILLEGAL;true );if (ret)return MODE_BAD;return MODE_OK;static void cdns_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,struct drm_atomic_state *state)struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);struct cdns_dsi *dsi = input_to_dsi(input);/* * The cdns-dsi controller needs to be disabled after it's DPI source * has stopped streaming. If this is not followed, there is a brief * window before DPI source is disabled and after cdns-dsi controller * has been disabled where the DPI stream is still on, but the cdns-dsi * controller is not ready anymore to accept the incoming signals. This * is one of the reasons why a shift in pixel colors is observed on * displays that have cdns-dsi as one of the bridges. * * To mitigate this, disable this bridge from the bridge post_disable() * hook, instead of the bridge _disable() hook. The bridge post_disable() * hook gets called after the CRTC disable, where often many DPI sources * disable their streams. if (dsi->platform_ops && dsi->platform_ops->disable)false ;false ;static void cdns_dsi_hs_init(struct cdns_dsi *dsi)struct cdns_dsi_output *output = &dsi->output;if (dsi->phy_initialized)return ;/* * Power all internal DPHY blocks down and maintain their reset line * asserted before changing the DPHY config. /* Activate the PLL and wait until it's locked. */ /* De-assert data and clock reset lines. */ true ;static void cdns_dsi_init_link(struct cdns_dsi *dsi)struct cdns_dsi_output *output = &dsi->output;unsigned long sysclk_period, ulpout;int i;if (dsi->link_initialized)return ;for (i = 1; i < output->dev->lanes; i++)if (!(output->dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))/* ULPOUT should be set to 1ms and is expressed in sysclk cycles. */ for (i = 0; i < output->dev->lanes; i++)true ;static void cdns_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge,struct drm_atomic_state *state)struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);struct cdns_dsi *dsi = input_to_dsi(input);struct cdns_dsi_output *output = &dsi->output;struct drm_connector_state *conn_state;struct drm_crtc_state *crtc_state;struct cdns_dsi_bridge_state *dsi_state;struct drm_bridge_state *new_bridge_state;struct drm_display_mode *mode;struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;struct drm_connector *connector;unsigned long tx_byte_period;struct cdns_dsi_cfg dsi_cfg;int nlanes;/* * The cdns-dsi controller needs to be enabled before it's DPI source * has begun streaming. If this is not followed, there is a brief window * after DPI source enable and before cdns-dsi controller enable where * the DPI stream is on, but the cdns-dsi controller is not ready to * accept the incoming signals. This is one of the reasons why a shift * in pixel colors is observed on displays that have cdns-dsi as one of * the bridges. * * To mitigate this, enable this bridge from the bridge pre_enable() * hook, instead of the bridge _enable() hook. The bridge pre_enable() * hook gets called before the CRTC enable, where often many DPI sources * enable their streams. if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))return ;if (WARN_ON(!new_bridge_state))return ;if (dsi->platform_ops && dsi->platform_ops->enable)/* * Now that the DSI Link and DSI Phy are initialized, * wait for the CLK and Data Lanes to be ready. for (int i = 0; i < nlanes; i++)if (readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,"Timed Out: DSI-DPhy Clock and Data Lanes not ready.\n" );if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)if (!(output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))if (!(output->dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))/* * Estimated time [in clock cycles] to perform LP->HS on D-PHY. * It is not clear how to calculate this, so for now, * set it to 1/10 of the total number of clocks in a line. /* * HSTX and LPRX timeouts are both expressed in TX byte clk cycles and * both should be set to at least the time it takes to transmit a * frame. for (div = 0; div <= CLK_DIV_MAX; div++) {if (tmp <= HSTX_TIMEOUT_MAX)break ;if (tmp > HSTX_TIMEOUT_MAX)if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO) {switch (output->dev->format) {case MIPI_DSI_FMT_RGB888:break ;case MIPI_DSI_FMT_RGB666:break ;case MIPI_DSI_FMT_RGB666_PACKED:break ;case MIPI_DSI_FMT_RGB565:break ;default :"Unsupported DSI format\n" );return ;if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)if (!(output->dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO)static u32 *cdns_dsi_bridge_get_input_bus_fmts(struct drm_bridge *bridge,struct drm_bridge_state *bridge_state,struct drm_crtc_state *crtc_state,struct drm_connector_state *conn_state,unsigned int *num_input_fmts)struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);struct cdns_dsi *dsi = input_to_dsi(input);struct cdns_dsi_output *output = &dsi->output;sizeof (*input_fmts), GFP_KERNEL);if (!input_fmts)return NULL;if (!input_fmts[0])return NULL;return input_fmts;static int cdns_dsi_bridge_atomic_check(struct drm_bridge *bridge,struct drm_bridge_state *bridge_state,struct drm_crtc_state *crtc_state,struct drm_connector_state *conn_state)struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);struct cdns_dsi *dsi = input_to_dsi(input);struct cdns_dsi_bridge_state *dsi_state = to_cdns_dsi_bridge_state(bridge_state);const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;struct cdns_dsi_cfg *dsi_cfg = &dsi_state->dsi_cfg;return cdns_dsi_check_conf(dsi, adjusted_mode, dsi_cfg, true );static struct drm_bridge_state *struct drm_bridge *bridge)struct cdns_dsi_bridge_state *dsi_state, *old_dsi_state;struct drm_bridge_state *bridge_state;if (WARN_ON(!bridge->base.state))return NULL;sizeof (*dsi_state), GFP_KERNEL);if (!dsi_state)return NULL;sizeof (dsi_state->dsi_cfg));return &dsi_state->base;static void struct drm_bridge *bridge,struct drm_bridge_state *state)struct cdns_dsi_bridge_state *dsi_state;static struct drm_bridge_state *struct drm_bridge *bridge)struct cdns_dsi_bridge_state *dsi_state;sizeof (*dsi_state), GFP_KERNEL);if (!dsi_state)return NULL;sizeof (*dsi_state));return &dsi_state->base;static const struct drm_bridge_funcs cdns_dsi_bridge_funcs = {static int cdns_dsi_attach(struct mipi_dsi_host *host,struct mipi_dsi_device *dev)struct cdns_dsi *dsi = to_cdns_dsi(host);struct cdns_dsi_output *output = &dsi->output;struct cdns_dsi_input *input = &dsi->input;struct drm_bridge *bridge;int ret;/* * We currently do not support connecting several DSI devices to the * same host. In order to support that we'd need the DRM bridge * framework to allow dynamic reconfiguration of the bridge chain. if (output->dev)return -EBUSY;/* * The host <-> device link might be described using an OF-graph * representation, in this case we extract the device of_node from * this representation. if (IS_ERR(bridge)) {"failed to add DSI device %s (err = %d)" ,return ret;/* * The DSI output has been properly configured, we can now safely * register the input to the bridge framework so that it can take place * in a display pipeline. return 0;static int cdns_dsi_detach(struct mipi_dsi_host *host,struct mipi_dsi_device *dev)struct cdns_dsi *dsi = to_cdns_dsi(host);struct cdns_dsi_input *input = &dsi->input;return 0;static irqreturn_t cdns_dsi_interrupt(int irq, void *data)struct cdns_dsi *dsi = data;if (flag) {return ret;static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,const struct mipi_dsi_msg *msg)struct cdns_dsi *dsi = to_cdns_dsi(host);struct mipi_dsi_packet packet;int ret, i, tx_len, rx_len;if (ret < 0)return ret;if (ret)goto out;/* For read operations, the maximum TX len is 2. */ if (rx_len && tx_len > 2) {goto out;/* TX len is limited by the CMD FIFO depth. */ if (tx_len > dsi->direct_cmd_fifo_depth) {goto out;/* RX len is limited by the RX FIFO depth. */ if (rx_len > dsi->rx_fifo_depth) {goto out;if (msg->flags & MIPI_DSI_MSG_USE_LPM)if (mipi_dsi_packet_format_is_long(msg->type))if (rx_len) {else if (msg->flags & MIPI_DSI_MSG_REQ_ACK) {for (i = 0; i < tx_len; i += 4) {const u8 *buf = msg->tx_buf;int j;for (j = 0; j < 4 && j + i < tx_len; j++)/* Clear status flags before sending the command. */ /* We did not receive the events we were waiting for. */ if (!(sts & wait)) {goto out;/* 'READ' or 'WRITE with ACK' failed. */ if (sts & (READ_COMPLETED_WITH_ERR | ACK_WITH_ERR_RCVD)) {goto out;for (i = 0; i < rx_len; i += 4) {int j;for (j = 0; j < 4 && j + i < rx_len; j++)return ret;static const struct mipi_dsi_host_ops cdns_dsi_ops = {static int __maybe_unused cdns_dsi_resume(struct device *dev)struct cdns_dsi *dsi = dev_get_drvdata(dev);return 0;static int __maybe_unused cdns_dsi_suspend(struct device *dev)struct cdns_dsi *dsi = dev_get_drvdata(dev);return 0;static UNIVERSAL_DEV_PM_OPS(cdns_dsi_pm_ops, cdns_dsi_suspend, cdns_dsi_resume,static int cdns_dsi_drm_probe(struct platform_device *pdev)struct cdns_dsi *dsi;struct cdns_dsi_input *input;int ret, irq;struct cdns_dsi, input.bridge,if (IS_ERR(dsi))return PTR_ERR(dsi);if (IS_ERR(dsi->regs))return PTR_ERR(dsi->regs);"dsi_p_clk" );if (IS_ERR(dsi->dsi_p_clk))return PTR_ERR(dsi->dsi_p_clk);"dsi_p_rst" );if (IS_ERR(dsi->dsi_p_rst))return PTR_ERR(dsi->dsi_p_rst);"dsi_sys_clk" );if (IS_ERR(dsi->dsi_sys_clk))return PTR_ERR(dsi->dsi_sys_clk);if (irq < 0)return irq;"dphy" );if (IS_ERR(dsi->dphy))return PTR_ERR(dsi->dphy);if (ret)return ret;if (REV_VENDOR_ID(val) != 0xcad) {"invalid vendor id\n" );goto err_disable_pclk;/* * We only support the DPI input, so force input->id to * CDNS_DPI_INPUT. /* Mask all interrupts before registering the IRQ handler. */ if (ret)goto err_disable_pclk;if (dsi->platform_ops && dsi->platform_ops->init) {if (ret != 0) {"platform initialization failed: %d\n" ,goto err_disable_runtime_pm;if (ret)goto err_deinit_platform;return 0;if (dsi->platform_ops && dsi->platform_ops->deinit)return ret;static void cdns_dsi_drm_remove(struct platform_device *pdev)struct cdns_dsi *dsi = platform_get_drvdata(pdev);if (dsi->platform_ops && dsi->platform_ops->deinit)static const struct of_device_id cdns_dsi_of_match[] = {"cdns,dsi" },#ifdef CONFIG_DRM_CDNS_DSI_J721E"ti,j721e-dsi" , .data = &dsi_ti_j721e_ops, },#endif static struct platform_driver cdns_dsi_platform_driver = {"cdns-dsi" ,"Boris Brezillon " );"Cadence DSI driver" );"GPL" );"platform:cdns-dsi" );
Messung V0.5 C=92 H=93 G=92
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