/* Unlike most Intel display engines, on Cedarview the DPLL registers * are behind this sideband bus. They must be programmed while the * DPLL reference clock is on in the DPLL control register, but before * the DPLL is enabled in the DPLL control register.
*/ staticint
cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc, struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
{ struct gma_crtc *gma_crtc = to_gma_crtc(crtc); int pipe = gma_crtc->pipe;
u32 m, n_vco, p; int ret = 0; int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B; int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
u32 ref_value;
u32 lane_reg, lane_value;
/* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
ref_value = 0x68A701;
cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
/* We don't know what the other fields of these regs are, so * leave them in place.
*/ /* * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk * for the pipe A/B. Display spec 1.06 has wrong definition. * Correct definition is like below: * * refclka mean use clock from same PLL * * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll * * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA *
*/
ret = cdv_sb_read(dev, ref_sfr, &ref_value); if (ret) return ret;
ref_value &= ~(REF_CLK_MASK);
/* use DPLL_A for pipeB on CRT/HDMI */ if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
DRM_DEBUG_KMS("use DPLLA for pipe B\n");
ref_value |= REF_CLK_DPLLA;
} else {
DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
ref_value |= REF_CLK_DPLL;
}
ret = cdv_sb_write(dev, ref_sfr, ref_value); if (ret) return ret;
ret = cdv_sb_read(dev, SB_M(pipe), &m); if (ret) return ret;
m &= ~SB_M_DIVIDER_MASK;
m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
ret = cdv_sb_write(dev, SB_M(pipe), m); if (ret) return ret;
ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco); if (ret) return ret;
/* Follow the BIOS to program the N_DIVIDER REG */
n_vco &= 0xFFFF;
n_vco |= 0x107;
n_vco &= ~(SB_N_VCO_SEL_MASK |
SB_N_DIVIDER_MASK |
SB_N_CB_TUNE_MASK);
ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco); if (ret) return ret;
ret = cdv_sb_read(dev, SB_P(pipe), &p); if (ret) return ret;
p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); switch (clock->p2) { case 5:
p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); break; case 10:
p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); break; case 14:
p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); break; case 7:
p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER); break; default:
DRM_ERROR("Bad P2 clock: %d\n", clock->p2); return -EINVAL;
}
ret = cdv_sb_write(dev, SB_P(pipe), p); if (ret) return ret;
/* Cedarview workaround to write ovelay plane, which force to leave * MAX_FIFO state.
*/
REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
REG_READ(OV_OVADD);
/* * Return the pipe currently connected to the panel fitter, * or -1 if the panel fitter is not present or not in use
*/ staticint cdv_intel_panel_fitter_pipe(struct drm_device *dev)
{
u32 pfit_control;
pfit_control = REG_READ(PFIT_CONTROL);
/* See if the panel fitter is in use */ if ((pfit_control & PFIT_ENABLE) == 0) return -1; return (pfit_control >> 29) & 0x3;
}
if (!connector->encoder
|| connector->encoder->crtc != crtc) continue;
ddi_select = gma_encoder->ddi_select; switch (gma_encoder->type) { case INTEL_OUTPUT_LVDS:
is_lvds = true; break; case INTEL_OUTPUT_ANALOG: case INTEL_OUTPUT_HDMI: break; case INTEL_OUTPUT_DISPLAYPORT:
is_dp = true; break; case INTEL_OUTPUT_EDP:
is_edp = true; break; default:
drm_connector_list_iter_end(&conn_iter);
DRM_ERROR("invalid output type.\n"); return 0;
}
break;
}
drm_connector_list_iter_end(&conn_iter);
if (dev_priv->dplla_96mhz) /* low-end sku, 96/100 mhz */
refclk = 96000; else /* high-end sku, 27/100 mhz */
refclk = 27000; if (is_dp || is_edp) { /* * Based on the spec the low-end SKU has only CRT/LVDS. So it is * unnecessary to consider it for DP/eDP. * On the high-end SKU, it will use the 27/100M reference clk * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise * it will be 27MHz. From the VBIOS code it seems that the pipe A choose * 27MHz for DP/eDP while the Pipe B chooses the 100MHz.
*/ if (pipe == 0)
refclk = 27000; else
refclk = 100000;
}
/* The LVDS pin pair needs to be on before the DPLLs are enabled. * This is an exception to the general rule that mode_set doesn't turn * things on.
*/ if (is_lvds) {
u32 lvds = REG_READ(LVDS);
lvds |=
LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
LVDS_PIPEB_SELECT; /* Set the B0-B3 data pairs corresponding to * whether we're going to * set the DPLLs for dual-channel mode or not.
*/ if (clock.p2 == 7)
lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; else
lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
/* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) * appropriately here, but we need to look more * thoroughly into how panels behave in the two modes.
*/
REG_WRITE(LVDS, lvds);
REG_READ(LVDS);
}
dpll |= DPLL_VCO_ENABLE;
/* Disable the panel fitter if it was on our pipe */ if (cdv_intel_panel_fitter_pipe(dev) == pipe)
REG_WRITE(PFIT_CONTROL, 0);
/* XXX: It would be nice to validate the clocks, but we can't reuse * i830PllIsValid() because it relies on the xf86_config connector * configuration being accurate, which it isn't necessarily.
*/
return clock.dot;
}
/** Returns the currently programmed mode of the given pipe. */ struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev, struct drm_crtc *crtc)
{ struct gma_crtc *gma_crtc = to_gma_crtc(crtc); int pipe = gma_crtc->pipe; struct drm_psb_private *dev_priv = to_drm_psb_private(dev); struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; conststruct psb_offset *map = &dev_priv->regmap[pipe]; struct drm_display_mode *mode; int htot; int hsync; int vtot; int vsync;
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