if (HAS_DDI(display)) { /* * DDI does not have a specific FDI_TX register. * * FDI is never fed from EDP transcoder * so pipe->transcoder cast is fine here.
*/ enum transcoder cpu_transcoder = (enum transcoder)pipe;
cur_state = intel_de_read(display,
TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE;
} else {
cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE;
}
INTEL_DISPLAY_STATE_WARN(display, cur_state != state, "FDI TX state assertion failure (expected %s, current %s)\n",
str_on_off(state), str_on_off(cur_state));
}
/* ILK FDI PLL is always enabled */ if (display->platform.ironlake) return;
/* On Haswell, DDI ports are responsible for the FDI PLL setup */ if (HAS_DDI(display)) return;
cur_state = intel_de_read(display, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE;
INTEL_DISPLAY_STATE_WARN(display, !cur_state, "FDI TX PLL assertion failure, should be active but is disabled\n");
}
/** * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs * @state: intel atomic state * * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is * known to affect the available FDI BW for the former CRTC. In practice this * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by * CRTC C) and CRTC C is getting disabled. * * Returns 0 in case of success, or a negative error code otherwise.
*/ int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state)
{ struct intel_display *display = to_intel_display(state); conststruct intel_crtc_state *old_crtc_state; conststruct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc;
if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3) return 0;
int intel_fdi_link_freq(struct intel_display *display, conststruct intel_crtc_state *pipe_config)
{ if (HAS_DDI(display)) return pipe_config->port_clock; /* SPLL */ else return display->fdi.pll_freq;
}
/** * intel_fdi_compute_pipe_bpp - compute pipe bpp limited by max link bpp * @crtc_state: the crtc state * * Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can * call this function during state computation in the simple case where the * link bpp will always match the pipe bpp. This is the case for all non-DP * encoders, while DP encoders will use a link bpp lower than pipe bpp in case * of DSC compression. * * Returns %true in case of success, %false if pipe bpp would need to be * reduced below its valid range.
*/ bool intel_fdi_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
{ int pipe_bpp = min(crtc_state->pipe_bpp,
fxp_q4_to_int(crtc_state->max_link_bpp_x16));
/* FDI is a binary signal running at ~2.7GHz, encoding * each output octet as 10 bits. The actual frequency * is stored as a divider into a 100MHz clock, and the * mode pixel clock is stored in units of 1KHz. * Hence the bw of each lane in terms of the mode signal * is:
*/
link_bw = intel_fdi_link_freq(display, pipe_config);
fdi_dotclock = adjusted_mode->crtc_clock;
lane = ilk_get_lanes_required(fdi_dotclock, link_bw,
pipe_config->pipe_bpp);
ret = ilk_check_fdi_lanes(display, crtc->pipe, pipe_config,
&pipe_to_reduce); if (ret != -EINVAL) return ret;
ret = intel_link_bw_reduce_bpp(state, limits,
BIT(pipe_to_reduce), "FDI link BW");
return ret ? : -EAGAIN;
}
/** * intel_fdi_atomic_check_link - check all modeset FDI link configuration * @state: intel atomic state * @limits: link BW limits * * Check the link configuration for all modeset FDI outputs. If the * configuration is invalid @limits will be updated if possible to * reduce the total BW, after which the configuration for all CRTCs in * @state must be recomputed with the updated @limits. * * Returns: * - 0 if the configuration is valid * - %-EAGAIN, if the configuration is invalid and @limits got updated * with fallback values with which the configuration of all CRTCs * in @state must be recomputed * - Other negative error, if the configuration is invalid without a * fallback possibility, or the check failed for another reason
*/ int intel_fdi_atomic_check_link(struct intel_atomic_state *state, struct intel_link_bw_limits *limits)
{ struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; int i;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { int ret;
if (!crtc_state->has_pch_encoder ||
!intel_crtc_needs_modeset(crtc_state) ||
!crtc_state->hw.enable) continue;
ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits); if (ret) return ret;
}
/* The FDI link training functions for ILK/Ibexpeak. */ staticvoid ilk_fdi_link_train(struct intel_crtc *crtc, conststruct intel_crtc_state *crtc_state)
{ struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe;
i915_reg_t reg;
u32 temp, tries;
/* * Write the TU size bits before fdi link training, so that error * detection works.
*/
intel_de_write(display, FDI_RX_TUSIZE1(pipe),
intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
/* FDI needs bits from pipe first */
assert_transcoder_enabled(display, crtc_state->cpu_transcoder);
/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
for train result */
reg = FDI_RX_IMR(pipe);
temp = intel_de_read(display, reg);
temp &= ~FDI_RX_SYMBOL_LOCK;
temp &= ~FDI_RX_BIT_LOCK;
intel_de_write(display, reg, temp);
intel_de_read(display, reg);
udelay(150);
/* The FDI link training functions for SNB/Cougarpoint. */ staticvoid gen6_fdi_link_train(struct intel_crtc *crtc, conststruct intel_crtc_state *crtc_state)
{ struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe;
i915_reg_t reg;
u32 temp, i, retry;
/* * Write the TU size bits before fdi link training, so that error * detection works.
*/
intel_de_write(display, FDI_RX_TUSIZE1(pipe),
intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
for train result */
reg = FDI_RX_IMR(pipe);
temp = intel_de_read(display, reg);
temp &= ~FDI_RX_SYMBOL_LOCK;
temp &= ~FDI_RX_BIT_LOCK;
intel_de_write(display, reg, temp);
/* Manual link training for Ivy Bridge A0 parts */ staticvoid ivb_manual_fdi_link_train(struct intel_crtc *crtc, conststruct intel_crtc_state *crtc_state)
{ struct intel_display *display = to_intel_display(crtc); enum pipe pipe = crtc->pipe;
i915_reg_t reg;
u32 temp, i, j;
ivb_update_fdi_bc_bifurcation(crtc_state);
/* * Write the TU size bits before fdi link training, so that error * detection works.
*/
intel_de_write(display, FDI_RX_TUSIZE1(pipe),
intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK);
/* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
for train result */
reg = FDI_RX_IMR(pipe);
temp = intel_de_read(display, reg);
temp &= ~FDI_RX_SYMBOL_LOCK;
temp &= ~FDI_RX_BIT_LOCK;
intel_de_write(display, reg, temp);
intel_de_posting_read(display, reg);
udelay(150);
drm_dbg_kms(display->drm, "FDI_RX_IIR before link train 0x%x\n",
intel_de_read(display, FDI_RX_IIR(pipe)));
/* Try each vswing and preemphasis setting twice before moving on */ for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { /* disable first in case we need to retry */
reg = FDI_TX_CTL(pipe);
temp = intel_de_read(display, reg);
temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
temp &= ~FDI_TX_ENABLE;
intel_de_write(display, reg, temp);
/* Starting with Haswell, different DDI ports can work in FDI mode for * connection to the PCH-located connectors. For this, it is necessary to train * both the DDI port and PCH receiver for the desired DDI buffer settings. * * The recommended port to work in FDI mode is DDI E, which we use here. Also, * please note that when FDI mode is active on DDI E, it shares 2 lines with * DDI A (which is used for eDP)
*/ void hsw_fdi_link_train(struct intel_encoder *encoder, conststruct intel_crtc_state *crtc_state)
{ struct intel_display *display = to_intel_display(crtc_state);
u32 temp, i, rx_ctl_val; int n_entries;
/* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the * mode set "sequence for CRT port" document: * - TP1 to TP2 time with the default value * - FDI delay to 90h * * WaFDIAutoLinkSetTimingOverrride:hsw
*/
intel_de_write(display, FDI_RX_MISC(PIPE_A),
FDI_RX_PWRDN_LANE1_VAL(2) |
FDI_RX_PWRDN_LANE0_VAL(2) |
FDI_RX_TP1_TO_TP2_48 |
FDI_RX_FDI_DELAY_90);
/* Start the training iterating through available voltages and emphasis,
* testing each value twice. */ for (i = 0; i < n_entries * 2; i++) { /* Configure DP_TP_CTL with auto-training */
intel_de_write(display, DP_TP_CTL(PORT_E),
DP_TP_CTL_FDI_AUTOTRAIN |
DP_TP_CTL_ENHANCED_FRAME_ENABLE |
DP_TP_CTL_LINK_TRAIN_PAT1 |
DP_TP_CTL_ENABLE);
/* Configure and enable DDI_BUF_CTL for DDI E with next voltage. * DDI E does not support port reversal, the functionality is * achieved on the PCH side in FDI_RX_CTL, so no need to set the
* port reversal bit */
intel_de_write(display, DDI_BUF_CTL(PORT_E),
DDI_BUF_CTL_ENABLE |
((crtc_state->fdi_lanes - 1) << 1) |
DDI_BUF_TRANS_SELECT(i / 2));
intel_de_posting_read(display, DDI_BUF_CTL(PORT_E));
udelay(600);
/* Program PCH FDI Receiver TU */
intel_de_write(display, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
temp = intel_de_read(display, DP_TP_STATUS(PORT_E)); if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
drm_dbg_kms(display->drm, "FDI link training done on step %d\n", i); break;
}
/* * Leave things enabled even if we failed to train FDI. * Results in less fireworks from the state checker.
*/ if (i == n_entries * 2 - 1) {
drm_err(display->drm, "FDI link training failed!\n"); break;
}
/* * Bspec lists this as both step 13 (before DDI_BUF_CTL disable) * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN, * step 13 is the correct place for it. Step 18 is where it was * originally before the BUN.
*/
intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
intel_de_rmw(display, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
intel_wait_ddi_buf_idle(display, PORT_E);
intel_ddi_disable_clock(encoder);
intel_de_rmw(display, FDI_RX_MISC(PIPE_A),
FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
intel_de_rmw(display, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
}
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