Quelle  intel_hdmi.c   Sprache: C

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 * Eric Anholt <eric@anholt.net>
 * Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/delay.h>
#include <linux/hdmi.h>
#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/string_helpers.h>

#include <drm/display/drm_hdcp_helper.h>
#include <drm/display/drm_hdmi_helper.h>
#include <drm/display/drm_scdc_helper.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
#include <drm/intel/intel_lpe_audio.h>
#include <media/cec-notifier.h>

#include "g4x_hdmi.h"
#include "i915_utils.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_driver.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_gmbus.h"
#include "intel_hdcp.h"
#include "intel_hdcp_regs.h"
#include "intel_hdcp_shim.h"
#include "intel_hdmi.h"
#include "intel_lspcon.h"
#include "intel_panel.h"
#include "intel_pfit.h"
#include "intel_snps_phy.h"
#include "intel_vrr.h"

static void
assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{
 struct intel_display *display = to_intel_display(intel_hdmi);
 u32 enabled_bits;

 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;

 drm_WARN(display->drm,
   intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits,
   "HDMI port enabled, expecting disabled\n");
}

static void
assert_hdmi_transcoder_func_disabled(struct intel_display *display,
         enum transcoder cpu_transcoder)
{
 drm_WARN(display->drm,
   intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
   TRANS_DDI_FUNC_ENABLE,
   "HDMI transcoder function enabled, expecting disabled\n");
}

static u32 g4x_infoframe_index(unsigned int type)
{
 switch (type) {
 case HDMI_PACKET_TYPE_GAMUT_METADATA:
  return VIDEO_DIP_SELECT_GAMUT;
 case HDMI_INFOFRAME_TYPE_AVI:
  return VIDEO_DIP_SELECT_AVI;
 case HDMI_INFOFRAME_TYPE_SPD:
  return VIDEO_DIP_SELECT_SPD;
 case HDMI_INFOFRAME_TYPE_VENDOR:
  return VIDEO_DIP_SELECT_VENDOR;
 default:
  MISSING_CASE(type);
  return 0;
 }
}

static u32 g4x_infoframe_enable(unsigned int type)
{
 switch (type) {
 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
  return VIDEO_DIP_ENABLE_GCP;
 case HDMI_PACKET_TYPE_GAMUT_METADATA:
  return VIDEO_DIP_ENABLE_GAMUT;
 case DP_SDP_VSC:
  return 0;
 case DP_SDP_ADAPTIVE_SYNC:
  return 0;
 case HDMI_INFOFRAME_TYPE_AVI:
  return VIDEO_DIP_ENABLE_AVI;
 case HDMI_INFOFRAME_TYPE_SPD:
  return VIDEO_DIP_ENABLE_SPD;
 case HDMI_INFOFRAME_TYPE_VENDOR:
  return VIDEO_DIP_ENABLE_VENDOR;
 case HDMI_INFOFRAME_TYPE_DRM:
  return 0;
 default:
  MISSING_CASE(type);
  return 0;
 }
}

static u32 hsw_infoframe_enable(unsigned int type)
{
 switch (type) {
 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
  return VIDEO_DIP_ENABLE_GCP_HSW;
 case HDMI_PACKET_TYPE_GAMUT_METADATA:
  return VIDEO_DIP_ENABLE_GMP_HSW;
 case DP_SDP_VSC:
  return VIDEO_DIP_ENABLE_VSC_HSW;
 case DP_SDP_ADAPTIVE_SYNC:
  return VIDEO_DIP_ENABLE_AS_ADL;
 case DP_SDP_PPS:
  return VDIP_ENABLE_PPS;
 case HDMI_INFOFRAME_TYPE_AVI:
  return VIDEO_DIP_ENABLE_AVI_HSW;
 case HDMI_INFOFRAME_TYPE_SPD:
  return VIDEO_DIP_ENABLE_SPD_HSW;
 case HDMI_INFOFRAME_TYPE_VENDOR:
  return VIDEO_DIP_ENABLE_VS_HSW;
 case HDMI_INFOFRAME_TYPE_DRM:
  return VIDEO_DIP_ENABLE_DRM_GLK;
 default:
  MISSING_CASE(type);
  return 0;
 }
}

static i915_reg_t
hsw_dip_data_reg(struct intel_display *display,
   enum transcoder cpu_transcoder,
   unsigned int type,
   int i)
{
 switch (type) {
 case HDMI_PACKET_TYPE_GAMUT_METADATA:
  return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i);
 case DP_SDP_VSC:
  return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i);
 case DP_SDP_ADAPTIVE_SYNC:
  return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i);
 case DP_SDP_PPS:
  return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i);
 case HDMI_INFOFRAME_TYPE_AVI:
  return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i);
 case HDMI_INFOFRAME_TYPE_SPD:
  return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i);
 case HDMI_INFOFRAME_TYPE_VENDOR:
  return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i);
 case HDMI_INFOFRAME_TYPE_DRM:
  return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i);
 default:
  MISSING_CASE(type);
  return INVALID_MMIO_REG;
 }
}

static int hsw_dip_data_size(struct intel_display *display,
        unsigned int type)
{
 switch (type) {
 case DP_SDP_VSC:
  return VIDEO_DIP_VSC_DATA_SIZE;
 case DP_SDP_ADAPTIVE_SYNC:
  return VIDEO_DIP_ASYNC_DATA_SIZE;
 case DP_SDP_PPS:
  return VIDEO_DIP_PPS_DATA_SIZE;
 case HDMI_PACKET_TYPE_GAMUT_METADATA:
  if (DISPLAY_VER(display) >= 11)
   return VIDEO_DIP_GMP_DATA_SIZE;
  else
   return VIDEO_DIP_DATA_SIZE;
 default:
  return VIDEO_DIP_DATA_SIZE;
 }
}

static void g4x_write_infoframe(struct intel_encoder *encoder,
    const struct intel_crtc_state *crtc_state,
    unsigned int type,
    const void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 const u32 *data = frame;
 u32 val = intel_de_read(display, VIDEO_DIP_CTL);
 int i;

 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
   "Writing DIP with CTL reg disabled\n");

 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 val |= g4x_infoframe_index(type);

 val &= ~g4x_infoframe_enable(type);

 intel_de_write(display, VIDEO_DIP_CTL, val);

 for (i = 0; i < len; i += 4) {
  intel_de_write(display, VIDEO_DIP_DATA, *data);
  data++;
 }
 /* Write every possible data byte to force correct ECC calculation. */
 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  intel_de_write(display, VIDEO_DIP_DATA, 0);

 val |= g4x_infoframe_enable(type);
 val &= ~VIDEO_DIP_FREQ_MASK;
 val |= VIDEO_DIP_FREQ_VSYNC;

 intel_de_write(display, VIDEO_DIP_CTL, val);
 intel_de_posting_read(display, VIDEO_DIP_CTL);
}

static void g4x_read_infoframe(struct intel_encoder *encoder,
          const struct intel_crtc_state *crtc_state,
          unsigned int type,
          void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 u32 *data = frame;
 int i;

 intel_de_rmw(display, VIDEO_DIP_CTL,
       VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));

 for (i = 0; i < len; i += 4)
  *data++ = intel_de_read(display, VIDEO_DIP_DATA);
}

static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
      const struct intel_crtc_state *pipe_config)
{
 struct intel_display *display = to_intel_display(encoder);
 u32 val = intel_de_read(display, VIDEO_DIP_CTL);

 if ((val & VIDEO_DIP_ENABLE) == 0)
  return 0;

 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
  return 0;

 return val & (VIDEO_DIP_ENABLE_AVI |
        VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
}

static void ibx_write_infoframe(struct intel_encoder *encoder,
    const struct intel_crtc_state *crtc_state,
    unsigned int type,
    const void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 const u32 *data = frame;
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 u32 val = intel_de_read(display, reg);
 int i;

 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
   "Writing DIP with CTL reg disabled\n");

 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 val |= g4x_infoframe_index(type);

 val &= ~g4x_infoframe_enable(type);

 intel_de_write(display, reg, val);

 for (i = 0; i < len; i += 4) {
  intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
          *data);
  data++;
 }
 /* Write every possible data byte to force correct ECC calculation. */
 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);

 val |= g4x_infoframe_enable(type);
 val &= ~VIDEO_DIP_FREQ_MASK;
 val |= VIDEO_DIP_FREQ_VSYNC;

 intel_de_write(display, reg, val);
 intel_de_posting_read(display, reg);
}

static void ibx_read_infoframe(struct intel_encoder *encoder,
          const struct intel_crtc_state *crtc_state,
          unsigned int type,
          void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 u32 *data = frame;
 int i;

 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
       VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));

 for (i = 0; i < len; i += 4)
  *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
}

static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
      const struct intel_crtc_state *pipe_config)
{
 struct intel_display *display = to_intel_display(encoder);
 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 u32 val = intel_de_read(display, reg);

 if ((val & VIDEO_DIP_ENABLE) == 0)
  return 0;

 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
  return 0;

 return val & (VIDEO_DIP_ENABLE_AVI |
        VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
        VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
}

static void cpt_write_infoframe(struct intel_encoder *encoder,
    const struct intel_crtc_state *crtc_state,
    unsigned int type,
    const void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 const u32 *data = frame;
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 u32 val = intel_de_read(display, reg);
 int i;

 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
   "Writing DIP with CTL reg disabled\n");

 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 val |= g4x_infoframe_index(type);

 /* The DIP control register spec says that we need to update the AVI
 * infoframe without clearing its enable bit */
 if (type != HDMI_INFOFRAME_TYPE_AVI)
  val &= ~g4x_infoframe_enable(type);

 intel_de_write(display, reg, val);

 for (i = 0; i < len; i += 4) {
  intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe),
          *data);
  data++;
 }
 /* Write every possible data byte to force correct ECC calculation. */
 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0);

 val |= g4x_infoframe_enable(type);
 val &= ~VIDEO_DIP_FREQ_MASK;
 val |= VIDEO_DIP_FREQ_VSYNC;

 intel_de_write(display, reg, val);
 intel_de_posting_read(display, reg);
}

static void cpt_read_infoframe(struct intel_encoder *encoder,
          const struct intel_crtc_state *crtc_state,
          unsigned int type,
          void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 u32 *data = frame;
 int i;

 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe),
       VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));

 for (i = 0; i < len; i += 4)
  *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe));
}

static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
      const struct intel_crtc_state *pipe_config)
{
 struct intel_display *display = to_intel_display(encoder);
 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe));

 if ((val & VIDEO_DIP_ENABLE) == 0)
  return 0;

 return val & (VIDEO_DIP_ENABLE_AVI |
        VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
        VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
}

static void vlv_write_infoframe(struct intel_encoder *encoder,
    const struct intel_crtc_state *crtc_state,
    unsigned int type,
    const void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 const u32 *data = frame;
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
 u32 val = intel_de_read(display, reg);
 int i;

 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE),
   "Writing DIP with CTL reg disabled\n");

 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 val |= g4x_infoframe_index(type);

 val &= ~g4x_infoframe_enable(type);

 intel_de_write(display, reg, val);

 for (i = 0; i < len; i += 4) {
  intel_de_write(display,
          VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
  data++;
 }
 /* Write every possible data byte to force correct ECC calculation. */
 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
  intel_de_write(display,
          VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);

 val |= g4x_infoframe_enable(type);
 val &= ~VIDEO_DIP_FREQ_MASK;
 val |= VIDEO_DIP_FREQ_VSYNC;

 intel_de_write(display, reg, val);
 intel_de_posting_read(display, reg);
}

static void vlv_read_infoframe(struct intel_encoder *encoder,
          const struct intel_crtc_state *crtc_state,
          unsigned int type,
          void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 u32 *data = frame;
 int i;

 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe),
       VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));

 for (i = 0; i < len; i += 4)
  *data++ = intel_de_read(display,
            VLV_TVIDEO_DIP_DATA(crtc->pipe));
}

static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
      const struct intel_crtc_state *pipe_config)
{
 struct intel_display *display = to_intel_display(encoder);
 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe));

 if ((val & VIDEO_DIP_ENABLE) == 0)
  return 0;

 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
  return 0;

 return val & (VIDEO_DIP_ENABLE_AVI |
        VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
        VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
}

void hsw_write_infoframe(struct intel_encoder *encoder,
    const struct intel_crtc_state *crtc_state,
    unsigned int type,
    const void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 const u32 *data = frame;
 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder);
 int data_size;
 int i;
 u32 val = intel_de_read(display, ctl_reg);

 data_size = hsw_dip_data_size(display, type);

 drm_WARN_ON(display->drm, len > data_size);

 val &= ~hsw_infoframe_enable(type);
 intel_de_write(display, ctl_reg, val);

 for (i = 0; i < len; i += 4) {
  intel_de_write(display,
          hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),
          *data);
  data++;
 }
 /* Write every possible data byte to force correct ECC calculation. */
 for (; i < data_size; i += 4)
  intel_de_write(display,
          hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2),
          0);

 /* Wa_14013475917 */
 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr &&
       !crtc_state->has_panel_replay && type == DP_SDP_VSC))
  val |= hsw_infoframe_enable(type);

 if (type == DP_SDP_VSC)
  val |= VSC_DIP_HW_DATA_SW_HEA;

 intel_de_write(display, ctl_reg, val);
 intel_de_posting_read(display, ctl_reg);
}

void hsw_read_infoframe(struct intel_encoder *encoder,
   const struct intel_crtc_state *crtc_state,
   unsigned int type, void *frame, ssize_t len)
{
 struct intel_display *display = to_intel_display(encoder);
 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 u32 *data = frame;
 int i;

 for (i = 0; i < len; i += 4)
  *data++ = intel_de_read(display,
     hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2));
}

static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
      const struct intel_crtc_state *pipe_config)
{
 struct intel_display *display = to_intel_display(encoder);
 u32 val = intel_de_read(display,
    HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder));
 u32 mask;

 mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);

 if (DISPLAY_VER(display) >= 10)
  mask |= VIDEO_DIP_ENABLE_DRM_GLK;

 if (HAS_AS_SDP(display))
  mask |= VIDEO_DIP_ENABLE_AS_ADL;

 return val & mask;
}

static const u8 infoframe_type_to_idx[] = {
 HDMI_PACKET_TYPE_GENERAL_CONTROL,
 HDMI_PACKET_TYPE_GAMUT_METADATA,
 DP_SDP_VSC,
 DP_SDP_ADAPTIVE_SYNC,
 HDMI_INFOFRAME_TYPE_AVI,
 HDMI_INFOFRAME_TYPE_SPD,
 HDMI_INFOFRAME_TYPE_VENDOR,
 HDMI_INFOFRAME_TYPE_DRM,
};

u32 intel_hdmi_infoframe_enable(unsigned int type)
{
 int i;

 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
  if (infoframe_type_to_idx[i] == type)
   return BIT(i);
 }

 return 0;
}

u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
      const struct intel_crtc_state *crtc_state)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 u32 val, ret = 0;
 int i;

 val = dig_port->infoframes_enabled(encoder, crtc_state);

 /* map from hardware bits to dip idx */
 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
  unsigned int type = infoframe_type_to_idx[i];

  if (HAS_DDI(display)) {
   if (val & hsw_infoframe_enable(type))
    ret |= BIT(i);
  } else {
   if (val & g4x_infoframe_enable(type))
    ret |= BIT(i);
  }
 }

 return ret;
}

/*
 * The data we write to the DIP data buffer registers is 1 byte bigger than the
 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 * used for both technologies.
 *
 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 * DW1:       DB3       | DB2 | DB1 | DB0
 * DW2:       DB7       | DB6 | DB5 | DB4
 * DW3: ...
 *
 * (HB is Header Byte, DB is Data Byte)
 *
 * The hdmi pack() functions don't know about that hardware specific hole so we
 * trick them by giving an offset into the buffer and moving back the header
 * bytes by one.
 */
static void intel_write_infoframe(struct intel_encoder *encoder,
      const struct intel_crtc_state *crtc_state,
      enum hdmi_infoframe_type type,
      const union hdmi_infoframe *frame)
{
 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 u8 buffer[VIDEO_DIP_DATA_SIZE];
 ssize_t len;

 if ((crtc_state->infoframes.enable &
      intel_hdmi_infoframe_enable(type)) == 0)
  return;

 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
  return;

 /* see comment above for the reason for this offset */
 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 if (drm_WARN_ON(encoder->base.dev, len < 0))
  return;

 /* Insert the 'hole' (see big comment above) at position 3 */
 memmove(&buffer[0], &buffer[1], 3);
 buffer[3] = 0;
 len++;

 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
}

void intel_read_infoframe(struct intel_encoder *encoder,
     const struct intel_crtc_state *crtc_state,
     enum hdmi_infoframe_type type,
     union hdmi_infoframe *frame)
{
 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 u8 buffer[VIDEO_DIP_DATA_SIZE];
 int ret;

 if ((crtc_state->infoframes.enable &
      intel_hdmi_infoframe_enable(type)) == 0)
  return;

 dig_port->read_infoframe(encoder, crtc_state,
           type, buffer, sizeof(buffer));

 /* Fill the 'hole' (see big comment above) at position 3 */
 memmove(&buffer[1], &buffer[0], 3);

 /* see comment above for the reason for this offset */
 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 if (ret) {
  drm_dbg_kms(encoder->base.dev,
       "Failed to unpack infoframe type 0x%02x\n", type);
  return;
 }

 if (frame->any.type != type)
  drm_dbg_kms(encoder->base.dev,
       "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
       frame->any.type, type);
}

static bool
intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
     struct intel_crtc_state *crtc_state,
     struct drm_connector_state *conn_state)
{
 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 const struct drm_display_mode *adjusted_mode =
  &crtc_state->hw.adjusted_mode;
 struct intel_connector *connector = to_intel_connector(conn_state->connector);
 int ret;

 if (!crtc_state->has_infoframe)
  return true;

 crtc_state->infoframes.enable |=
  intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);

 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, &connector->base,
             adjusted_mode);
 if (ret)
  return false;

 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
  frame->colorspace = HDMI_COLORSPACE_YUV420;
 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
  frame->colorspace = HDMI_COLORSPACE_YUV444;
 else
  frame->colorspace = HDMI_COLORSPACE_RGB;

 drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);

 /* nonsense combination */
 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
      crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);

 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
  drm_hdmi_avi_infoframe_quant_range(frame, &connector->base,
         adjusted_mode,
         crtc_state->limited_color_range ?
         HDMI_QUANTIZATION_RANGE_LIMITED :
         HDMI_QUANTIZATION_RANGE_FULL);
 } else {
  frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
  frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 }

 drm_hdmi_avi_infoframe_content_type(frame, conn_state);

 /* TODO: handle pixel repetition for YCBCR420 outputs */

 ret = hdmi_avi_infoframe_check(frame);
 if (drm_WARN_ON(encoder->base.dev, ret))
  return false;

 return true;
}

static bool
intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
     struct intel_crtc_state *crtc_state,
     struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(crtc_state);
 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 int ret;

 if (!crtc_state->has_infoframe)
  return true;

 crtc_state->infoframes.enable |=
  intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);

 if (display->platform.dgfx)
  ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
 else
  ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");

 if (drm_WARN_ON(encoder->base.dev, ret))
  return false;

 frame->sdi = HDMI_SPD_SDI_PC;

 ret = hdmi_spd_infoframe_check(frame);
 if (drm_WARN_ON(encoder->base.dev, ret))
  return false;

 return true;
}

static bool
intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
      struct intel_crtc_state *crtc_state,
      struct drm_connector_state *conn_state)
{
 struct hdmi_vendor_infoframe *frame =
  &crtc_state->infoframes.hdmi.vendor.hdmi;
 const struct drm_display_info *info =
  &conn_state->connector->display_info;
 int ret;

 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
  return true;

 crtc_state->infoframes.enable |=
  intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);

 ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
         conn_state->connector,
         &crtc_state->hw.adjusted_mode);
 if (drm_WARN_ON(encoder->base.dev, ret))
  return false;

 ret = hdmi_vendor_infoframe_check(frame);
 if (drm_WARN_ON(encoder->base.dev, ret))
  return false;

 return true;
}

static bool
intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
     struct intel_crtc_state *crtc_state,
     struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(encoder);
 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 int ret;

 if (DISPLAY_VER(display) < 10)
  return true;

 if (!crtc_state->has_infoframe)
  return true;

 if (!conn_state->hdr_output_metadata)
  return true;

 crtc_state->infoframes.enable |=
  intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);

 ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 if (ret < 0) {
  drm_dbg_kms(display->drm,
       "couldn't set HDR metadata in infoframe\n");
  return false;
 }

 ret = hdmi_drm_infoframe_check(frame);
 if (drm_WARN_ON(display->drm, ret))
  return false;

 return true;
}

static void g4x_set_infoframes(struct intel_encoder *encoder,
          bool enable,
          const struct intel_crtc_state *crtc_state,
          const struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 i915_reg_t reg = VIDEO_DIP_CTL;
 u32 val = intel_de_read(display, reg);
 u32 port = VIDEO_DIP_PORT(encoder->port);

 assert_hdmi_port_disabled(intel_hdmi);

 /* If the registers were not initialized yet, they might be zeroes,
 * which means we're selecting the AVI DIP and we're setting its
 * frequency to once. This seems to really confuse the HW and make
 * things stop working (the register spec says the AVI always needs to
 * be sent every VSync). So here we avoid writing to the register more
 * than we need and also explicitly select the AVI DIP and explicitly
 * set its frequency to every VSync. Avoiding to write it twice seems to
 * be enough to solve the problem, but being defensive shouldn't hurt us
 * either. */
 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

 if (!enable) {
  if (!(val & VIDEO_DIP_ENABLE))
   return;
  if (port != (val & VIDEO_DIP_PORT_MASK)) {
   drm_dbg_kms(display->drm,
        "video DIP still enabled on port %c\n",
        (val & VIDEO_DIP_PORT_MASK) >> 29);
   return;
  }
  val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
    VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
  intel_de_write(display, reg, val);
  intel_de_posting_read(display, reg);
  return;
 }

 if (port != (val & VIDEO_DIP_PORT_MASK)) {
  if (val & VIDEO_DIP_ENABLE) {
   drm_dbg_kms(display->drm,
        "video DIP already enabled on port %c\n",
        (val & VIDEO_DIP_PORT_MASK) >> 29);
   return;
  }
  val &= ~VIDEO_DIP_PORT_MASK;
  val |= port;
 }

 val |= VIDEO_DIP_ENABLE;
 val &= ~(VIDEO_DIP_ENABLE_AVI |
   VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);

 intel_de_write(display, reg, val);
 intel_de_posting_read(display, reg);

 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_AVI,
         &crtc_state->infoframes.avi);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_SPD,
         &crtc_state->infoframes.spd);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_VENDOR,
         &crtc_state->infoframes.hdmi);
}

/*
 * Determine if default_phase=1 can be indicated in the GCP infoframe.
 *
 * From HDMI specification 1.4a:
 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 *   phase of 0
 */
static bool gcp_default_phase_possible(int pipe_bpp,
           const struct drm_display_mode *mode)
{
 unsigned int pixels_per_group;

 switch (pipe_bpp) {
 case 30:
  /* 4 pixels in 5 clocks */
  pixels_per_group = 4;
  break;
 case 36:
  /* 2 pixels in 3 clocks */
  pixels_per_group = 2;
  break;
 case 48:
  /* 1 pixel in 2 clocks */
  pixels_per_group = 1;
  break;
 default:
  /* phase information not relevant for 8bpc */
  return false;
 }

 return mode->crtc_hdisplay % pixels_per_group == 0 &&
  mode->crtc_htotal % pixels_per_group == 0 &&
  mode->crtc_hblank_start % pixels_per_group == 0 &&
  mode->crtc_hblank_end % pixels_per_group == 0 &&
  mode->crtc_hsync_start % pixels_per_group == 0 &&
  mode->crtc_hsync_end % pixels_per_group == 0 &&
  ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
   mode->crtc_htotal/2 % pixels_per_group == 0);
}

static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
      const struct intel_crtc_state *crtc_state,
      const struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 i915_reg_t reg;

 if ((crtc_state->infoframes.enable &
      intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
  return false;

 if (HAS_DDI(display))
  reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
 else if (display->platform.valleyview || display->platform.cherryview)
  reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 else if (HAS_PCH_SPLIT(display))
  reg = TVIDEO_DIP_GCP(crtc->pipe);
 else
  return false;

 intel_de_write(display, reg, crtc_state->infoframes.gcp);

 return true;
}

void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
       struct intel_crtc_state *crtc_state)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 i915_reg_t reg;

 if ((crtc_state->infoframes.enable &
      intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
  return;

 if (HAS_DDI(display))
  reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder);
 else if (display->platform.valleyview || display->platform.cherryview)
  reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 else if (HAS_PCH_SPLIT(display))
  reg = TVIDEO_DIP_GCP(crtc->pipe);
 else
  return;

 crtc_state->infoframes.gcp = intel_de_read(display, reg);
}

static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
          struct intel_crtc_state *crtc_state,
          struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(encoder);

 if (display->platform.g4x || !crtc_state->has_infoframe)
  return;

 crtc_state->infoframes.enable |=
  intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);

 /* Indicate color indication for deep color mode */
 if (crtc_state->pipe_bpp > 24)
  crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;

 /* Enable default_phase whenever the display mode is suitably aligned */
 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
           &crtc_state->hw.adjusted_mode))
  crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
}

static void ibx_set_infoframes(struct intel_encoder *encoder,
          bool enable,
          const struct intel_crtc_state *crtc_state,
          const struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 u32 val = intel_de_read(display, reg);
 u32 port = VIDEO_DIP_PORT(encoder->port);

 assert_hdmi_port_disabled(intel_hdmi);

 /* See the big comment in g4x_set_infoframes() */
 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

 if (!enable) {
  if (!(val & VIDEO_DIP_ENABLE))
   return;
  val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
    VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
    VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  intel_de_write(display, reg, val);
  intel_de_posting_read(display, reg);
  return;
 }

 if (port != (val & VIDEO_DIP_PORT_MASK)) {
  drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
    "DIP already enabled on port %c\n",
    (val & VIDEO_DIP_PORT_MASK) >> 29);
  val &= ~VIDEO_DIP_PORT_MASK;
  val |= port;
 }

 val |= VIDEO_DIP_ENABLE;
 val &= ~(VIDEO_DIP_ENABLE_AVI |
   VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
   VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);

 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
  val |= VIDEO_DIP_ENABLE_GCP;

 intel_de_write(display, reg, val);
 intel_de_posting_read(display, reg);

 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_AVI,
         &crtc_state->infoframes.avi);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_SPD,
         &crtc_state->infoframes.spd);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_VENDOR,
         &crtc_state->infoframes.hdmi);
}

static void cpt_set_infoframes(struct intel_encoder *encoder,
          bool enable,
          const struct intel_crtc_state *crtc_state,
          const struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 u32 val = intel_de_read(display, reg);

 assert_hdmi_port_disabled(intel_hdmi);

 /* See the big comment in g4x_set_infoframes() */
 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

 if (!enable) {
  if (!(val & VIDEO_DIP_ENABLE))
   return;
  val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
    VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
    VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  intel_de_write(display, reg, val);
  intel_de_posting_read(display, reg);
  return;
 }

 /* Set both together, unset both together: see the spec. */
 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
   VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);

 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
  val |= VIDEO_DIP_ENABLE_GCP;

 intel_de_write(display, reg, val);
 intel_de_posting_read(display, reg);

 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_AVI,
         &crtc_state->infoframes.avi);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_SPD,
         &crtc_state->infoframes.spd);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_VENDOR,
         &crtc_state->infoframes.hdmi);
}

static void vlv_set_infoframes(struct intel_encoder *encoder,
          bool enable,
          const struct intel_crtc_state *crtc_state,
          const struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(encoder);
 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
 u32 val = intel_de_read(display, reg);
 u32 port = VIDEO_DIP_PORT(encoder->port);

 assert_hdmi_port_disabled(intel_hdmi);

 /* See the big comment in g4x_set_infoframes() */
 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

 if (!enable) {
  if (!(val & VIDEO_DIP_ENABLE))
   return;
  val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
    VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
    VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
  intel_de_write(display, reg, val);
  intel_de_posting_read(display, reg);
  return;
 }

 if (port != (val & VIDEO_DIP_PORT_MASK)) {
  drm_WARN(display->drm, val & VIDEO_DIP_ENABLE,
    "DIP already enabled on port %c\n",
    (val & VIDEO_DIP_PORT_MASK) >> 29);
  val &= ~VIDEO_DIP_PORT_MASK;
  val |= port;
 }

 val |= VIDEO_DIP_ENABLE;
 val &= ~(VIDEO_DIP_ENABLE_AVI |
   VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
   VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);

 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
  val |= VIDEO_DIP_ENABLE_GCP;

 intel_de_write(display, reg, val);
 intel_de_posting_read(display, reg);

 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_AVI,
         &crtc_state->infoframes.avi);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_SPD,
         &crtc_state->infoframes.spd);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_VENDOR,
         &crtc_state->infoframes.hdmi);
}

void intel_hdmi_fastset_infoframes(struct intel_encoder *encoder,
       const struct intel_crtc_state *crtc_state,
       const struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(encoder);
 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
         crtc_state->cpu_transcoder);
 u32 val = intel_de_read(display, reg);

 if ((crtc_state->infoframes.enable &
  intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM)) == 0 &&
   (val & VIDEO_DIP_ENABLE_DRM_GLK) == 0)
  return;

 val &= ~(VIDEO_DIP_ENABLE_DRM_GLK);

 intel_de_write(display, reg, val);
 intel_de_posting_read(display, reg);

 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_DRM,
         &crtc_state->infoframes.drm);
}

static void hsw_set_infoframes(struct intel_encoder *encoder,
          bool enable,
          const struct intel_crtc_state *crtc_state,
          const struct drm_connector_state *conn_state)
{
 struct intel_display *display = to_intel_display(encoder);
 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display,
         crtc_state->cpu_transcoder);
 u32 val = intel_de_read(display, reg);

 assert_hdmi_transcoder_func_disabled(display,
          crtc_state->cpu_transcoder);

 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
   VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
   VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
   VIDEO_DIP_ENABLE_DRM_GLK | VIDEO_DIP_ENABLE_AS_ADL);

 if (!enable) {
  intel_de_write(display, reg, val);
  intel_de_posting_read(display, reg);
  return;
 }

 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
  val |= VIDEO_DIP_ENABLE_GCP_HSW;

 intel_de_write(display, reg, val);
 intel_de_posting_read(display, reg);

 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_AVI,
         &crtc_state->infoframes.avi);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_SPD,
         &crtc_state->infoframes.spd);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_VENDOR,
         &crtc_state->infoframes.hdmi);
 intel_write_infoframe(encoder, crtc_state,
         HDMI_INFOFRAME_TYPE_DRM,
         &crtc_state->infoframes.drm);
}

void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
{
 struct intel_display *display = to_intel_display(hdmi);
 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;

 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
  return;

 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n",
      enable ? "Enabling" : "Disabling");

 drm_dp_dual_mode_set_tmds_output(display->drm,
      hdmi->dp_dual_mode.type, ddc, enable);
}

static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
    unsigned int offset, void *buffer, size_t size)
{
 struct intel_hdmi *hdmi = &dig_port->hdmi;
 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
 int ret;
 u8 start = offset & 0xff;
 struct i2c_msg msgs[] = {
  {
   .addr = DRM_HDCP_DDC_ADDR,
   .flags = 0,
   .len = 1,
   .buf = &start,
  },
  {
   .addr = DRM_HDCP_DDC_ADDR,
   .flags = I2C_M_RD,
   .len = size,
   .buf = buffer
  }
 };
 ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs));
 if (ret == ARRAY_SIZE(msgs))
  return 0;
 return ret >= 0 ? -EIO : ret;
}

static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
     unsigned int offset, void *buffer, size_t size)
{
 struct intel_hdmi *hdmi = &dig_port->hdmi;
 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
 int ret;
 u8 *write_buf;
 struct i2c_msg msg;

 write_buf = kzalloc(size + 1, GFP_KERNEL);
 if (!write_buf)
  return -ENOMEM;

 write_buf[0] = offset & 0xff;
 memcpy(&write_buf[1], buffer, size);

 msg.addr = DRM_HDCP_DDC_ADDR;
 msg.flags = 0;
 msg.len = size + 1;
 msg.buf = write_buf;

 ret = i2c_transfer(ddc, &msg, 1);
 if (ret == 1)
  ret = 0;
 else if (ret >= 0)
  ret = -EIO;

 kfree(write_buf);
 return ret;
}

static
int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
      u8 *an)
{
 struct intel_display *display = to_intel_display(dig_port);
 struct intel_hdmi *hdmi = &dig_port->hdmi;
 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
 int ret;

 ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
        DRM_HDCP_AN_LEN);
 if (ret) {
  drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n",
       ret);
  return ret;
 }

 ret = intel_gmbus_output_aksv(ddc);
 if (ret < 0) {
  drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret);
  return ret;
 }
 return 0;
}

static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
         u8 *bksv)
{
 struct intel_display *display = to_intel_display(dig_port);

 int ret;
 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
       DRM_HDCP_KSV_LEN);
 if (ret)
  drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n",
       ret);
 return ret;
}

static
int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
     u8 *bstatus)
{
 struct intel_display *display = to_intel_display(dig_port);

 int ret;
 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
       bstatus, DRM_HDCP_BSTATUS_LEN);
 if (ret)
  drm_dbg_kms(display->drm,
       "Read bstatus over DDC failed (%d)\n",
       ret);
 return ret;
}

static
int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
         bool *repeater_present)
{
 struct intel_display *display = to_intel_display(dig_port);
 int ret;
 u8 val;

 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
 if (ret) {
  drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
       ret);
  return ret;
 }
 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
 return 0;
}

static
int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
      u8 *ri_prime)
{
 struct intel_display *display = to_intel_display(dig_port);

 int ret;
 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
       ri_prime, DRM_HDCP_RI_LEN);
 if (ret)
  drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n",
       ret);
 return ret;
}

static
int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
       bool *ksv_ready)
{
 struct intel_display *display = to_intel_display(dig_port);
 int ret;
 u8 val;

 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
 if (ret) {
  drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n",
       ret);
  return ret;
 }
 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
 return 0;
}

static
int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
      int num_downstream, u8 *ksv_fifo)
{
 struct intel_display *display = to_intel_display(dig_port);
 int ret;
 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
       ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
 if (ret) {
  drm_dbg_kms(display->drm,
       "Read ksv fifo over DDC failed (%d)\n", ret);
  return ret;
 }
 return 0;
}

static
int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
          int i, u32 *part)
{
 struct intel_display *display = to_intel_display(dig_port);
 int ret;

 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
  return -EINVAL;

 ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
       part, DRM_HDCP_V_PRIME_PART_LEN);
 if (ret)
  drm_dbg_kms(display->drm,
       "Read V'[%d] over DDC failed (%d)\n",
       i, ret);
 return ret;
}

static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
        enum transcoder cpu_transcoder)
{
 struct intel_display *display = to_intel_display(connector);
 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
 u32 scanline;
 int ret;

 for (;;) {
  scanline = intel_de_read(display,
      PIPEDSL(display, crtc->pipe));
  if (scanline > 100 && scanline < 200)
   break;
  usleep_range(25, 50);
 }

 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
      false, TRANS_DDI_HDCP_SIGNALLING);
 if (ret) {
  drm_err(display->drm,
   "Disable HDCP signalling failed (%d)\n", ret);
  return ret;
 }

 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
      true, TRANS_DDI_HDCP_SIGNALLING);
 if (ret) {
  drm_err(display->drm,
   "Enable HDCP signalling failed (%d)\n", ret);
  return ret;
 }

 return 0;
}

static
int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
          enum transcoder cpu_transcoder,
          bool enable)
{
 struct intel_display *display = to_intel_display(dig_port);
 struct intel_hdmi *hdmi = &dig_port->hdmi;
 struct intel_connector *connector = hdmi->attached_connector;
 int ret;

 if (!enable)
  usleep_range(6, 60); /* Bspec says >= 6us */

 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
      cpu_transcoder, enable,
      TRANS_DDI_HDCP_SIGNALLING);
 if (ret) {
  drm_err(display->drm, "%s HDCP signalling failed (%d)\n",
   enable ? "Enable" : "Disable", ret);
  return ret;
 }

 /*
 * WA: To fix incorrect positioning of the window of
 * opportunity and enc_en signalling in KABYLAKE.
 */
 if (display->platform.kabylake && enable)
  return kbl_repositioning_enc_en_signal(connector,
             cpu_transcoder);

 return 0;
}

static
bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
         struct intel_connector *connector)
{
 struct intel_display *display = to_intel_display(dig_port);
 enum port port = dig_port->base.port;
 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
 int ret;
 union {
  u32 reg;
  u8 shim[DRM_HDCP_RI_LEN];
 } ri;

 ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
 if (ret)
  return false;

 intel_de_write(display, HDCP_RPRIME(display, cpu_transcoder, port), ri.reg);

 /* Wait for Ri prime match */
 if (wait_for((intel_de_read(display, HDCP_STATUS(display, cpu_transcoder, port)) &
        (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
       (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
  drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n",
       intel_de_read(display, HDCP_STATUS(display, cpu_transcoder,
              port)));
  return false;
 }
 return true;
}

static
bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
    struct intel_connector *connector)
{
 int retry;

 for (retry = 0; retry < 3; retry++)
  if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
   return true;

 return false;
}

struct hdcp2_hdmi_msg_timeout {
 u8 msg_id;
 u16 timeout;
};

static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
 { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
 { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
 { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
 { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
 { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
};

static
int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
        u8 *rx_status)
{
 return intel_hdmi_hdcp_read(dig_port,
        HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
        rx_status,
        HDCP_2_2_HDMI_RXSTATUS_LEN);
}

static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
{
 int i;

 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
  if (is_paired)
   return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
  else
   return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
 }

 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
  if (hdcp2_msg_timeout[i].msg_id == msg_id)
   return hdcp2_msg_timeout[i].timeout;
 }

 return -EINVAL;
}

static int
hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
         u8 msg_id, bool *msg_ready,
         ssize_t *msg_sz)
{
 struct intel_display *display = to_intel_display(dig_port);
 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
 int ret;

 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
 if (ret < 0) {
  drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n",
       ret);
  return ret;
 }

 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
    rx_status[0]);

 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
  *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
        *msg_sz);
 else
  *msg_ready = *msg_sz;

 return 0;
}

static ssize_t
intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
         u8 msg_id, bool paired)
{
 struct intel_display *display = to_intel_display(dig_port);
 bool msg_ready = false;
 int timeout, ret;
 ssize_t msg_sz = 0;

 timeout = get_hdcp2_msg_timeout(msg_id, paired);
 if (timeout < 0)
  return timeout;

 ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
            msg_id, &msg_ready,
            &msg_sz),
    !ret && msg_ready && msg_sz, timeout * 1000,
    1000, 5 * 1000);
 if (ret)
  drm_dbg_kms(display->drm,
       "msg_id: %d, ret: %d, timeout: %d\n",
       msg_id, ret, timeout);

 return ret ? ret : msg_sz;
}

static
int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector,
          void *buf, size_t size)
{
 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
 unsigned int offset;

 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
 return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
}

static
int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector,
         u8 msg_id, void *buf, size_t size)
{
 struct intel_display *display = to_intel_display(connector);
 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
 struct intel_hdmi *hdmi = &dig_port->hdmi;
 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
 unsigned int offset;
 ssize_t ret;

 ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
         hdcp->is_paired);
 if (ret < 0)
  return ret;

 /*
 * Available msg size should be equal to or lesser than the
 * available buffer.
 */
 if (ret > size) {
  drm_dbg_kms(display->drm,
       "msg_sz(%zd) is more than exp size(%zu)\n",
       ret, size);
  return -EINVAL;
 }

 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
 ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
 if (ret)
  drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n",
       msg_id, ret);

 return ret;
}

static
int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
    struct intel_connector *connector)
{
 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
 int ret;

 ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
 if (ret)
  return ret;

 /*
 * Re-auth request and Link Integrity Failures are represented by
 * same bit. i.e reauth_req.
 */
 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
  ret = HDCP_REAUTH_REQUEST;
 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
  ret = HDCP_TOPOLOGY_CHANGE;

 return ret;
}

static
int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector,
        bool *capable)
{
 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
 u8 hdcp2_version;
 int ret;

 *capable = false;
 ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
       &hdcp2_version, sizeof(hdcp2_version));
 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
  *capable = true;

 return ret;
}

static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
 .read_bksv = intel_hdmi_hdcp_read_bksv,
 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
 .repeater_present = intel_hdmi_hdcp_repeater_present,
 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
 .check_link = intel_hdmi_hdcp_check_link,
 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
 .check_2_2_link = intel_hdmi_hdcp2_check_link,
 .hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability,
 .protocol = HDCP_PROTOCOL_HDMI,
};

static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
{
 struct intel_display *display = to_intel_display(encoder);
 int max_tmds_clock, vbt_max_tmds_clock;

 if (DISPLAY_VER(display) >= 13 || display->platform.alderlake_s)
  max_tmds_clock = 600000;
 else if (DISPLAY_VER(display) >= 10)
  max_tmds_clock = 594000;
 else if (DISPLAY_VER(display) >= 8 || display->platform.haswell)
  max_tmds_clock = 300000;
 else if (DISPLAY_VER(display) >= 5)
  max_tmds_clock = 225000;
 else
  max_tmds_clock = 165000;

 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata);
 if (vbt_max_tmds_clock)
  max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);

 return max_tmds_clock;
}

static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
    const struct drm_connector_state *conn_state)
{
 struct intel_connector *connector = hdmi->attached_connector;

 return connector->base.display_info.is_hdmi &&
  READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
}

static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
{
 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
}

static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
     bool respect_downstream_limits,
     bool has_hdmi_sink)
{
 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);

 if (respect_downstream_limits) {
  struct intel_connector *connector = hdmi->attached_connector;
  const struct drm_display_info *info = &connector->base.display_info;

  if (hdmi->dp_dual_mode.max_tmds_clock)
   max_tmds_clock = min(max_tmds_clock,
          hdmi->dp_dual_mode.max_tmds_clock);

  if (info->max_tmds_clock)
   max_tmds_clock = min(max_tmds_clock,
          info->max_tmds_clock);
  else if (!has_hdmi_sink)
   max_tmds_clock = min(max_tmds_clock, 165000);
 }

 return max_tmds_clock;
}

static enum drm_mode_status
hdmi_port_clock_valid(struct intel_hdmi *hdmi,
        int clock, bool respect_downstream_limits,
        bool has_hdmi_sink)
{
 struct intel_display *display = to_intel_display(hdmi);
 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;

 if (clock < 25000)
  return MODE_CLOCK_LOW;
 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
       has_hdmi_sink))
  return MODE_CLOCK_HIGH;

 /* GLK DPLL can't generate 446-480 MHz */
 if (display->platform.geminilake && clock > 446666 && clock < 480000)
  return MODE_CLOCK_RANGE;

 /* BXT/GLK DPLL can't generate 223-240 MHz */
 if ((display->platform.geminilake || display->platform.broxton) &&
     clock > 223333 && clock < 240000)
  return MODE_CLOCK_RANGE;

 /* CHV DPLL can't generate 216-240 MHz */
 if (display->platform.cherryview && clock > 216000 && clock < 240000)
  return MODE_CLOCK_RANGE;

 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
 if (intel_encoder_is_combo(encoder) && clock > 500000 && clock < 533200)
  return MODE_CLOCK_RANGE;

 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
 if (intel_encoder_is_tc(encoder) && clock > 500000 && clock < 532800)
  return MODE_CLOCK_RANGE;

 return MODE_OK;
}

int intel_hdmi_tmds_clock(int clock, int bpc,
     enum intel_output_format sink_format)
{
 /* YCBCR420 TMDS rate requirement is half the pixel clock */
 if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
  clock /= 2;

 /*
 * Need to adjust the port link by:
 *  1.5x for 12bpc
 *  1.25x for 10bpc
 */
 return DIV_ROUND_CLOSEST(clock * bpc, 8);
}

static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc)
{
 switch (bpc) {
 case 12:
  return !HAS_GMCH(display);
 case 10:
  return DISPLAY_VER(display) >= 11;
 case 8:
  return true;
 default:
  MISSING_CASE(bpc);
  return false;
 }
}

static bool intel_hdmi_sink_bpc_possible(struct drm_connector *_connector,
      int bpc, bool has_hdmi_sink,
      enum intel_output_format sink_format)
{
 struct intel_connector *connector = to_intel_connector(_connector);
 const struct drm_display_info *info = &connector->base.display_info;
 const struct drm_hdmi_info *hdmi = &info->hdmi;

 switch (bpc) {
 case 12:
  if (!has_hdmi_sink)
   return false;

  if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
   return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
  else
   return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
 case 10:
  if (!has_hdmi_sink)
   return false;

  if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
   return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
  else
   return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
 case 8:
  return true;
 default:
  MISSING_CASE(bpc);
  return false;
 }
}

static enum drm_mode_status
intel_hdmi_mode_clock_valid(struct drm_connector *_connector, int clock,
       bool has_hdmi_sink,
       enum intel_output_format sink_format)
{
 struct intel_connector *connector = to_intel_connector(_connector);
 struct intel_display *display = to_intel_display(connector);
 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
 enum drm_mode_status status = MODE_OK;
 int bpc;

 /*
 * Try all color depths since valid port clock range
 * can have holes. Any mode that can be used with at
 * least one color depth is accepted.
 */
 for (bpc = 12; bpc >= 8; bpc -= 2) {
  int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);

  if (!intel_hdmi_source_bpc_possible(display, bpc))
   continue;

  if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink,
        sink_format))
   continue;

  status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
  if (status == MODE_OK)
   return MODE_OK;
 }

 /* can never happen */
 drm_WARN_ON(display->drm, status == MODE_OK);

 return status;
}

static enum drm_mode_status
intel_hdmi_mode_valid(struct drm_connector *_connector,
        const struct drm_display_mode *mode)
{
 struct intel_connector *connector = to_intel_connector(_connector);
 struct intel_display *display = to_intel_display(connector);
 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
 enum drm_mode_status status;
 int clock = mode->clock;
 int max_dotclk = display->cdclk.max_dotclk_freq;
 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->base.state);
 bool ycbcr_420_only;
 enum intel_output_format sink_format;

 status = intel_cpu_transcoder_mode_valid(display, mode);
 if (status != MODE_OK)
  return status;

 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
  clock *= 2;

 if (clock > max_dotclk)
  return MODE_CLOCK_HIGH;

 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
  if (!has_hdmi_sink)
   return MODE_CLOCK_LOW;
  clock *= 2;
 }

 /*
 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
 * enumerated only if FRL is supported. Current platforms do not support
 * FRL so prune the higher resolution modes that require doctclock more
 * than 600MHz.
 */
 if (clock > 600000)
  return MODE_CLOCK_HIGH;

 ycbcr_420_only = drm_mode_is_420_only(&connector->base.display_info, mode);

 if (ycbcr_420_only)
  sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
 else
  sink_format = INTEL_OUTPUT_FORMAT_RGB;

 status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink, sink_format);
 if (status != MODE_OK) {
  if (ycbcr_420_only ||
      !connector->base.ycbcr_420_allowed ||
      !drm_mode_is_420_also(&connector->base.display_info, mode))
   return status;

  sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
  status = intel_hdmi_mode_clock_valid(&connector->base, clock, has_hdmi_sink,
           sink_format);
  if (status != MODE_OK)
   return status;
 }

 return intel_mode_valid_max_plane_size(display, mode, 1);
}

bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
        int bpc, bool has_hdmi_sink)
{
 struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
 struct intel_digital_connector_state *connector_state;
 struct intel_connector *connector;
 int i;

 for_each_new_intel_connector_in_state(state, connector, connector_state, i) {
  if (connector_state->base.crtc != crtc_state->uapi.crtc)
   continue;

  if (!intel_hdmi_sink_bpc_possible(&connector->base, bpc, has_hdmi_sink,
        crtc_state->sink_format))
   return false;
 }

 return true;
}

static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
{
 struct intel_display *display = to_intel_display(crtc_state);
 const struct drm_display_mode *adjusted_mode =
  &crtc_state->hw.adjusted_mode;

 if (!intel_hdmi_source_bpc_possible(display, bpc))
  return false;

 /* Display Wa_1405510057:icl,ehl */
 if (intel_hdmi_is_ycbcr420(crtc_state) &&
     bpc == 10 && DISPLAY_VER(display) == 11 &&
     (adjusted_mode->crtc_hblank_end -
      adjusted_mode->crtc_hblank_start) % 8 == 2)
  return false;

 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
}

static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
      struct intel_crtc_state *crtc_state,
      int clock, bool respect_downstream_limits)
{
 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 int bpc;

 /*
 * pipe_bpp could already be below 8bpc due to FDI
 * bandwidth constraints. HDMI minimum is 8bpc however.
 */
 bpc = max(crtc_state->pipe_bpp / 3, 8);

 /*
 * We will never exceed downstream TMDS clock limits while
 * attempting deep color. If the user insists on forcing an
 * out of spec mode they will have to be satisfied with 8bpc.
 */
 if (!respect_downstream_limits)
  bpc = 8;

 for (; bpc >= 8; bpc -= 2) {
  int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
             crtc_state->sink_format);

  if (hdmi_bpc_possible(crtc_state, bpc) &&
      hdmi_port_clock_valid(intel_hdmi, tmds_clock,
       respect_downstream_limits,
       crtc_state->has_hdmi_sink) == MODE_OK)
   return bpc;
 }

 return -EINVAL;
}

static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
        struct intel_crtc_state *crtc_state,
        bool respect_downstream_limits)
{
 struct intel_display *display = to_intel_display(encoder);
 const struct drm_display_mode *adjusted_mode =
  &crtc_state->hw.adjusted_mode;
 int bpc, clock = adjusted_mode->crtc_clock;

 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
  clock *= 2;

 bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
         respect_downstream_limits);
 if (bpc < 0)
  return bpc;

 crtc_state->port_clock =
  intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);

 /*
 * pipe_bpp could already be below 8bpc due to
 * FDI bandwidth constraints. We shouldn't bump it
 * back up to the HDMI minimum 8bpc in that case.
 */
 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);

 drm_dbg_kms(display->drm,
      "picking %d bpc for HDMI output (pipe bpp: %d)\n",
      bpc, crtc_state->pipe_bpp);

 return 0;
}

bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
        const struct drm_connector_state *conn_state)
{
 const struct intel_digital_connector_state *intel_conn_state =
  to_intel_digital_connector_state(conn_state);
 const struct drm_display_mode *adjusted_mode =
  &crtc_state->hw.adjusted_mode;

 /*
 * Our YCbCr output is always limited range.
 * crtc_state->limited_color_range only applies to RGB,
 * and it must never be set for YCbCr or we risk setting
 * some conflicting bits in TRANSCONF which will mess up
 * the colors on the monitor.
 */
 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
  return false;

 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
  /* See CEA-861-E - 5.1 Default Encoding Parameters */
  return crtc_state->has_hdmi_sink &&
   drm_default_rgb_quant_range(adjusted_mode) ==
   HDMI_QUANTIZATION_RANGE_LIMITED;
 } else {
  return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
 }
}

static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
     const struct intel_crtc_state *crtc_state,
     const struct drm_connector_state *conn_state)
{
 struct intel_connector *connector = to_intel_connector(conn_state->connector);
 const struct intel_digital_connector_state *intel_conn_state =
  to_intel_digital_connector_state(conn_state);

 if (!crtc_state->has_hdmi_sink)
  return false;

 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
  return connector->base.display_info.has_audio;
 else
  return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}

static enum intel_output_format
intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state,
         struct intel_connector *connector,
         bool ycbcr_420_output)
{
 if (!crtc_state->has_hdmi_sink)
  return INTEL_OUTPUT_FORMAT_RGB;

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