/* * Copyright © 2013 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS * IN THE SOFTWARE. #include <drm/drm_managed.h>#include <linux/pm_runtime.h>#include "display/intel_display_core.h" #include "gt/intel_gt.h" #include "gt/intel_engine_regs.h" #include "gt/intel_gt_regs.h" #include "i915_drv.h" #include "i915_iosf_mbi.h" #include "i915_reg.h" #include "i915_vgpu.h" #include "intel_uncore_trace.h" #define FORCEWAKE_ACK_TIMEOUT_MS 50#define GT_FIFO_TIMEOUT_MS 10struct intel_uncore *to_intel_uncore(struct drm_device *drm)return &to_i915(drm)->uncore;#define __raw_posting_read(...) ((void )__raw_uncore_read32(__VA_ARGS__))static void struct intel_uncore *uncore, enum forcewake_domains fw_domains)void struct drm_i915_private *i915)static void mmio_debug_suspend(struct intel_uncore *uncore)if (!uncore->debug)return ;/* Save and disable mmio debugging for the user bypass */ if (!uncore->debug->suspend_count++) {static bool check_for_unclaimed_mmio(struct intel_uncore *uncore);static void mmio_debug_resume(struct intel_uncore *uncore)if (!uncore->debug)return ;if (!--uncore->debug->suspend_count)if (check_for_unclaimed_mmio(uncore))"Invalid mmio detected during user access\n" );static const char * const forcewake_domain_names[] = {"render" ,"gt" ,"media" ,"vdbox0" ,"vdbox1" ,"vdbox2" ,"vdbox3" ,"vdbox4" ,"vdbox5" ,"vdbox6" ,"vdbox7" ,"vebox0" ,"vebox1" ,"vebox2" ,"vebox3" ,"gsc" ,const char *const enum forcewake_domain_id id)if (id >= 0 && id < FW_DOMAIN_ID_COUNT)return forcewake_domain_names[id];return "unknown" ;#define fw_ack(d) readl((d)->reg_ack)#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set)#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set)static inline void const struct intel_uncore_forcewake_domain *d)/* * We don't really know if the powerwell for the forcewake domain we are * trying to reset here does exist at this point (engines could be fused * off in ICL+), so no waiting for acks /* WaRsClearFWBitsAtReset */ if (GRAPHICS_VER(d->uncore->i915) >= 12)else static inline void struct intel_uncore_forcewake_domain *d)static inline int const struct intel_uncore_forcewake_domain *d,const u32 ack,const u32 value)return wait_for_atomic((fw_ack(d) & ack) == value,static inline int const struct intel_uncore_forcewake_domain *d,const u32 ack)return __wait_for_ack(d, ack, 0);static inline int const struct intel_uncore_forcewake_domain *d,const u32 ack)return __wait_for_ack(d, ack, ack);static inline void const struct intel_uncore_forcewake_domain *d)if (!wait_ack_clear(d, FORCEWAKE_KERNEL))return ;if (fw_ack(d) == ~0) {"%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n" ,else {"%s: timed out waiting for forcewake ack to clear.\n" ,/* CI now unreliable */ enum ack_type {static int const struct intel_uncore_forcewake_domain *d,const enum ack_type type)const u32 ack_bit = FORCEWAKE_KERNEL;const u32 value = type == ACK_SET ? ack_bit : 0;unsigned int pass;bool ack_detected;/* * There is a possibility of driver's wake request colliding * with hardware's own wake requests and that can cause * hardware to not deliver the driver's ack message. * * Use a fallback bit toggle to kick the gpu state machine * in the hope that the original ack will be delivered along with * the fallback ack. * * This workaround is described in HSDES #1604254524 and it's known as: * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl * although the name is a bit misleading. do {/* Give gt some time to relax before the polling frenzy */ while (!ack_detected && pass++ < 10);"%s had to use fallback to %s ack, 0x%x (passes %u)\n" ,"set" : "clear" ,return ack_detected ? 0 : -ETIMEDOUT;static inline void const struct intel_uncore_forcewake_domain *d)if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL)))return ;if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR))static inline void const struct intel_uncore_forcewake_domain *d)static inline void const struct intel_uncore_forcewake_domain *d)if (wait_ack_set(d, FORCEWAKE_KERNEL)) {"%s: timed out waiting for forcewake ack request.\n" ,/* CI now unreliable */ static inline void const struct intel_uncore_forcewake_domain *d)if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL)))return ;if (fw_domain_wait_ack_with_fallback(d, ACK_SET))static inline void const struct intel_uncore_forcewake_domain *d)static void struct intel_uncore *uncore, enum forcewake_domains fw_domains)struct intel_uncore_forcewake_domain *d;unsigned int tmp;static void struct intel_uncore *uncore,enum forcewake_domains fw_domains)struct intel_uncore_forcewake_domain *d;unsigned int tmp;static void struct intel_uncore *uncore, enum forcewake_domains fw_domains)struct intel_uncore_forcewake_domain *d;unsigned int tmp;static void struct intel_uncore *uncore,enum forcewake_domains fw_domains)struct intel_uncore_forcewake_domain *d;unsigned int tmp;if (!fw_domains)return ;static inline u32 gt_thread_status(struct intel_uncore *uncore)return val;static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore)/* * w/a for a sporadic read returning 0 by waiting for the GT * thread to wake up. "GT thread status wait timed out\n" );static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,enum forcewake_domains fw_domains)/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ static inline u32 fifo_free_entries(struct intel_uncore *uncore)return count & GT_FIFO_FREE_ENTRIES_MASK;static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore)/* On VLV, FIFO will be shared by both SW and HW. if (IS_VALLEYVIEW(uncore->i915))else if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) {if (wait_for_atomic((n = fifo_free_entries(uncore)) >"GT_FIFO timeout, entries: %u\n" , n);return ;static enum hrtimer_restartstruct hrtimer *timer)struct intel_uncore_forcewake_domain *domain =struct intel_uncore_forcewake_domain, timer);struct intel_uncore *uncore = domain->uncore;unsigned long irqflags;if (xchg(&domain->active, false ))return HRTIMER_RESTART;if (--domain->wake_count == 0)return HRTIMER_NORESTART;/* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */ static unsigned int struct intel_uncore *uncore)unsigned long irqflags;struct intel_uncore_forcewake_domain *domain;int retry_count = 100;enum forcewake_domains fw, active_domains;/* Hold uncore.lock across reset to prevent any register access * with forcewake not set correctly. Wait until all pending * timers are run before holding. while (1) {unsigned int tmp;false );if (hrtimer_cancel(&domain->timer) == 0)continue ;if (hrtimer_active(&domain->timer))if (active_domains == 0)break ;if (--retry_count == 0) {"Timed out waiting for forcewake timers to finish\n" );break ;if (fw)return fw; /* track the lost user forcewake domains */ static bool struct intel_uncore *uncore)if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM)))return false ;/* * Bugs in PCI programming (or failing hardware) can occasionally cause * us to lose access to the MMIO BAR. When this happens, register * reads will come back with 0xFFFFFFFF for every register and things * go bad very quickly. Let's try to detect that special case and at * least try to print a more informative message about what has * happened. * * During normal operation the FPGA_DBG register has several unused * bits that will always read back as 0's so we can use them as canaries * to recognize when MMIO accesses are just busted. if (unlikely(dbg == ~0))"Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n" );return true ;static bool struct intel_uncore *uncore)if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK))))return false ;return true ;static bool struct intel_uncore *uncore)if (unlikely(fifodbg)) {"GTFIFODBG = 0x08%x\n" , fifodbg);return fifodbg;static bool struct intel_uncore *uncore)bool ret = false ;if (uncore->debug->suspend_count)return false ;if (intel_uncore_has_fpga_dbg_unclaimed(uncore))if (intel_uncore_has_dbg_unclaimed(uncore))if (intel_uncore_has_fifo(uncore))return ret;static void forcewake_early_sanitize(struct intel_uncore *uncore,unsigned int restore_forcewake)/* WaDisableShadowRegForCpd:chv */ if (IS_CHERRYVIEW(uncore->i915)) {if (restore_forcewake) {if (intel_uncore_has_fifo(uncore))void intel_uncore_suspend(struct intel_uncore *uncore)if (!intel_uncore_has_forcewake(uncore))return ;void intel_uncore_resume_early(struct intel_uncore *uncore)unsigned int restore_forcewake;if (intel_uncore_unclaimed_mmio(uncore))"unclaimed mmio detected on resume, clearing\n" );if (!intel_uncore_has_forcewake(uncore))return ;void intel_uncore_runtime_resume(struct intel_uncore *uncore)if (!intel_uncore_has_forcewake(uncore))return ;static void __intel_uncore_forcewake_get(struct intel_uncore *uncore,enum forcewake_domains fw_domains)struct intel_uncore_forcewake_domain *domain;unsigned int tmp;if (domain->wake_count++) {true ;if (fw_domains)/** * intel_uncore_forcewake_get - grab forcewake domain references * @uncore: the intel_uncore structure * @fw_domains: forcewake domains to get reference on * * This function can be used get GT's forcewake domain references. * Normal register access will handle the forcewake domains automatically. * However if some sequence requires the GT to not power down a particular * forcewake domains this function should be called at the beginning of the * sequence. And subsequently the reference should be dropped by symmetric * call to intel_unforce_forcewake_put(). Usually caller wants all the domains * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. void intel_uncore_forcewake_get(struct intel_uncore *uncore,enum forcewake_domains fw_domains)unsigned long irqflags;if (!uncore->fw_get_funcs)return ;/** * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace * @uncore: the intel_uncore structure * * This function is a wrapper around intel_uncore_forcewake_get() to acquire * the GT powerwell and in the process disable our debugging for the * duration of userspace's bypass. void intel_uncore_forcewake_user_get(struct intel_uncore *uncore)if (!uncore->user_forcewake_count++) {/** * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace * @uncore: the intel_uncore structure * * This function complements intel_uncore_forcewake_user_get() and releases * the GT powerwell taken on behalf of the userspace bypass. void intel_uncore_forcewake_user_put(struct intel_uncore *uncore)if (!--uncore->user_forcewake_count) {/** * intel_uncore_forcewake_get__locked - grab forcewake domain references * @uncore: the intel_uncore structure * @fw_domains: forcewake domains to get reference on * * See intel_uncore_forcewake_get(). This variant places the onus * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore,enum forcewake_domains fw_domains)if (!uncore->fw_get_funcs)return ;static void __intel_uncore_forcewake_put(struct intel_uncore *uncore,enum forcewake_domains fw_domains,bool delayed)struct intel_uncore_forcewake_domain *domain;unsigned int tmp;if (--domain->wake_count) {true ;continue ;if (delayed &&else /** * intel_uncore_forcewake_put - release a forcewake domain reference * @uncore: the intel_uncore structure * @fw_domains: forcewake domains to put references * * This function drops the device-level forcewakes for specified * domains obtained by intel_uncore_forcewake_get(). void intel_uncore_forcewake_put(struct intel_uncore *uncore,enum forcewake_domains fw_domains)unsigned long irqflags;if (!uncore->fw_get_funcs)return ;false );void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore,enum forcewake_domains fw_domains)unsigned long irqflags;if (!uncore->fw_get_funcs)return ;true );/** * intel_uncore_forcewake_flush - flush the delayed release * @uncore: the intel_uncore structure * @fw_domains: forcewake domains to flush void intel_uncore_forcewake_flush(struct intel_uncore *uncore,enum forcewake_domains fw_domains)struct intel_uncore_forcewake_domain *domain;unsigned int tmp;if (!uncore->fw_get_funcs)return ;false );if (hrtimer_cancel(&domain->timer))/** * intel_uncore_forcewake_put__locked - release forcewake domain references * @uncore: the intel_uncore structure * @fw_domains: forcewake domains to put references * * See intel_uncore_forcewake_put(). This variant places the onus * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore,enum forcewake_domains fw_domains)if (!uncore->fw_get_funcs)return ;false );void assert_forcewakes_inactive(struct intel_uncore *uncore)if (!uncore->fw_get_funcs)return ;"Expected all fw_domains to be inactive, but %08x are still on\n" ,void assert_forcewakes_active(struct intel_uncore *uncore,enum forcewake_domains fw_domains)struct intel_uncore_forcewake_domain *domain;unsigned int tmp;if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))return ;if (!uncore->fw_get_funcs)return ;"Expected %08x fw_domains to be active, but %08x are off\n" ,/* * Check that the caller has an explicit wakeref and we don't mistake * it for the auto wakeref. unsigned int actual = READ_ONCE(domain->wake_count);unsigned int expect = 1;if (uncore->fw_domains_timer & domain->mask)/* pending automatic release */ if (drm_WARN(&uncore->i915->drm, actual < expect,"Expected domain %d to be held awake by caller, count=%d\n" ,break ;/* * We give fast paths for the really cool registers. The second range includes * media domains (and the GSC starting from Xe_LPM+) #define NEEDS_FORCE_WAKE(reg) ({ \static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)if (offset < entry->start)return -1;else if (offset > entry->end)return 1;else return 0;/* Copied and "macroized" from lib/bsearch.c */ #define BSEARCH(key, base, num, cmp) ({ \unsigned int start__ = 0, end__ = (num); \while (start__ < end__) { \unsigned int mid__ = start__ + (end__ - start__) / 2; \int ret__ = (cmp)((key), (base) + mid__); \if (ret__ < 0) { \else if (ret__ > 0) { \else { \break ; \static enum forcewake_domainsstruct intel_uncore *uncore, u32 offset)const struct intel_forcewake_range *entry;if (IS_GSI_REG(offset))if (!entry)return 0;/* * The list of FW domains depends on the SKU in gen11+ so we * can't determine it statically. We use FORCEWAKE_ALL and * translate it here to the list of available domains. if (entry->domains == FORCEWAKE_ALL)return uncore->fw_domains;"Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n" ,return entry->domains;/* * Shadowed register tables describe special register ranges that i915 is * allowed to write to without acquiring forcewake. If these registers' power * wells are down, the hardware will save values written by i915 to a shadow * copy and automatically transfer them into the real register the next time * the power well is woken up. Shadowing only applies to writes; forcewake * must still be acquired when reading from registers in these ranges. * * The documentation for shadowed registers is somewhat spotty on older * platforms. However missing registers from these lists is non-fatal; it just * means we'll wake up the hardware for some register accesses where we didn't * really need to. * * The ranges listed in these tables must be sorted by offset. * * When adding new tables here, please also add them to * intel_shadow_table_check() in selftests/intel_uncore.c so that they will be * scanned for obvious mistakes or typos by the selftests. static const struct i915_range gen8_shadowed_regs[] = {static const struct i915_range gen11_shadowed_regs[] = {static const struct i915_range gen12_shadowed_regs[] = {/* * The rest of these ranges are specific to Xe_HP and beyond, but * are reserved/unused ranges on earlier gen12 platforms, so they can * be safely added to the gen12 table. static const struct i915_range dg2_shadowed_regs[] = {static const struct i915_range mtl_shadowed_regs[] = {static const struct i915_range xelpmp_shadowed_regs[] = {static int mmio_range_cmp(u32 key, const struct i915_range *range)if (key < range->start)return -1;else if (key > range->end)return 1;else return 0;static bool is_shadowed(struct intel_uncore *uncore, u32 offset)if (drm_WARN_ON(&uncore->i915->drm, !uncore->shadowed_reg_table))return false ;if (IS_GSI_REG(offset))return BSEARCH(offset,static enum forcewake_domainsstruct intel_uncore *uncore, i915_reg_t reg)return FORCEWAKE_RENDER;#define __fwtable_reg_read_fw_domains(uncore, offset) \enum forcewake_domains __fwd = 0; \if (NEEDS_FORCE_WAKE((offset))) \#define __fwtable_reg_write_fw_domains(uncore, offset) \enum forcewake_domains __fwd = 0; \const u32 __offset = (offset); \if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \#define GEN_FW_RANGE(s, e, d) \/* * All platforms' forcewake tables below must be sorted by offset ranges. * Furthermore, new forcewake tables added should be "watertight" and have * no gaps between ranges. * * When there are multiple consecutive ranges listed in the bspec with * the same forcewake domain, it is customary to combine them into a single * row in the tables below to keep the tables small and lookups fast. * Likewise, reserved/unused ranges may be combined with the preceding and/or * following ranges since the driver will never be making MMIO accesses in * those ranges. * * For example, if the bspec were to list: * * ... * 0x1000 - 0x1fff: GT * 0x2000 - 0x2cff: GT * 0x2d00 - 0x2fff: unused/reserved * 0x3000 - 0xffff: GT * ... * * these could all be represented by a single line in the code: * * GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT) * * When adding new forcewake tables here, please also add them to * intel_uncore_mock_selftests in selftests/intel_uncore.c so that they will be * scanned for obvious mistakes or typos by the selftests. static const struct intel_forcewake_range __gen6_fw_ranges[] = {static const struct intel_forcewake_range __vlv_fw_ranges[] = {static const struct intel_forcewake_range __chv_fw_ranges[] = {static const struct intel_forcewake_range __gen9_fw_ranges[] = {/* uncore range */ static const struct intel_forcewake_range __gen11_fw_ranges[] = {/* uncore range */ static const struct intel_forcewake_range __gen12_fw_ranges[] = {/* 0x0 - 0xaff: reserved /* 0x4000 - 0x48ff: gt /* 0x5200 - 0x53ff: render 0x5400 - 0x54ff: reserved /* 0x8160 - 0x817f: reserved /* 0x8500 - 0x87ff: gt 0x8800 - 0x8fff: reserved 0x9000 - 0x947f: gt /* 0x9560 - 0x95ff: always on /* 0xb400 - 0xbf7f: gt 0xb480 - 0xbfff: reserved /* 0xdc00 - 0xddff: render 0xde00 - 0xde7f: reserved 0xde80 - 0xe8ff: render /* 0xf000 - 0xffff: gt /* 0x14800 - 0x14fff: render 0x15000 - 0x16dff: reserved 0x16e00 - 0x1bfff: render /* 0x24000 - 0x2407f: always on /* 0x24180 - 0x241ff: gt /* 0x24a00 - 0x24a7f: render /* 0x25200 - 0x252ff: gt /* 0x25680 - 0x256ff: VD2 /* 0x25a80 - 0x25aff: VD2 /* 0x1c0000 - 0x1c2bff: VD0 0x1c2c00 - 0x1c2cff: reserved 0x1c2d00 - 0x1c2dff: VD0 0x1c2e00 - 0x1c3eff: reserved /* 0x1c8000 - 0x1ca0ff: VE0 0x1ca100 - 0x1cbeff: reserved /* 0x1cc000 - 0x1ccfff: VD0 /* 0x1d0000 - 0x1d2bff: VD2 0x1d2c00 - 0x1d2cff: reserved 0x1d2d00 - 0x1d2dff: VD2 0x1d2e00 - 0x1d3eff: reserved static const struct intel_forcewake_range __dg2_fw_ranges[] = {/* 0x0 - 0xaff: reserved /* 0x4b00 - 0x4fff: reserved /* 0x8160 - 0x817f: reserved /* 0x8500 - 0x87ff: gt 0x8800 - 0x8c7f: reserved /* 0x8d00 - 0x8dff: render (DG2 only) /* 0x9000 - 0x947f: gt /* 0x9560 - 0x95ff: always on /* 0x9680 - 0x96ff: render /* 0x9800 - 0xb4ff: gt 0xb500 - 0xbfff: reserved /* 0xdd00 - 0xddff: gt /* 0xde80 - 0xdfff: render 0xe000 - 0xe0ff: reserved /* 0xe900 - 0xe9ff: gt 0xea00 - 0xefff: reserved /* 0x10000 - 0x11fff: reserved 0x12000 - 0x127ff: always on /* 0x13200 - 0x133ff: VD2 (DG2 only) /* 0x15000 - 0x15fff: gt (DG2 only) /* 0x16e00 - 0x1ffff: render /* 0x24000 - 0x2407f: always on /* 0x24180 - 0x241ff: gt /* 0x24a00 - 0x24a7f: render /* 0x25200 - 0x252ff: gt /* 0x26000 - 0x27fff: render 0x28000 - 0x29fff: reserved /* 0x1c0000 - 0x1c2bff: VD0 0x1c2c00 - 0x1c2cff: reserved 0x1c2d00 - 0x1c2dff: VD0 0x1c2e00 - 0x1c3eff: VD0 /* 0x1c4000 - 0x1c6bff: VD1 0x1c6c00 - 0x1c6cff: reserved 0x1c6d00 - 0x1c6dff: VD1 /* 0x1c8000 - 0x1ca0ff: VE0 /* 0x1d0000 - 0x1d2bff: VD2 0x1d2c00 - 0x1d2cff: reserved 0x1d2d00 - 0x1d2dff: VD2 0x1d2e00 - 0x1d3dff: VD2 0x1d3e00 - 0x1d3eff: reserved /* 0x1d4000 - 0x1d6bff: VD3 0x1d6c00 - 0x1d6cff: reserved 0x1d6d00 - 0x1d6dff: VD3 /* 0x1d8000 - 0x1da0ff: VE1 /* 0x1e0000 - 0x1e2bff: VD4 0x1e2c00 - 0x1e2cff: reserved 0x1e2d00 - 0x1e2dff: VD4 0x1e2e00 - 0x1e3eff: reserved /* 0x1e4000 - 0x1e6bff: VD5 0x1e6c00 - 0x1e6cff: reserved 0x1e6d00 - 0x1e6dff: VD5 /* 0x1e8000 - 0x1ea0ff: VE2 /* 0x1f0000 - 0x1f2bff: VD6 0x1f2c00 - 0x1f2cff: reserved 0x1f2d00 - 0x1f2dff: VD6 0x1f2e00 - 0x1f3eff: reserved /* 0x1f4000 - 0x1f6bff: VD7 0x1f6c00 - 0x1f6cff: reserved 0x1f6d00 - 0x1f6dff: VD7 static const struct intel_forcewake_range __mtl_fw_ranges[] = {/* 0x4000 - 0x48ff: render /* 0x5200 - 0x53ff: render 0x5400 - 0x54ff: reserved /* 0x8140 - 0x815f: render /* 0x8200 - 0x87ff: gt 0x8800 - 0x8dff: reserved 0x8e00 - 0x8f7f: gt 0x8f80 - 0x8fff: reserved 0x9000 - 0x947f: gt /* 0x9560 - 0x95ff: always on /* 0x9680 - 0x96ff: render /* 0x9800 - 0xb4ff: gt 0xb500 - 0xbfff: reserved /* 0xd000 - 0xd3ff: always on /* 0xdd00 - 0xddff: gt /* 0xde80 - 0xdfff: render 0xe000 - 0xe0ff: reserved /* 0xea00 - 0x11fff: reserved 0x12000 - 0x127ff: always on /* 0x14800 - 0x153ff: gt /* 0x1a000 - 0x1bfff: render /* 0x24000 - 0x2407f: always on /* FIXME: WA to wake GT while triggering H2G */ /* * Note that the register ranges here are the final offsets after * translation of the GSI block to the 0x380000 offset. * * NOTE: There are a couple MCR ranges near the bottom of this table * that need to power up either VD0 or VD2 depending on which replicated * instance of the register we're trying to access. Our forcewake logic * at the moment doesn't have a good way to take steering into consideration, * and the driver doesn't even access any registers in those ranges today, * so for now we just mark those ranges as FORCEWAKE_ALL. That will ensure * proper operation if we do start using the ranges in the future, and we * can determine at that time whether it's worth adding extra complexity to * the forcewake handling to take steering into consideration. static const struct intel_forcewake_range __xelpmp_fw_ranges[] = {/* render GT range */ /* 0x116000 - 0x117fff: gsc 0x118000 - 0x119fff: reserved 0x11a000 - 0x11efff: gsc /* non-GT range */ /* 0x1c0000 - 0x1c3dff: VD0 0x1c3e00 - 0x1c3eff: reserved 0x1c3f00 - 0x1c3fff: VD0 /* 0x1c8000 - 0x1ca0ff: VE0 /* 0x1cc000 - 0x1cdfff: VD0 /* 0x1d0000 - 0x1d3dff: VD2 0x1d3e00 - 0x1d3eff: reserved /* 0x1da100 - 0x23ffff: reserved 0x240000 - 0x37ffff: non-GT range /* 0x381000 - 0x381fff: gt 0x382000 - 0x383fff: reserved 0x384000 - 0x384aff: gt 0x384b00 - 0x3851ff: reserved 0x385200 - 0x3871ff: gt 0x387200 - 0x387fff: reserved 0x388000 - 0x38813f: gt /* 0x388180 - 0x3881ff: always on /* 0x388300 - 0x38887f: gt 0x388880 - 0x388fff: reserved 0x389000 - 0x38947f: gt /* 0x389560 - 0x3895ff: always on /* 0x38a000 - 0x38afff: gt 0x38b000 - 0x38bfff: reserved /* 0x38d120 - 0x38dfff: gt 0x38e000 - 0x38efff: reserved 0x38f000 - 0x38ffff: gt /* 0x392000 - 0x3927ff: always on /* instance-based, see note above */ /* instance-based, see note above */ /* 0x393500 - 0x393bff: reserved static void struct intel_uncore *uncore)/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up * the chip from rc6 before touching it for real. MI_MODE is masked, static void struct intel_uncore *uncore,const i915_reg_t reg,const bool read)if (drm_WARN(&uncore->i915->drm,"Unclaimed %s register 0x%x\n" ,"read from" : "write to" ,/* Only report the first N failures */ static void struct intel_uncore *uncore,const i915_reg_t reg,const bool read)if (check_for_unclaimed_mmio(uncore))"Unclaimed access detected before %s register 0x%x\n" ,"read from" : "write to" ,static inline bool __must_checkstruct intel_uncore *uncore,const i915_reg_t reg, const bool read)if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug)return false ;/* interrupts are disabled and re-enabled around uncore->lock usage */ return true ;static inline void struct intel_uncore *uncore,const i915_reg_t reg, const bool read)/* interrupts are disabled and re-enabled around uncore->lock usage */ #define __vgpu_read(x) \static u## x \## x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \## x val = __raw_uncore_read## x(uncore, reg); \false , reg, val, sizeof (val), trace); \return val; \#define GEN2_READ_HEADER(x) \## x val = 0; \#define GEN2_READ_FOOTER \false , reg, val, sizeof (val), trace); \return val#define __gen2_read(x) \static u## x \## x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \## x(uncore, reg); \#define __gen5_read(x) \static u## x \## x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \## x(uncore, reg); \#undef __gen5_read#undef __gen2_read#undef GEN2_READ_FOOTER#undef GEN2_READ_HEADER#define GEN6_READ_HEADER(x) \unsigned long irqflags; \bool unclaimed_reg_debug; \## x val = 0; \true )#define GEN6_READ_FOOTER \if (unclaimed_reg_debug) \true ); \false , reg, val, sizeof (val), trace); \return valstatic noinline void ___force_wake_auto(struct intel_uncore *uncore,enum forcewake_domains fw_domains)struct intel_uncore_forcewake_domain *domain;unsigned int tmp;static inline void __force_wake_auto(struct intel_uncore *uncore,enum forcewake_domains fw_domains)/* Turn on all requested but inactive supported forcewake domains. */ if (fw_domains)#define __gen_fwtable_read(x) \static u## x \## x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \enum forcewake_domains fw_engine; \if (fw_engine) \## x(uncore, reg); \static enum forcewake_domainsstruct intel_uncore *uncore, i915_reg_t reg) {return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg));#undef __gen_fwtable_read#undef GEN6_READ_FOOTER#undef GEN6_READ_HEADER#define GEN2_WRITE_HEADER \true , reg, val, sizeof (val), trace); \#define GEN2_WRITE_FOOTER#define __gen2_write(x) \static void \## x(struct intel_uncore *uncore, i915_reg_t reg, u## x val, bool trace) { \## x(uncore, reg, val); \#define __gen5_write(x) \static void \## x(struct intel_uncore *uncore, i915_reg_t reg, u## x val, bool trace) { \## x(uncore, reg, val); \#undef __gen5_write#undef __gen2_write#undef GEN2_WRITE_FOOTER#undef GEN2_WRITE_HEADER#define GEN6_WRITE_HEADER \unsigned long irqflags; \bool unclaimed_reg_debug; \true , reg, val, sizeof (val), trace); \false )#define GEN6_WRITE_FOOTER \if (unclaimed_reg_debug) \false ); \#define __gen6_write(x) \static void \## x(struct intel_uncore *uncore, i915_reg_t reg, u## x val, bool trace) { \if (NEEDS_FORCE_WAKE(offset)) \## x(uncore, reg, val); \#define __gen_fwtable_write(x) \static void \## x(struct intel_uncore *uncore, i915_reg_t reg, u## x val, bool trace) { \enum forcewake_domains fw_engine; \if (fw_engine) \## x(uncore, reg, val); \static enum forcewake_domainsstruct intel_uncore *uncore, i915_reg_t reg)return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg));#undef __gen_fwtable_write#undef GEN6_WRITE_FOOTER#undef GEN6_WRITE_HEADER#define __vgpu_write(x) \static void \## x(struct intel_uncore *uncore, i915_reg_t reg, u## x val, bool trace) { \true , reg, val, sizeof (val), trace); \## x(uncore, reg, val); \#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \do { \## _write8; \## _write16; \## _write32; \while (0)#define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \do { \## _read8; \## _read16; \## _read32; \## _read64; \while (0)#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \do { \## _reg_write_fw_domains; \while (0)#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \do { \## _reg_read_fw_domains; \while (0)static int __fw_domain_init(struct intel_uncore *uncore,enum forcewake_domain_id domain_id,struct intel_uncore_forcewake_domain *d;if (i915_inject_probe_failure(uncore->i915))return -ENOMEM;sizeof (*d), GFP_KERNEL);if (!d)return -ENOMEM;
Messung V0.5 C=94 H=96 G=94
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