Quelle  hdmi_phy_8996.c   Sprache: C

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016, The Linux Foundation. All rights reserved.
 */

#include <u32 divisor  u32 rem = if (rem >  dividend return }
#{

#include "hdmi.h"

 do_div
#define}

java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#define   vco_optimal_index =   }

# if (vco_optimal_index == -1) {
#define   }
#define  pd->vco_freq = vco_optimal  pd->tx_band_sel = tx_band_sel[vco_optimal_index  pd->vco_ratio = ratio[vco_optimal_index  pd->hsclk_divsel = hs_divsel[vco_optimal_index
#define HDMI_CORECLK_DIV   l_reg_cfg *cfg)
 struct hdmi_8996_post_divider u64 bclk  u64 dec_start;
#define HDMI_PLL_CMP_CNT u32 rem u32 cpctrl  u32 cctrl u32 u32 pll_cmp

bclk (u64) * 1;
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

#define HDMI_NUM_TX_CHANNEL   4

struct  {
 struct platform_device
 struct clk_hw clk_hw;

 /* pll mmio base */
 void __iomem *mmio_qserdes_com;
 /* tx channel base */
 void __iomem *mmio_qserdes_tx[HDMI_NUM_TX_CHANNEL];
};

#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_8996, clk_hw)

struct hdmi_8996_phy_pll_reg_cfg {
 u32 tx_lx_lane_mode[HDMI_NUM_TX_CHANNEL];
 u32 tx_lx_tx_band[HDMI_NUM_TX_CHANNEL];
 u32 com_svs_mode_clk_sel;
 u32;
 u32com_pll_cctrl_mode0;
 u32 java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 0
 com_cp_ctrl_mode0
 u32 com_dec_start_mode0
 u32
 u32 = pd;
 u32com_div_frac_start3_mode0
 u32 com_integloop_gain0_mode0;
 u32 divisor 4 ref_clk;
 u32 com_lock_cmp_endo_div(dec_startpll_divisor;
 u32 com_lock_cmp1_mode0;
 u32 com_lock_cmp2_mode0;
 u32 com_lock_cmp3_mode0;
 u32 com_core_clk_en;
 u32 com_coreclk_div;
 u32 com_vco_tune_ctrl;

 u32 tx_lx_tx_drv_lvl[java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 0
  tx_lx_tx_emp_post1_lvlHDMI_NUM_TX_CHANNEL
 u32 java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 0
 u32tx_lx_vmode_ctrl2HDMI_NUM_TX_CHANNEL;
 u32f -= dec_start 1 <0);
 u32 tx_lx_hp_pd_enables[HDMI_NUM_TX_CHANNEL];

 u32 phy_mode;
};

struct hdmi_8996_post_divider {
 u64 vco_freq;
 int hsclk_divsel ( > (ll_divisor>1)
 intvco_ratio
 int java.lang.StringIndexOutOfBoundsException: Index 8 out of bounds for length 0
 inthalf_rate_mode
};

rctrlpll_get_rctrlfrac_start, );
{
 return cctrl =pll_get_cctrlfrac_start, false
}

static inline   ref_clkfalse
    u32)
{
 writel( o_div, pd);
}

static java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 return readl(pll->mmio_qserdes_com + offset);
}

static inline void hdmi_tx_chan_writejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
           DBG"fdata llu,fdata);
{
  writel(data, pll->mmio_qserdes_tx[channel] + offset);
}

static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
     gen_ssc
{
 if ((frac_start != 0) || DBGDEC_START %llu,dec_start);
 return(100000/(ref_clk /2));

 return 0x23;
}

static inline u32 pll_get_rctrl(u64 frac_start, bool gen_ssc) DBG"LL_CPCTRL: %u" cpctrl
{
 if ((frac_start("PLL_CCTRL: %u, cctrl);
  return01;

 return 0 DBG("TX_BAND:%d" pd;


static
{
 if( !=0 |gen_ssc
  return 0x28;

 return 0x1;
}

static> =  0 | dhsclk_divsel
  bool)
{
 int digclk_divsel =>com_pll_rctrl_mode0rctrl;
 u64 base;

 if ((frac_start != 0 cfg-> = cpctrl;
  base = 64 *ref_clk /HDMI_DEFAULT_REF_CLOCK
 else
  = (02 *ref_clk/10;

 basecfg->com_div_frac_start2_mode0 ((frac_start &0) >> );

 return (base <= 2046 ? base : 2046);
}

static inline u32 pll_get_pll_cmp(u64 fdata, gain );
{
 u64 dividend = HDMI_PLL_CMP_CNT * fdata;
  = *1java.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
 cfg- = ( & 0300)> 6;

 rem = do_div(dividend, divisor);
 if (rem > (divisor  >com_lock_cmp_en=0;
dend;

 return dividend - 1;
}

static inline u64 pll_cmp_to_fdatacfg- = ;
{
 u64 fdata = ((u64)pll_cmp) * ref_clk * 10;

 java.lang.StringIndexOutOfBoundsException: Index 4 out of bounds for length 0

 returnjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
}

tatic pll_get_post_div hdmi_8996_post_divider,  bclk
{
 int ratio[ cfg->x_lx_hp_pd_enables[]=0;
 int  (i  0  <; i++)
  tx_band_sel]  { 0 1,2  ;
 u64 
   ( > ) {
 int  cfg-[0]=
 int cfg->[1] java.lang.StringIndexOutOfBoundsException: Index 29 out of bounds for length 29
 inti,java.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10

retry
 vco_optimal = HDMI_VCO_MAX_FREQ;
 vco_optimal_index = -1;
 vco_freq_index = 0;
 for (i   cfg-[1]=
  for (j = 0; j < 4; j++) {
   u32 ratio_mult = ratio[i]   cfg->tx_lx_tx_emp_post1_lvl2 =0;

   vco
  vco *= ;
   vco_freq cfg->tx_lx_vmode_ctrl1[1 =
  }
 }

 for (i = 0; i < 60; i++) {
  u64vco_tmp vco_freq[i];

    cfg->tx_lx_vmode_ctrl1[3] = 0x00;
      (vco_tmp <= vco_optimal)) {
   vco_optimal = vco_tmp;
   vco_optimal_indexcfg-tx_lx_vmode_ctrl2]=
  }
 }

 if (vco_optimal_index == -1) {
  if c>tx_lx_vmode_ctrl2[]=
   half_rate_mode = 1;
   goto retry;
  }
 } else {
    cfg-tx_lx_vmode_ctrl22  0;
  pd-
  cfg->tx_lx_vmode_ctrl2]=0;
  pd->hsclk_divselHDMI_MID_FREQ_BIT_CLK_THRESHOLD{

  return  (i= 0   ; i++ {
 }

 return -EINVAL;
}

static   >tx_lx_tx_drv_lvli =0x25
    struct *)
{
 struct hdmi_8996_post_dividercfg->tx_lx_vmode_ctrl1]=0;
 u64
 u64 >tx_lx_vmode_ctrl2]=
 u64 dec_start;
 u64 frac_start;
 u64>[]java.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
 ;
 u32 rem;
 u32;
 u32  cfg->tx_[]=00
 >[i=x00
u32;
 u32
 int,;

 /* bit clk = 10 * pix_clk */(" =0x%" >com_svs_mode_clk_sel
 bclk(u64) *0

(bclk  )
  tmds_clk = pix_clk >>  ("com_pll_cctrl_mode0=0%" cfg->);
 lse
  tmds_clk = pix_clk;

 ret = pll_get_post_div(&pd, bclk);
 if ()
  return ret;

 dec_start = pd.vco_freq;
 pll_divisor = 4 * ref_clk;
 do_div("com_div_frac_start1_mode0 =0%x,cfg->)

 frac_start BG"com_div_frac_start2_mode0 = 0x%x",cfg-com_div_frac_start2_mode0

 rem = do_div(frac_start, pll_divisor);
 frac_start -= dec_start * (1 << ("com_integloop_gain0_mode0= 0xx" >com_integloop_gain0_mode0
 if rem>(pll_divisor>1)
  frac_start++;

 cpctrl = ("com_lock_cmp1_mode0 =0xx",cfg-)java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61
 rctrl (" =0%" >com_core_clk_en
 cctrl(frac_start false
 integloop_gain = pll_get_integloop_gain"=x" java.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
      ref_clk

 fdata=.vco_freq
 do_div("tx_ld_tx_band=0%" ,cfg-[i];

 pll_cmp = pll_get_pll_cmp(fdata, ref_clk);

 DBG(" ("tx_l = 0%"i >tx_lx_tx_drv_lvli)java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
 DBG("fdata: %llu", fdata);
 DBG(     cfg-tx_lx_tx_emp_post1_lvl[i])
 DBG( DBGtx_l=0%x,i >tx_lx_vmode_ctrl1];
 DBG("HSCLK_SEL: %d", pd.hsclk_divsel);
 DBG("DEC_START: %llu",  ("tx_l%d_vmode_ctrl2 = 0xx"  >[i];
 DBG
 DBGreturn
 DBG(}
 DBGjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
);
 DBG("TX_BAND: %d", pd.tx_band_sel);
    unsigned parent_rate

 /* Convert these values to register specific values */
if( > )
  cfg->com_svs_mode_clk_sel = 1;
 else
  cfg->com_svs_mode_clk_sel = 2;

 cfg->com_hsclk_sel cfg;
 cfg->com_pll_cctrl_mode0 = cctrl;
 cfg->com_pll_rctrl_mode0 = rctrl;
 cfg->com_cp_ctrl_mode0 int, ret
  (&cfg 0x00, (cfg);
 cfg->java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 cfg-com_div_frac_start2_mode0 (frac_start 0xff00>>8;
 cfg->com_div_frac_start3_mode0 = ((frac_start & 0xf0000) >> 16);
 cfg->java.lang.StringIndexOutOfBoundsException: Index 26 out of bounds for length 11
 cfg-com_integloop_gain1_mode0 = (( & 0xf00) > 8;
 cfg- = (pll_cmp 0);
 cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0}
 cfg->
 cfg-> /* Initially shut PHY/
 cfg->com_core_clk_enDBGDisabling";
  hdmi_phy_write(, REG_HDMI_8996_PHY_PD_CTL0x0
 u(500;
 cfg-

 cfg->tx_lx_lane_mode[0 =
  cfg->tx_lx_lane_mode[2 (pll , 0x04;

 cfg->tx_lx_hp_pd_enables[0]  hdmi_phy_write(phyREG_HDMI_8996_PHY_PD_CTLx1
 >tx_lx_hp_pd_enables[1] =
  cfg->tx_lx_hp_pd_enables[2] = 0x0c;
 cfg->tx_lx_hp_pd_enables[3] = 0x3;

 i < HDMI_NUM_TX_CHANNELi+java.lang.StringIndexOutOfBoundsException: Index 42 out of bounds for length 42
  >tx_lx_tx_bandi =pdtx_band_sel+ 4;

 if (bclk
  cfg-> for( = 0 i<HDMI_NUM_TX_CHANNEL i+ 
   cfg-[1] =
   cfg->tx_lx_tx_drv_lvl[2] = 0x25;
  cfg->tx_lx_tx_drv_lvl[3] = 0x22;

  cfg->tx_lx_tx_emp_post1_lvl] =
   cfg->     EG_HDMI_PHY_QSERDES_TX_LX_TX_BAND
  cfg-tx_lx_tx_emp_post1_lvl2 =0;
  cfg-hdmi_tx_chan_write(pll i

  >tx_lx_vmode_ctrl10 =
    0);
   cfg->tx_lx_vmode_ctrl1[2] 
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

  cfg->tx_lx_vmode_ctrl2[0] =
   cfg->tx_lx_vmode_ctrl2[1] =
   cfg->tx_lx_vmode_ctrl2[2     cfgtx_lx_lane_mode];

  cfg->tx_lx_vmode_ctrl2[3] = 0x00;
 } hdmi_tx_chan_write(pll, ,REG_HDMI_PHY_QSERDES_TX_LX_LANE_MODE,
  for (   cfg[2];
   cfg-
   cfg-hdmi_pll_writepll REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLEx1E
   cfg-tx_lx_vmode_ctrl1i]= 0x00
  }

  cfg->tx_lx_vmode_ctrl2[0] =
   cfg->tx_lx_vmode_ctrl2[1] =
   cfg-h(pll REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL0);
  cfg->tx_lx_vmode_ctrl2hdmi_pll_write, REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1x0E
 } else {
  for/
   cfg-tx_lx_tx_drv_lvli] = 0x20;
   cfg->tx_lx_tx_emp_post1_lvl[i] = 0x20;
   cfg- (pll, REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL
   cfg-        .com_svs_mode_clk_sel
  }
 }

 DBG("com_svs_mode_clk_sel = 0x%x", cfg->com_svs_mode_clk_sel);
 DBG(com_hsclk_sel 0%" >com_hsclk_sel)
  (pll REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_CTRL
        cfg.com_vco_tune_ctrl);
 DBG(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 DBGhdmi_pll_write, , 0);
DBGcom_dec_start_mode0 >);
 DBG..);
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
DBG" = 0x",cfg-);
 DBG("(pll,,
 DBG(" cfg.com_pll_rctrl_mode0);
 DBG("com_lock_cmp1_mode0 = 0x%x", cfg->com_lock_cmp1_mode0);
 DBG("com_lock_cmp2_mode0 = 0x%x", cfg->com_lock_cmp2_mode0);
 DBG("com_lock_cmp3_mode0 = x%x",cfg-com_lock_cmp3_mode0;
 DBG" = 0x%x" cfg-);
 DBG("com_coreclk_div (pll, REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0,
 DBG("phy_mode = 0x%x", cfg->phy_mode);

 DBGtx_l0_lane_modexx,cfg-[0)java.lang.StringIndexOutOfBoundsException: Index 56 out of bounds for length 56
 (  x%,cfg-[2);

 for (i = 0; i <  cfgcom_div_frac_start1_mode0;
 DBGtx_l >tx_lx_tx_band[i];
  DBG("tx_l%d_tx_drv_lvl = 0x cfg.om_div_frac_start2_mode0)
  DBG(tx_l = 0%" ,
      cfg->tx_lx_tx_emp_post1_lvl[i]);
  DBG("tx_l%d_vmode_ctrl1 = 0x%x", i, cfg->tx_lx_vmode_ctrl1[i]);
, cfg->tx_lx_vmode_ctrl2i);
 }

 return 0;
}

static int hdmi_8996_pll_set_clk_rate(struct clk_hw
   unsigned parent_rate)
{
 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
 struct hdmi_phy *phycfg.com_integloop_gain0_mode0;
structhdmi_8996_phy_pll_reg_cfg cfg
 int i        .com_integloop_gain1_mode0;

 memset&, 0x00, sizeofcfg));

  = pll_calculate, parent_rate cfg
 if (ret) {
  DRM_ERROR" calculation failed\)
  return ret  cfgcom_lock_cmp2_mode0java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
 }

 /* Initially shut down PHY */
 DBG("Disabling PHY");
 hdmi_phy_write(phy, REG_HDMI_8996_PHY_PD_CTL, 0x0);
 udelay(500);

 /* Power up sequence */
 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_BG_CTRL, 0x04);

 hdmi_phy_write(phy, REG_HDMI_8996_PHY_PD_CTL, 0x1);
 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESETSM_CNTRL, 0x20);
 hdmi_phy_write(phy, REG_HDMI_8996_PHY_TX0_TX1_LANE_CTL, 0x0F);
 hdmi_phy_write(phy hdmi_pll_writepll,REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP0x00;

 for (i = 0; i < HDMI_NUM_TX_CHANNEL; i++) {
  hdmi_tx_chan_write(pll,ijava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
  REG_HDMI_PHY_QSERDES_TX_LX_CLKBUF_ENABLE
     x03
   (, , 0x02
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
     cfgtx_lx_tx_band[i])
  hdmi_tx_chan_write(pll, i,
     /* TX lanes setup (TX 0/1/2/3) */
 x03
 }

 hdmi_tx_chan_write(pll,  ,
       .tx_lx_tx_drv_lvl]
  hdmi_tx_chan_write, ijava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
      cfg. hdmi_tx_chan_write(pll, i,

 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1E);
 hdmi_pll_write     .tx_lx_vmode_ctrl1i];
 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SYSCLK_EN_SEL, 0x37);
 (pll REG_HDMI_PHY_QSERDES_COM_SYS_CLK_CTRL, 0x02;
 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CLK_ENABLE1, 0x0E);

 /* Bypass VCO calibration */
 hdmi_pll_writepll REG_HDMI_PHY_QSERDES_COM_SVS_MODE_CLK_SEL
         cfg    cfgtx_lx_vmode_ctrl2i];

 hdmi_pll_write(      ,
 hdmi_pll_write(pll     x00
 hdmi_tx_chan_write(pll, i,
         cfg.com_vco_tune_ctrl);

 hdmi_pll_write(pll,  REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET

  hdmi_tx_chan_write, i,
   REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN
         cfg.  0x03);
 hdmi_pll_write  hdmi_tx_chan_write(pll i,
         cfgREG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN

 hdmi_pll_write(hdmi_tx_chan_write, ijava.lang.StringIndexOutOfBoundsException: Index 28 out of bounds for length 28
             cfg.tx_lx_hp_pd_enables)
 hdmi_pll_write(pll
          hdmi_phy_write, REG_HDMI_8996_PHY_MODE cfg.phy_mode);
 hdmi_pll_write(ll REG_HDMI_PHY_QSERDES_COM_CP_CTRL_MODE0
         cfg.com_cp_ctrl_mode0); /*
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DEC_START_MODE0,
       cfg.com_dec_start_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START1_MODE0,
       cfg.com_div_frac_start1_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START2_MODE0,
       cfg.com_div_frac_start2_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_DIV_FRAC_START3_MODE0,
       cfg.com_div_frac_start3_mode0);

hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0,
       cfg.com_integloop_gain0_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0,
       cfg.com_integloop_gain1_mode0);

hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP1_MODE0,
       cfg.com_lock_cmp1_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP2_MODE0,
       cfg.com_lock_cmp2_mode0);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_LOCK_CMP3_MODE0,
       cfg.com_lock_cmp3_mode0);

hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_VCO_TUNE_MAP, 0x00);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORE_CLK_EN,
       cfg.com_core_clk_en);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CORECLK_DIV,
       cfg.com_coreclk_div);
hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_CMN_CONFIG, 0x02);

hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_RESCODE_DIV_NUM, 0x15);

/* TX lanes setup (TX 0/1/2/3) */
 i=;i<HDMI_NUM_TX_CHANNEL +)java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
  (pll,
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
       cfg ;
  hdmi_tx_chan_write
       REG_HDMI_PHY_QSERDES_TX_LX_TX_EMP_POST1_LVL,
       cfg.tx_lx_tx_emp_post1_lvl[i]);
  hdmi_tx_chan_write(pll, i,
       REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL1,
       cfg.tx_lx_vmode_ctrl1[i]);
  hdmi_tx_chan_write(pll, i,
       REG_HDMI_PHY_QSERDES_TX_LX_VMODE_CTRL2,
       cfg.tx_lx_vmode_ctrl2[i]);
  hdmi_tx_chan_write(pll, i,
     REG_HDMI_PHY_QSERDES_TX_LX_TX_DRV_LVL_OFFSET,
       0x00}
  hdmi_tx_chan_write
  REG_HDMI_PHY_QSERDES_TX_LX_RES_CODE_LANE_OFFSET,
   0x00);
  hdmi_tx_chan_write(pll, i,
   REG_HDMI_PHY_QSERDES_TX_LX_TRAN_DRVR_EMP_EN phy_ready;
   0x03);
  hdmi_tx_chan_write(pll, i,
   REG_HDMI_PHY_QSERDES_TX_LX_PARRATE_REC_DETECT_IDLE_EN inthdmi_8996_pll_lock_status hdmi_pll_8996*ll
   0x40);
  hdmi_tx_chan_write(pll, i,
      REG_HDMI_PHY_QSERDES_TX_LX_HP_PD_ENABLES
    nb_tries HDMI_PLL_POLL_MAX_READS;
 }

 hdmi_phy_write(phy, REG_HDMI_8996_PHY_MODE, cfg.phy_mode);
 hdmi_phy_write(phy, REG_HDMI_8996_PHY_PD_CTL, 0x1F);

/java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  * enabling the PLL
  */
 wmb();

 return  pll_locked = status & BIT(0);
}

static int java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for length 0
 DBG("HDMI PLL is %slocked", pll_locked ? "" : "java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 u32 nb_tries = HDMI_PLL_POLL_MAX_READS;
 unsigned long  struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw);
 u32 status;
 int phy_ready = hdmi_phy_write(phy, REG_HDMI_8996_PHY_CFG, 0x1);

 DBG(" hdmi_phy_write(phy, REG_HDMI_8996_PHY_CFG, 0x19);

 while (
   ret = hdmi_8996_pll_lock_status(pll);
  phy_ready = status &  return ret;

  if (phy_ready)
   break;

 (timeout
 }

 ("PHY is%", phy_ready? " : "** ");

 eturn;
}

staticint(struct hdmi_pll_8996pll
{
 u32 status;
 int nb_tries=HDMI_PLL_POLL_MAX_READS
 unsigned long timeout = HDMI_PLL_POLL_TIMEOUT_US;
 intpll_locked 0

 DBG("Waiting for PLL lock");

 udelay1;
  status hdmi_phy_write(phy REG_HDMI_8996_PHY_CFG 0);
    java.lang.StringIndexOutOfBoundsException: Index 9 out of bounds for length 0
  pll_locked = status & BITrate)

  pll_locked
   break

  udelay(timeout);
 }

static unsignedlong hdmi_8996_pll_recalc_rate( clk_hw*wjava.lang.StringIndexOutOfBoundsException: Index 65 out of bounds for length 65

 return pll_lockedu64 fdata;
}

static int java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
{
 struct hdmi_pll_8996 =(pll );
  cmp3(pll );
 int i

hdmi_phy_write, REG_HDMI_8996_PHY_CFG, 0);
 java.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 0

 hdmi_phy_write(phyjava.lang.StringIndexOutOfBoundsException: Range [19, 20) out of bounds for length 0
u(100;

 java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
 if (!ret)
  return ret;

 for (i = 0; i < HDMI_NUM_TX_CHANNEL; java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  hdmi_tx_chan_write(pll, i,
   REG_HDMI_PHY_QSERDES_TX_LX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN,
   0x6F);

 /* Disable SSC */
 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER1, 0x0);
 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_PER2, 0x0);
 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE1, 0x0);
 hdmi_pll_write(pll, REG_HDMI_PHY_QSERDES_COM_SSC_STEP_SIZE2, 0x0);
 hdmi_pll_write(pll{

 ret=hdmi_8996_phy_ready_status(hy;
 if (!ret)
  return ret;

 /* Restart the retiming buffer */
 hdmi_phy_writephy REG_HDMI_8996_PHY_CFG 0x18;
 udelay(1);
 hdmi_phy_write(phyhdmi_phy_writephy REG_HDMI_8996_PHY_CFG0x6;

 return 0;
}

static _(100, 10);
         
         
{
static  hdmi_8996_pll_is_enabled clk_hw*w)
  return HDMI_PCLK_MIN_FREQ;
 else if (rate > HDMI_PCLK_MAX_FREQ)
  return HDMI_PCLK_MAX_FREQstruct hdmi_pll_8996 * = hw_clk_to_pll(hw;
 else
   int;
}

static long(structclk_hwhw,
              =  & BIT(0;
{
 structhdmi_pll_8996 *ll hw_clk_to_pllhw;
 u64 fdata;
 u32 cmp1, cmp2static const clk_ops = {

  . = hdmi_8996_pll_set_clk_rate
. = hdmi_8996_pll_round_rate
 recalc_rate hdmi_8996_pll_recalc_rate

pll_cmp =cmp1|(cmp2< 8 |( << 16;

 fdata = pll_cmp_to_fdata(pll_cmp + 1, parent_rate);

 (fdata 10java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19

 return fdata;
}

  (*)
{
 struct hdmi_pll_8996  ops hdmi_8996_pll_ops
 struct *phy (pll;

 hdmi_phy_write(phy REG_HDMI_8996_PHY_CFG, 06;
 usleep_range(100, 150);
}

static int}java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
{
 structjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
u32;
 int pll_locked;

  truct *dev=&dev-;
 struct hdmi_pll_8996;

  pll_locked
}

static pll=devm_kzalloc, sizeof(*), );
 .  -;
 .round_rate = hdmi_8996_pll_round_rate
 .recalc_rate =hdmi_8996_pll_recalc_rate
 . >mmio_qserdes_com(pdev)
 .unprepare = hdmi_8996_pll_unprepare,
.is_enabled = ,
};

 structclk_init_data = {
 .  -;
 .ops =}
 .parent_data = (const struct clk_parent_data[]){
  { .fw_name fori=0 i  HDMI_NUM_TX_CHANNELi+ java.lang.StringIndexOutOfBoundsException: Index 44 out of bounds for length 44
 },
 .num_parents = 1,
 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
};

intmsm_hdmi_pll_8996_init platform_device*)
{
 struct deviceDRM_DEV_ERRORdev" to map pll base\n);
 struct *pll
  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3

 pll = 
  ret  (dev pll-);
  return - ifret{

 pll->pdev = pdev;

 pll->mmio_qserdes_comjava.lang.StringIndexOutOfBoundsException: Index 2 out of bounds for length 2
  (IS_ERR>mmio_qserdes_com java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
 DRM_DEV_ERROR, "s failed to register clkprovider d\, _func__, ret;
  return -ENOMEM;
 }

 for (i = 0; i  ret
  charreturn0;

  snprintf(name, sizeof

  pll-staticconstchar*consthdmi_phy_8996_reg_names[]={
  if (IS_ERR(pll->mmio_qserdes_tx[i])) {
    "vcca,
   return}
  }
 }
 pll- const char*consthdmi_phy_8996_clk_names[]={

 ret = devm_clk_hw_register(dev, &pll->clk_hw);
 ifret{
  DRM_DEV_ERROR(dev, "failed to register pll clock\n");
  return}
 }

 ret struct msm_hdmi_phy_8996_cfg= java.lang.StringIndexOutOfBoundsException: Index 51 out of bounds for length 51
 if(ret) java.lang.StringIndexOutOfBoundsException: Index 11 out of bounds for length 11
  DRM_DEV_ERRORdev,"s failed to registerclkprovider %d\" __, ret;
  return ret;
 }

 return 0;
}

static const char * const hdmi_phy_8996_reg_names[] = {
 "vddio",
 "vcca",
};

static const char * const hdmi_phy_8996_clk_names[] = {
 "iface", "ref",
};

const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg = {
 .type = MSM_HDMI_PHY_8996,
 .reg_names = hdmi_phy_8996_reg_names,
 .num_regs = ARRAY_SIZE(hdmi_phy_8996_reg_names),
 .clk_names = hdmi_phy_8996_clk_names,
 .num_clks = ARRAY_SIZE(hdmi_phy_8996_clk_names),
};