// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark <robdclark@gmail.com> #include <linux/clk-provider.h>#include <linux/delay.h>#include "hdmi.h" struct hdmi_pll_8960 {struct platform_device *pdev;struct clk_hw clk_hw;void __iomem *mmio;unsigned long pixclk;#define hw_clk_to_pll(x) container_of(x, struct hdmi_pll_8960, clk_hw)/* * HDMI PLL: * * To get the parent clock setup properly, we need to plug in hdmi pll * configuration into common-clock-framework. struct pll_rate {unsigned long rate;int num_reg;struct {/* NOTE: keep sorted highest freq to lowest: */ static const struct pll_rate freqtbl[] = {/* 1080p60/1080p50 case */ /* 720p60/720p50/1080i60/1080i50/1080p24/1080p30/1080p25 */ /* 480p60/480i60 */ /* 576p50/576i50 */ /* 640x480p60 */ static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data)static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg)return readl(pll->mmio + reg);static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)return platform_get_drvdata(pll->pdev);static int hdmi_pll_enable(struct clk_hw *hw)struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);struct hdmi_phy *phy = pll_get_phy(pll);int timeout_count, pll_lock_retry = 10;unsigned int val;"" );/* Assert PLL S/W reset */ /* Wait for a short time before de-asserting * to allow the hardware to complete its job. * This much of delay should be fine for hardware * to assert and de-assert. /* De-assert PLL S/W reset */ /* Assert PHY S/W reset */ /* * Wait for a short time before de-asserting to allow the hardware to * complete its job. This much of delay should be fine for hardware to * assert and de-assert. /* De-assert PHY S/W reset */ /* Wait 10 us for enabling global power for PHY */ while (--pll_lock_retry > 0) {/* are we there yet? */ if (val & HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK)break ;if (--timeout_count > 0)continue ;/* * PLL has still not locked. * Do a software reset and try again * Assert PLL S/W reset first /* * Wait for a short duration for the PLL calibration * before checking if the PLL gets locked return 0;static void hdmi_pll_disable(struct clk_hw *hw)struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);struct hdmi_phy *phy = pll_get_phy(pll);unsigned int val;"" );/* Make sure HDMI PHY/PLL are powered down */ static const struct pll_rate *find_rate(unsigned long rate)int i;for (i = 1; i < ARRAY_SIZE(freqtbl); i++)if (rate > freqtbl[i].rate)return &freqtbl[i - 1];return &freqtbl[i - 1];static unsigned long hdmi_pll_recalc_rate(struct clk_hw *hw,unsigned long parent_rate)struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);return pll->pixclk;static long hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,unsigned long *parent_rate)const struct pll_rate *pll_rate = find_rate(rate);return pll_rate->rate;static int hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,unsigned long parent_rate)struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw);const struct pll_rate *pll_rate = find_rate(rate);int i;"rate=%lu" , rate);for (i = 0; i < pll_rate->num_reg; i++)return 0;static const struct clk_ops hdmi_pll_ops = {static const struct clk_parent_data hdmi_pll_parents[] = {"pxo" , .name = "pxo_board" },static struct clk_init_data pll_init = {"hdmi_pll" ,int msm_hdmi_pll_8960_init(struct platform_device *pdev)struct device *dev = &pdev->dev;struct hdmi_pll_8960 *pll;int i, ret;/* sanity check: */ for (i = 0; i < (ARRAY_SIZE(freqtbl) - 1); i++)if (WARN_ON(freqtbl[i].rate < freqtbl[i + 1].rate))return -EINVAL;sizeof (*pll), GFP_KERNEL);if (!pll)return -ENOMEM;"hdmi_pll" );if (IS_ERR(pll->mmio)) {"failed to map pll base\n" );return -ENOMEM;if (ret < 0) {"failed to register pll clock\n" );return ret;if (ret) {"%s: failed to register clk provider: %d\n" , __func__, ret);return ret;return 0;
Messung V0.5 C=96 H=93 G=94
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