Quelle  a5xx.xml   Sprache: XML

<?xml version="1.0" encoding="UTF-8"?>
<database xmlns="http://nouveau.freedesktop.org/"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<import file="freedreno_copyright.xml"/>
<import file="adreno/adreno_common.xml"/>
<import file="adreno/adreno_pm4.xml"/>

<enum name="a5xx_color_fmt">
 <value value="0x02" name="RB5_A8_UNORM"/>
 <value value="0x03" name="RB5_R8_UNORM"/>
 <value value="0x04" name="RB5_R8_SNORM"/>
 <value value="0x05" name="RB5_R8_UINT"/>
 <value value="0x06" name="RB5_R8_SINT"/>
 <value value="0x08" name="RB5_R4G4B4A4_UNORM"/>
 <value value="0x0a" name="RB5_R5G5B5A1_UNORM"/>
 <value value="0x0e" name="RB5_R5G6B5_UNORM"/>
 <value value="0x0f" name="RB5_R8G8_UNORM"/>
 <value value="0x10" name="RB5_R8G8_SNORM"/>
 <value value="0x11" name="RB5_R8G8_UINT"/>
 <value value="0x12" name="RB5_R8G8_SINT"/>
 <value value="0x15" name="RB5_R16_UNORM"/>
 <value value="0x16" name="RB5_R16_SNORM"/>
 <value value="0x17" name="RB5_R16_FLOAT"/>
 <value value="0x18" name="RB5_R16_UINT"/>
 <value value="0x19" name="RB5_R16_SINT"/>
 <value value="0x30" name="RB5_R8G8B8A8_UNORM"/>
 <value value="0x31" name="RB5_R8G8B8_UNORM"/>
 <value value="0x32" name="RB5_R8G8B8A8_SNORM"/>
 <value value="0x33" name="RB5_R8G8B8A8_UINT"/>
 <value value="0x34" name="RB5_R8G8B8A8_SINT"/>
 <value value="0x37" name="RB5_R10G10B10A2_UNORM"/>  <!-- GL_RGB10_A2 -->
 <value value="0x3a" name="RB5_R10G10B10A2_UINT"/>   <!-- GL_RGB10_A2UI -->
 <value value="0x42" name="RB5_R11G11B10_FLOAT"/>    <!-- GL_R11F_G11F_B10F -->
 <value value="0x43" name="RB5_R16G16_UNORM"/>
 <value value="0x44" name="RB5_R16G16_SNORM"/>
 <value value="0x45" name="RB5_R16G16_FLOAT"/>
 <value value="0x46" name="RB5_R16G16_UINT"/>
 <value value="0x47" name="RB5_R16G16_SINT"/>
 <value value="0x4a" name="RB5_R32_FLOAT"/>
 <value value="0x4b" name="RB5_R32_UINT"/>
 <value value="0x4c" name="RB5_R32_SINT"/>
 <value value="0x60" name="RB5_R16G16B16A16_UNORM"/>
 <value value="0x61" name="RB5_R16G16B16A16_SNORM"/>
 <value value="0x62" name="RB5_R16G16B16A16_FLOAT"/>
 <value value="0x63" name="RB5_R16G16B16A16_UINT"/>
 <value value="0x64" name="RB5_R16G16B16A16_SINT"/>
 <value value="0x67" name="RB5_R32G32_FLOAT"/>
 <value value="0x68" name="RB5_R32G32_UINT"/>
 <value value="0x69" name="RB5_R32G32_SINT"/>
 <value value="0x82" name="RB5_R32G32B32A32_FLOAT"/>
 <value value="0x83" name="RB5_R32G32B32A32_UINT"/>
 <value value="0x84" name="RB5_R32G32B32A32_SINT"/>

 <value value="0xff" name="RB5_NONE"/>
</enum>

<enum name="a5xx_tile_mode">
 <value name="TILE5_LINEAR" value="0"/>
 <value name="TILE5_2" value="2"/>
 <value name="TILE5_3" value="3"/>
</enum>

<enum name="a5xx_vtx_fmt" prefix="chipset">
 <value value="0x03" name="VFMT5_8_UNORM"/>
 <value value="0x04" name="VFMT5_8_SNORM"/>
 <value value="0x05" name="VFMT5_8_UINT"/>
 <value value="0x06" name="VFMT5_8_SINT"/>

 <value value="0x0f" name="VFMT5_8_8_UNORM"/>
 <value value="0x10" name="VFMT5_8_8_SNORM"/>
 <value value="0x11" name="VFMT5_8_8_UINT"/>
 <value value="0x12" name="VFMT5_8_8_SINT"/>

 <value value="0x15" name="VFMT5_16_UNORM"/>
 <value value="0x16" name="VFMT5_16_SNORM"/>
 <value value="0x17" name="VFMT5_16_FLOAT"/>
 <value value="0x18" name="VFMT5_16_UINT"/>
 <value value="0x19" name="VFMT5_16_SINT"/>

 <value value="0x21" name="VFMT5_8_8_8_UNORM"/>
 <value value="0x22" name="VFMT5_8_8_8_SNORM"/>
 <value value="0x23" name="VFMT5_8_8_8_UINT"/>
 <value value="0x24" name="VFMT5_8_8_8_SINT"/>

 <value value="0x30" name="VFMT5_8_8_8_8_UNORM"/>
 <value value="0x32" name="VFMT5_8_8_8_8_SNORM"/>
 <value value="0x33" name="VFMT5_8_8_8_8_UINT"/>
 <value value="0x34" name="VFMT5_8_8_8_8_SINT"/>

 <value value="0x36" name="VFMT5_10_10_10_2_UNORM"/>
 <value value="0x39" name="VFMT5_10_10_10_2_SNORM"/>
 <value value="0x3a" name="VFMT5_10_10_10_2_UINT"/>
 <value value="0x3b" name="VFMT5_10_10_10_2_SINT"/>

 <value value="0x42" name="VFMT5_11_11_10_FLOAT"/>

 <value value="0x43" name="VFMT5_16_16_UNORM"/>
 <value value="0x44" name="VFMT5_16_16_SNORM"/>
 <value value="0x45" name="VFMT5_16_16_FLOAT"/>
 <value value="0x46" name="VFMT5_16_16_UINT"/>
 <value value="0x47" name="VFMT5_16_16_SINT"/>

 <value value="0x48" name="VFMT5_32_UNORM"/>
 <value value="0x49" name="VFMT5_32_SNORM"/>
 <value value="0x4a" name="VFMT5_32_FLOAT"/>
 <value value="0x4b" name="VFMT5_32_UINT"/>
 <value value="0x4c" name="VFMT5_32_SINT"/>
 <value value="0x4d" name="VFMT5_32_FIXED"/>

 <value value="0x58" name="VFMT5_16_16_16_UNORM"/>
 <value value="0x59" name="VFMT5_16_16_16_SNORM"/>
 <value value="0x5a" name="VFMT5_16_16_16_FLOAT"/>
 <value value="0x5b" name="VFMT5_16_16_16_UINT"/>
 <value value="0x5c" name="VFMT5_16_16_16_SINT"/>

 <value value="0x60" name="VFMT5_16_16_16_16_UNORM"/>
 <value value="0x61" name="VFMT5_16_16_16_16_SNORM"/>
 <value value="0x62" name="VFMT5_16_16_16_16_FLOAT"/>
 <value value="0x63" name="VFMT5_16_16_16_16_UINT"/>
 <value value="0x64" name="VFMT5_16_16_16_16_SINT"/>

 <value value="0x65" name="VFMT5_32_32_UNORM"/>
 <value value="0x66" name="VFMT5_32_32_SNORM"/>
 <value value="0x67" name="VFMT5_32_32_FLOAT"/>
 <value value="0x68" name="VFMT5_32_32_UINT"/>
 <value value="0x69" name="VFMT5_32_32_SINT"/>
 <value value="0x6a" name="VFMT5_32_32_FIXED"/>

 <value value="0x70" name="VFMT5_32_32_32_UNORM"/>
 <value value="0x71" name="VFMT5_32_32_32_SNORM"/>
 <value value="0x72" name="VFMT5_32_32_32_UINT"/>
 <value value="0x73" name="VFMT5_32_32_32_SINT"/>
 <value value="0x74" name="VFMT5_32_32_32_FLOAT"/>
 <value value="0x75" name="VFMT5_32_32_32_FIXED"/>

 <value value="0x80" name="VFMT5_32_32_32_32_UNORM"/>
 <value value="0x81" name="VFMT5_32_32_32_32_SNORM"/>
 <value value="0x82" name="VFMT5_32_32_32_32_FLOAT"/>
 <value value="0x83" name="VFMT5_32_32_32_32_UINT"/>
 <value value="0x84" name="VFMT5_32_32_32_32_SINT"/>
 <value value="0x85" name="VFMT5_32_32_32_32_FIXED"/>

 <value value="0xff" name="VFMT5_NONE"/>
</enum>

<enum name="a5xx_tex_fmt">
 <value value="0x02" name="TFMT5_A8_UNORM"/>
 <value value="0x03" name="TFMT5_8_UNORM"/>
 <value value="0x04" name="TFMT5_8_SNORM"/>
 <value value="0x05" name="TFMT5_8_UINT"/>
 <value value="0x06" name="TFMT5_8_SINT"/>
 <value value="0x08" name="TFMT5_4_4_4_4_UNORM"/>
 <value value="0x0a" name="TFMT5_5_5_5_1_UNORM"/>
 <value value="0x0e" name="TFMT5_5_6_5_UNORM"/>
 <value value="0x0f" name="TFMT5_8_8_UNORM"/>
 <value value="0x10" name="TFMT5_8_8_SNORM"/>
 <value value="0x11" name="TFMT5_8_8_UINT"/>
 <value value="0x12" name="TFMT5_8_8_SINT"/>
 <value value="0x13" name="TFMT5_L8_A8_UNORM"/>
 <value value="0x15" name="TFMT5_16_UNORM"/>
 <value value="0x16" name="TFMT5_16_SNORM"/>
 <value value="0x17" name="TFMT5_16_FLOAT"/>
 <value value="0x18" name="TFMT5_16_UINT"/>
 <value value="0x19" name="TFMT5_16_SINT"/>
 <value value="0x30" name="TFMT5_8_8_8_8_UNORM"/>
 <value value="0x31" name="TFMT5_8_8_8_UNORM"/>
 <value value="0x32" name="TFMT5_8_8_8_8_SNORM"/>
 <value value="0x33" name="TFMT5_8_8_8_8_UINT"/>
 <value value="0x34" name="TFMT5_8_8_8_8_SINT"/>
 <value value="0x35" name="TFMT5_9_9_9_E5_FLOAT"/>
 <value value="0x36" name="TFMT5_10_10_10_2_UNORM"/>
 <value value="0x3a" name="TFMT5_10_10_10_2_UINT"/>
 <value value="0x42" name="TFMT5_11_11_10_FLOAT"/>
 <value value="0x43" name="TFMT5_16_16_UNORM"/>
 <value value="0x44" name="TFMT5_16_16_SNORM"/>
 <value value="0x45" name="TFMT5_16_16_FLOAT"/>
 <value value="0x46" name="TFMT5_16_16_UINT"/>
 <value value="0x47" name="TFMT5_16_16_SINT"/>
 <value value="0x4a" name="TFMT5_32_FLOAT"/>
 <value value="0x4b" name="TFMT5_32_UINT"/>
 <value value="0x4c" name="TFMT5_32_SINT"/>
 <value value="0x60" name="TFMT5_16_16_16_16_UNORM"/>
 <value value="0x61" name="TFMT5_16_16_16_16_SNORM"/>
 <value value="0x62" name="TFMT5_16_16_16_16_FLOAT"/>
 <value value="0x63" name="TFMT5_16_16_16_16_UINT"/>
 <value value="0x64" name="TFMT5_16_16_16_16_SINT"/>
 <value value="0x67" name="TFMT5_32_32_FLOAT"/>
 <value value="0x68" name="TFMT5_32_32_UINT"/>
 <value value="0x69" name="TFMT5_32_32_SINT"/>
 <value value="0x72" name="TFMT5_32_32_32_UINT"/>
 <value value="0x73" name="TFMT5_32_32_32_SINT"/>
 <value value="0x74" name="TFMT5_32_32_32_FLOAT"/>
 <value value="0x82" name="TFMT5_32_32_32_32_FLOAT"/>
 <value value="0x83" name="TFMT5_32_32_32_32_UINT"/>
 <value value="0x84" name="TFMT5_32_32_32_32_SINT"/>
 <value value="0xa0" name="TFMT5_X8Z24_UNORM"/>

 <value value="0xab" name="TFMT5_ETC2_RG11_UNORM"/>
 <value value="0xac" name="TFMT5_ETC2_RG11_SNORM"/>
 <value value="0xad" name="TFMT5_ETC2_R11_UNORM"/>
 <value value="0xae" name="TFMT5_ETC2_R11_SNORM"/>
 <value value="0xaf" name="TFMT5_ETC1"/>
 <value value="0xb0" name="TFMT5_ETC2_RGB8"/>
 <value value="0xb1" name="TFMT5_ETC2_RGBA8"/>
 <value value="0xb2" name="TFMT5_ETC2_RGB8A1"/>
 <value value="0xb3" name="TFMT5_DXT1"/>
 <value value="0xb4" name="TFMT5_DXT3"/>
 <value value="0xb5" name="TFMT5_DXT5"/>
 <value value="0xb7" name="TFMT5_RGTC1_UNORM"/>
 <value value="0xb8" name="TFMT5_RGTC1_SNORM"/>
 <value value="0xbb" name="TFMT5_RGTC2_UNORM"/>
 <value value="0xbc" name="TFMT5_RGTC2_SNORM"/>
 <value value="0xbe" name="TFMT5_BPTC_UFLOAT"/>
 <value value="0xbf" name="TFMT5_BPTC_FLOAT"/>
 <value value="0xc0" name="TFMT5_BPTC"/>
 <value value="0xc1" name="TFMT5_ASTC_4x4"/>
 <value value="0xc2" name="TFMT5_ASTC_5x4"/>
 <value value="0xc3" name="TFMT5_ASTC_5x5"/>
 <value value="0xc4" name="TFMT5_ASTC_6x5"/>
 <value value="0xc5" name="TFMT5_ASTC_6x6"/>
 <value value="0xc6" name="TFMT5_ASTC_8x5"/>
 <value value="0xc7" name="TFMT5_ASTC_8x6"/>
 <value value="0xc8" name="TFMT5_ASTC_8x8"/>
 <value value="0xc9" name="TFMT5_ASTC_10x5"/>
 <value value="0xca" name="TFMT5_ASTC_10x6"/>
 <value value="0xcb" name="TFMT5_ASTC_10x8"/>
 <value value="0xcc" name="TFMT5_ASTC_10x10"/>
 <value value="0xcd" name="TFMT5_ASTC_12x10"/>
 <value value="0xce" name="TFMT5_ASTC_12x12"/>

 <value value="0xff" name="TFMT5_NONE"/>
</enum>

<enum name="a5xx_depth_format">
 <value name="DEPTH5_NONE" value="0"/>
 <value name="DEPTH5_16" value="1"/>
 <value name="DEPTH5_24_8" value="2"/>
 <value name="DEPTH5_32" value="4"/>
</enum>

<enum name="a5xx_blit_buf">
 <value value="0" name="BLIT_MRT0"/>
 <value value="1" name="BLIT_MRT1"/>
 <value value="2" name="BLIT_MRT2"/>
 <value value="3" name="BLIT_MRT3"/>
 <value value="4" name="BLIT_MRT4"/>
 <value value="5" name="BLIT_MRT5"/>
 <value value="6" name="BLIT_MRT6"/>
 <value value="7" name="BLIT_MRT7"/>
 <value value="8" name="BLIT_ZS"/>       <!-- depth or combined depth+stencil -->
 <value value="9" name="BLIT_S"/>        <!-- separate stencil -->
</enum>

<!-- see comment in a4xx.xml about script to extract countables from test-perf output -->
<enum name="a5xx_cp_perfcounter_select">
 <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 <value value="3" name="PERF_CP_PFP_IDLE"/>
 <value value="4" name="PERF_CP_PFP_BUSY_WORKING"/>
 <value value="5" name="PERF_CP_PFP_STALL_CYCLES_ANY"/>
 <value value="6" name="PERF_CP_PFP_STARVE_CYCLES_ANY"/>
 <value value="7" name="PERF_CP_PFP_ICACHE_MISS"/>
 <value value="8" name="PERF_CP_PFP_ICACHE_HIT"/>
 <value value="9" name="PERF_CP_PFP_MATCH_PM4_PKT_PROFILE"/>
 <value value="10" name="PERF_CP_ME_BUSY_WORKING"/>
 <value value="11" name="PERF_CP_ME_IDLE"/>
 <value value="12" name="PERF_CP_ME_STARVE_CYCLES_ANY"/>
 <value value="13" name="PERF_CP_ME_FIFO_EMPTY_PFP_IDLE"/>
 <value value="14" name="PERF_CP_ME_FIFO_EMPTY_PFP_BUSY"/>
 <value value="15" name="PERF_CP_ME_FIFO_FULL_ME_BUSY"/>
 <value value="16" name="PERF_CP_ME_FIFO_FULL_ME_NON_WORKING"/>
 <value value="17" name="PERF_CP_ME_STALL_CYCLES_ANY"/>
 <value value="18" name="PERF_CP_ME_ICACHE_MISS"/>
 <value value="19" name="PERF_CP_ME_ICACHE_HIT"/>
 <value value="20" name="PERF_CP_NUM_PREEMPTIONS"/>
 <value value="21" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 <value value="22" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 <value value="23" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 <value value="24" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 <value value="25" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 <value value="26" name="PERF_CP_MODE_SWITCH"/>
 <value value="27" name="PERF_CP_ZPASS_DONE"/>
 <value value="28" name="PERF_CP_CONTEXT_DONE"/>
 <value value="29" name="PERF_CP_CACHE_FLUSH"/>
 <value value="30" name="PERF_CP_LONG_PREEMPTIONS"/>
</enum>

<enum name="a5xx_rbbm_perfcounter_select">
 <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 <value value="7" name="PERF_RBBM_COM_BUSY"/>
 <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
</enum>

<enum name="a5xx_pc_perfcounter_select">
 <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 <value value="16" name="PERF_PC_INSTANCES"/>
 <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 <value value="18" name="PERF_PC_DEAD_PRIM"/>
 <value value="19" name="PERF_PC_LIVE_PRIM"/>
 <value value="20" name="PERF_PC_VERTEX_HITS"/>
 <value value="21" name="PERF_PC_IA_VERTICES"/>
 <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
</enum>

<enum name="a5xx_vfd_perfcounter_select">
 <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 <value value="3" name="PERF_VFD_STALL_CYCLES_MISS_VB"/>
 <value value="4" name="PERF_VFD_STALL_CYCLES_MISS_Q"/>
 <value value="5" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 <value value="6" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 <value value="7" name="PERF_VFD_STALL_CYCLES_VFDP_VB"/>
 <value value="8" name="PERF_VFD_STALL_CYCLES_VFDP_Q"/>
 <value value="9" name="PERF_VFD_DECODER_PACKER_STALL"/>
 <value value="10" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 <value value="11" name="PERF_VFD_RBUFFER_FULL"/>
 <value value="12" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 <value value="13" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 <value value="14" name="PERF_VFD_NUM_ATTRIBUTES"/>
 <value value="15" name="PERF_VFD_INSTRUCTIONS"/>
 <value value="16" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 <value value="17" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 <value value="18" name="PERF_VFD_MODE_0_FIBERS"/>
 <value value="19" name="PERF_VFD_MODE_1_FIBERS"/>
 <value value="20" name="PERF_VFD_MODE_2_FIBERS"/>
 <value value="21" name="PERF_VFD_MODE_3_FIBERS"/>
 <value value="22" name="PERF_VFD_MODE_4_FIBERS"/>
 <value value="23" name="PERF_VFD_TOTAL_VERTICES"/>
 <value value="24" name="PERF_VFD_NUM_ATTR_MISS"/>
 <value value="25" name="PERF_VFD_1_BURST_REQ"/>
 <value value="26" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 <value value="27" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 <value value="28" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 <value value="29" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 <value value="30" name="PERF_VFDP_VS_STAGE_32_WAVES"/>
</enum>

<enum name="a5xx_hlsq_perfcounter_select">
 <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 <value value="6" name="PERF_HLSQ_FS_STAGE_32_WAVES"/>
 <value value="7" name="PERF_HLSQ_FS_STAGE_64_WAVES"/>
 <value value="8" name="PERF_HLSQ_QUADS"/>
 <value value="9" name="PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE"/>
 <value value="10" name="PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE"/>
 <value value="11" name="PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE"/>
 <value value="12" name="PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE"/>
 <value value="13" name="PERF_HLSQ_CS_INVOCATIONS"/>
 <value value="14" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
</enum>

<enum name="a5xx_vpc_perfcounter_select">
 <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 <value value="7" name="PERF_VPC_POS_EXPORT_STALL_CYCLES"/>
 <value value="8" name="PERF_VPC_STARVE_CYCLES_SP"/>
 <value value="9" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 <value value="10" name="PERF_VPC_PC_PRIMITIVES"/>
 <value value="11" name="PERF_VPC_SP_COMPONENTS"/>
 <value value="12" name="PERF_VPC_SP_LM_PRIMITIVES"/>
 <value value="13" name="PERF_VPC_SP_LM_COMPONENTS"/>
 <value value="14" name="PERF_VPC_SP_LM_DWORDS"/>
 <value value="15" name="PERF_VPC_STREAMOUT_COMPONENTS"/>
 <value value="16" name="PERF_VPC_GRANT_PHASES"/>
</enum>

<enum name="a5xx_tse_perfcounter_select">
 <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 <value value="15" name="PERF_TSE_CINVOCATION"/>
 <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 <value value="18" name="PERF_TSE_2D_ALIVE_CLCLES"/>
</enum>

<enum name="a5xx_ras_perfcounter_select">
 <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 <value value="4" name="PERF_RAS_SUPER_TILES"/>
 <value value="5" name="PERF_RAS_8X4_TILES"/>
 <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
</enum>

<enum name="a5xx_lrz_perfcounter_select">
 <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 <value value="7" name="PERF_LRZ_LRZ_READ"/>
 <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
</enum>

<enum name="a5xx_uche_perfcounter_select">
 <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 <value value="1" name="PERF_UCHE_STALL_CYCLES_VBIF"/>
 <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 <value value="18" name="PERF_UCHE_EVICTS"/>
 <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 <value value="30" name="PERF_UCHE_FLAG_COUNT"/>
</enum>

<enum name="a5xx_tp_perfcounter_select">
 <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 <value value="18" name="PERF_TP_QUADS_1D"/>
 <value value="19" name="PERF_TP_QUADS_2D"/>
 <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 <value value="21" name="PERF_TP_QUADS_3D"/>
 <value value="22" name="PERF_TP_QUADS_CUBE"/>
 <value value="23" name="PERF_TP_STATE_CACHE_REQUESTS"/>
 <value value="24" name="PERF_TP_STATE_CACHE_MISSES"/>
 <value value="25" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 <value value="26" name="PERF_TP_BINDLESS_STATE_CACHE_REQUESTS"/>
 <value value="27" name="PERF_TP_BINDLESS_STATE_CACHE_MISSES"/>
 <value value="28" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 <value value="29" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 <value value="30" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 <value value="31" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 <value value="32" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 <value value="33" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 <value value="34" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 <value value="35" name="PERF_TP_FLAG_CACHE_MISSES"/>
 <value value="36" name="PERF_TP_L1_5_L2_REQUESTS"/>
 <value value="37" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 <value value="38" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 <value value="39" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 <value value="40" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 <value value="41" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
</enum>

<enum name="a5xx_sp_perfcounter_select">
 <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 <value value="7" name="PERF_SP_SCHEDULER_NON_WORKING"/>
 <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 <value value="29" name="PERF_SP_LM_ATOMICS"/>
 <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 <value value="32" name="PERF_SP_GM_ATOMICS"/>
 <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 <value value="34" name="PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
 <value value="35" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 <value value="36" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 <value value="37" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 <value value="38" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 <value value="39" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 <value value="40" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 <value value="41" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 <value value="42" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 <value value="43" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 <value value="44" name="PERF_SP_VS_INSTRUCTIONS"/>
 <value value="45" name="PERF_SP_FS_INSTRUCTIONS"/>
 <value value="46" name="PERF_SP_ADDR_LOCK_COUNT"/>
 <value value="47" name="PERF_SP_UCHE_READ_TRANS"/>
 <value value="48" name="PERF_SP_UCHE_WRITE_TRANS"/>
 <value value="49" name="PERF_SP_EXPORT_VPC_TRANS"/>
 <value value="50" name="PERF_SP_EXPORT_RB_TRANS"/>
 <value value="51" name="PERF_SP_PIXELS_KILLED"/>
 <value value="52" name="PERF_SP_ICL1_REQUESTS"/>
 <value value="53" name="PERF_SP_ICL1_MISSES"/>
 <value value="54" name="PERF_SP_ICL0_REQUESTS"/>
 <value value="55" name="PERF_SP_ICL0_MISSES"/>
 <value value="56" name="PERF_SP_HS_INSTRUCTIONS"/>
 <value value="57" name="PERF_SP_DS_INSTRUCTIONS"/>
 <value value="58" name="PERF_SP_GS_INSTRUCTIONS"/>
 <value value="59" name="PERF_SP_CS_INSTRUCTIONS"/>
 <value value="60" name="PERF_SP_GPR_READ"/>
 <value value="61" name="PERF_SP_GPR_WRITE"/>
 <value value="62" name="PERF_SP_LM_CH0_REQUESTS"/>
 <value value="63" name="PERF_SP_LM_CH1_REQUESTS"/>
 <value value="64" name="PERF_SP_LM_BANK_CONFLICTS"/>
</enum>

<enum name="a5xx_rb_perfcounter_select">
 <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 <value value="1" name="PERF_RB_STALL_CYCLES_CCU"/>
 <value value="2" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 <value value="3" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 <value value="4" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 <value value="5" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 <value value="6" name="PERF_RB_STARVE_CYCLES_SP"/>
 <value value="7" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 <value value="8" name="PERF_RB_STARVE_CYCLES_CCU"/>
 <value value="9" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 <value value="10" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 <value value="11" name="PERF_RB_Z_WORKLOAD"/>
 <value value="12" name="PERF_RB_HLSQ_ACTIVE"/>
 <value value="13" name="PERF_RB_Z_READ"/>
 <value value="14" name="PERF_RB_Z_WRITE"/>
 <value value="15" name="PERF_RB_C_READ"/>
 <value value="16" name="PERF_RB_C_WRITE"/>
 <value value="17" name="PERF_RB_TOTAL_PASS"/>
 <value value="18" name="PERF_RB_Z_PASS"/>
 <value value="19" name="PERF_RB_Z_FAIL"/>
 <value value="20" name="PERF_RB_S_FAIL"/>
 <value value="21" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 <value value="22" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 <value value="23" name="RB_RESERVED"/>
 <value value="24" name="PERF_RB_2D_ALIVE_CYCLES"/>
 <value value="25" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 <value value="27" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 <value value="28" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 <value value="29" name="PERF_RB_2D_VALID_PIXELS"/>
</enum>

<enum name="a5xx_rb_samples_perfcounter_select">
 <value value="0" name="TOTAL_SAMPLES"/>
 <value value="1" name="ZPASS_SAMPLES"/>
 <value value="2" name="ZFAIL_SAMPLES"/>
 <value value="3" name="SFAIL_SAMPLES"/>
</enum>

<enum name="a5xx_vsc_perfcounter_select">
 <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 <value value="3" name="PERF_VSC_EOT_NUM"/>
</enum>

<enum name="a5xx_ccu_perfcounter_select">
 <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 <value value="9" name="PERF_CCU_GMEM_READ"/>
 <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 <value value="16" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 <value value="17" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 <value value="18" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 <value value="19" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 <value value="20" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 <value value="21" name="PERF_CCU_2D_BUSY_CYCLES"/>
 <value value="22" name="PERF_CCU_2D_RD_REQ"/>
 <value value="23" name="PERF_CCU_2D_WR_REQ"/>
 <value value="24" name="PERF_CCU_2D_REORDER_STARVE_CYCLES"/>
 <value value="25" name="PERF_CCU_2D_PIXELS"/>
</enum>

<enum name="a5xx_cmp_perfcounter_select">
 <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_VBIF"/>
 <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 <value value="15" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 <value value="16" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 <value value="17" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 <value value="19" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 <value value="20" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 <value value="21" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 <value value="22" name="PERF_CMPDECMP_2D_RD_DATA"/>
 <value value="23" name="PERF_CMPDECMP_2D_WR_DATA"/>
</enum>

<enum name="a5xx_vbif_perfcounter_select">
 <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
 <value value="1" name="AXI_READ_REQUESTS_ID_1"/>
 <value value="2" name="AXI_READ_REQUESTS_ID_2"/>
 <value value="3" name="AXI_READ_REQUESTS_ID_3"/>
 <value value="4" name="AXI_READ_REQUESTS_ID_4"/>
 <value value="5" name="AXI_READ_REQUESTS_ID_5"/>
 <value value="6" name="AXI_READ_REQUESTS_ID_6"/>
 <value value="7" name="AXI_READ_REQUESTS_ID_7"/>
 <value value="8" name="AXI_READ_REQUESTS_ID_8"/>
 <value value="9" name="AXI_READ_REQUESTS_ID_9"/>
 <value value="10" name="AXI_READ_REQUESTS_ID_10"/>
 <value value="11" name="AXI_READ_REQUESTS_ID_11"/>
 <value value="12" name="AXI_READ_REQUESTS_ID_12"/>
 <value value="13" name="AXI_READ_REQUESTS_ID_13"/>
 <value value="14" name="AXI_READ_REQUESTS_ID_14"/>
 <value value="15" name="AXI_READ_REQUESTS_ID_15"/>
 <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
 <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
 <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
 <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
 <value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
 <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
 <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
 <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
 <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
 <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
 <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
 <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
 <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
 <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
 <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
 <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
 <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
 <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
 <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
 <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
 <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
 <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
 <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
 <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
 <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
 <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
 <value value="42" name="AXI_TOTAL_REQUESTS"/>
 <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
 <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
 <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
 <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
 <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
 <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
 <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
 <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
 <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
 <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
 <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
 <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
 <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
 <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
 <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
 <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
 <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
 <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
 <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
 <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
 <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
 <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
 <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
 <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
 <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
 <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
 <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
 <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
 <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
 <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
 <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
 <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
 <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
 <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
 <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
 <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
 <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
 <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
 <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
 <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
 <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
 <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
 <value value="85" name="AXI_DATA_BEATS_TOTAL"/>
</enum>

<domain name="A5XX" width="32">
 <bitset name="A5XX_INT0">
  <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
  <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
  <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2" type="boolean"/>
  <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
  <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
  <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5" type="boolean"/>
  <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6" type="boolean"/>
  <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
  <bitfield name="CP_SW" pos="8" type="boolean"/>
  <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
  <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
  <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
  <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
  <bitfield name="CP_IB2" pos="13" type="boolean"/>
  <bitfield name="CP_IB1" pos="14" type="boolean"/>
  <bitfield name="CP_RB" pos="15" type="boolean"/>
  <bitfield name="CP_UNUSED_1" pos="16" type="boolean"/>
  <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
  <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
  <bitfield name="UNKNOWN_1" pos="19" type="boolean"/>
  <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
  <bitfield name="UNUSED_2" pos="21" type="boolean"/>
  <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
  <bitfield name="MISC_HANG_DETECT" pos="23" type="boolean"/>
  <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
  <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
  <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
  <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
  <bitfield name="GPMU_VOLTAGE_DROOP" pos="28" type="boolean"/>
  <bitfield name="GPMU_FIRMWARE" pos="29" type="boolean"/>
  <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
  <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
 </bitset>

 <!-- CP Interrupt bits -->
 <bitset name="A5XX_CP_INT">
  <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
  <bitfield name="CP_RESERVED_BIT_ERROR" pos="1" type="boolean"/>
  <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
  <bitfield name="CP_DMA_ERROR" pos="3" type="boolean"/>
  <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
  <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
 </bitset>

 <!-- CP registers -->
 <reg32 offset="0x0800" name="CP_RB_BASE"/>
 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
 <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
 <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
 <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
 <reg32 offset="0x080c" name="CP_DRAW_STATE_DATA"/>
 <reg32 offset="0x080d" name="CP_ME_NRT_ADDR_LO"/>
 <reg32 offset="0x080e" name="CP_ME_NRT_ADDR_HI"/>
 <reg32 offset="0x0810" name="CP_ME_NRT_DATA"/>
 <reg32 offset="0x0817" name="CP_CRASH_SCRIPT_BASE_LO"/>
 <reg32 offset="0x0818" name="CP_CRASH_SCRIPT_BASE_HI"/>
 <reg32 offset="0x0819" name="CP_CRASH_DUMP_CNTL"/>
 <reg32 offset="0x081a" name="CP_ME_STAT_ADDR"/>
 <reg32 offset="0x081f" name="CP_ROQ_THRESHOLDS_1"/>
 <reg32 offset="0x0820" name="CP_ROQ_THRESHOLDS_2"/>
 <reg32 offset="0x0821" name="CP_ROQ_DBG_ADDR"/>
 <reg32 offset="0x0822" name="CP_ROQ_DBG_DATA"/>
 <reg32 offset="0x0823" name="CP_MEQ_DBG_ADDR"/>
 <reg32 offset="0x0824" name="CP_MEQ_DBG_DATA"/>
 <reg32 offset="0x0825" name="CP_MEQ_THRESHOLDS"/>
 <reg32 offset="0x0826" name="CP_MERCIU_SIZE"/>
 <reg32 offset="0x0827" name="CP_MERCIU_DBG_ADDR"/>
 <reg32 offset="0x0828" name="CP_MERCIU_DBG_DATA_1"/>
 <reg32 offset="0x0829" name="CP_MERCIU_DBG_DATA_2"/>
 <reg32 offset="0x082a" name="CP_PFP_UCODE_DBG_ADDR"/>
 <reg32 offset="0x082b" name="CP_PFP_UCODE_DBG_DATA"/>
 <reg32 offset="0x082f" name="CP_ME_UCODE_DBG_ADDR"/>
 <reg32 offset="0x0830" name="CP_ME_UCODE_DBG_DATA"/>
 <reg32 offset="0x0831" name="CP_CNTL"/>
 <reg32 offset="0x0832" name="CP_PFP_ME_CNTL"/>
 <reg32 offset="0x0833" name="CP_CHICKEN_DBG"/>
 <reg32 offset="0x0835" name="CP_PFP_INSTR_BASE_LO"/>
 <reg32 offset="0x0836" name="CP_PFP_INSTR_BASE_HI"/>
 <reg32 offset="0x0838" name="CP_ME_INSTR_BASE_LO"/>
 <reg32 offset="0x0839" name="CP_ME_INSTR_BASE_HI"/>
 <reg32 offset="0x083b" name="CP_CONTEXT_SWITCH_CNTL"/>
 <reg32 offset="0x083c" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_LO"/>
 <reg32 offset="0x083d" name="CP_CONTEXT_SWITCH_RESTORE_ADDR_HI"/>
 <reg32 offset="0x083e" name="CP_CONTEXT_SWITCH_SAVE_ADDR_LO"/>
 <reg32 offset="0x083f" name="CP_CONTEXT_SWITCH_SAVE_ADDR_HI"/>
 <reg32 offset="0x0840" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
 <reg32 offset="0x0841" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
 <reg32 offset="0x0860" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 <reg32 offset="0x0b14" name="CP_ME_STAT_DATA"/>
 <reg32 offset="0x0b15" name="CP_WFI_PEND_CTR"/>
 <reg32 offset="0x0b18" name="CP_INTERRUPT_STATUS"/>
 <reg32 offset="0x0b1a" name="CP_HW_FAULT"/>
 <reg32 offset="0x0b1c" name="CP_PROTECT_STATUS"/>
 <reg32 offset="0x0b1f" name="CP_IB1_BASE"/>
 <reg32 offset="0x0b20" name="CP_IB1_BASE_HI"/>
 <reg32 offset="0x0b21" name="CP_IB1_BUFSZ"/>
 <reg32 offset="0x0b22" name="CP_IB2_BASE"/>
 <reg32 offset="0x0b23" name="CP_IB2_BASE_HI"/>
 <reg32 offset="0x0b24" name="CP_IB2_BUFSZ"/>
 <array offset="0x0b78" name="CP_SCRATCH" stride="1" length="8">
  <reg32 offset="0x0" name="REG" type="uint"/>
 </array>
 <array offset="0x0880" name="CP_PROTECT" stride="1" length="32">
  <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
 </array>
 <reg32 offset="0x08a0" name="CP_PROTECT_CNTL"/>
 <reg32 offset="0x0b1b" name="CP_AHB_FAULT"/>
 <reg32 offset="0x0bb0" name="CP_PERFCTR_CP_SEL_0" type="a5xx_cp_perfcounter_select"/>
 <reg32 offset="0x0bb1" name="CP_PERFCTR_CP_SEL_1" type="a5xx_cp_perfcounter_select"/>
 <reg32 offset="0x0bb2" name="CP_PERFCTR_CP_SEL_2" type="a5xx_cp_perfcounter_select"/>
 <reg32 offset="0x0bb3" name="CP_PERFCTR_CP_SEL_3" type="a5xx_cp_perfcounter_select"/>
 <reg32 offset="0x0bb4" name="CP_PERFCTR_CP_SEL_4" type="a5xx_cp_perfcounter_select"/>
 <reg32 offset="0x0bb5" name="CP_PERFCTR_CP_SEL_5" type="a5xx_cp_perfcounter_select"/>
 <reg32 offset="0x0bb6" name="CP_PERFCTR_CP_SEL_6" type="a5xx_cp_perfcounter_select"/>
 <reg32 offset="0x0bb7" name="CP_PERFCTR_CP_SEL_7" type="a5xx_cp_perfcounter_select"/>
 <reg32 offset="0x0bc1" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
 <reg32 offset="0x0bba" name="CP_POWERCTR_CP_SEL_0"/>
 <reg32 offset="0x0bbb" name="CP_POWERCTR_CP_SEL_1"/>
 <reg32 offset="0x0bbc" name="CP_POWERCTR_CP_SEL_2"/>
 <reg32 offset="0x0bbd" name="CP_POWERCTR_CP_SEL_3"/>

 <!-- RBBM registers -->
 <reg32 offset="0x0004" name="RBBM_CFG_DBGBUS_SEL_A"/>
 <reg32 offset="0x0005" name="RBBM_CFG_DBGBUS_SEL_B"/>
 <reg32 offset="0x0006" name="RBBM_CFG_DBGBUS_SEL_C"/>
 <reg32 offset="0x0007" name="RBBM_CFG_DBGBUS_SEL_D"/>
<!--
#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_INDEX_SHIFT    0x0
#define A5XX_RBBM_CFG_DBGBUS_SEL_PING_BLK_SEL_SHIFT  0x8
#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_INDEX_SHIFT    0x10
#define A5XX_RBBM_CFG_DBGBUS_SEL_PONG_BLK_SEL_SHIFT  0x18
 -->
 <reg32 offset="0x0008" name="RBBM_CFG_DBGBUS_CNTLT"/>
 <reg32 offset="0x0009" name="RBBM_CFG_DBGBUS_CNTLM"/>
 <reg32 offset="0x0018" name="RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT"/>
 <reg32 offset="0x000a" name="RBBM_CFG_DBGBUS_OPL"/>
 <reg32 offset="0x000b" name="RBBM_CFG_DBGBUS_OPE"/>
 <reg32 offset="0x000c" name="RBBM_CFG_DBGBUS_IVTL_0"/>
 <reg32 offset="0x000d" name="RBBM_CFG_DBGBUS_IVTL_1"/>
 <reg32 offset="0x000e" name="RBBM_CFG_DBGBUS_IVTL_2"/>
 <reg32 offset="0x000f" name="RBBM_CFG_DBGBUS_IVTL_3"/>
 <reg32 offset="0x0010" name="RBBM_CFG_DBGBUS_MASKL_0"/>
 <reg32 offset="0x0011" name="RBBM_CFG_DBGBUS_MASKL_1"/>
 <reg32 offset="0x0012" name="RBBM_CFG_DBGBUS_MASKL_2"/>
 <reg32 offset="0x0013" name="RBBM_CFG_DBGBUS_MASKL_3"/>
 <reg32 offset="0x0014" name="RBBM_CFG_DBGBUS_BYTEL_0"/>
 <reg32 offset="0x0015" name="RBBM_CFG_DBGBUS_BYTEL_1"/>
 <reg32 offset="0x0016" name="RBBM_CFG_DBGBUS_IVTE_0"/>
 <reg32 offset="0x0017" name="RBBM_CFG_DBGBUS_IVTE_1"/>
 <reg32 offset="0x0018" name="RBBM_CFG_DBGBUS_IVTE_2"/>
 <reg32 offset="0x0019" name="RBBM_CFG_DBGBUS_IVTE_3"/>
 <reg32 offset="0x001a" name="RBBM_CFG_DBGBUS_MASKE_0"/>
 <reg32 offset="0x001b" name="RBBM_CFG_DBGBUS_MASKE_1"/>
 <reg32 offset="0x001c" name="RBBM_CFG_DBGBUS_MASKE_2"/>
 <reg32 offset="0x001d" name="RBBM_CFG_DBGBUS_MASKE_3"/>
 <reg32 offset="0x001e" name="RBBM_CFG_DBGBUS_NIBBLEE"/>
 <reg32 offset="0x001f" name="RBBM_CFG_DBGBUS_PTRC0"/>
 <reg32 offset="0x0020" name="RBBM_CFG_DBGBUS_PTRC1"/>
 <reg32 offset="0x0021" name="RBBM_CFG_DBGBUS_LOADREG"/>
 <reg32 offset="0x0022" name="RBBM_CFG_DBGBUS_IDX"/>
 <reg32 offset="0x0023" name="RBBM_CFG_DBGBUS_CLRC"/>
 <reg32 offset="0x0024" name="RBBM_CFG_DBGBUS_LOADIVT"/>
 <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
 <reg32 offset="0x0037" name="RBBM_INT_CLEAR_CMD"/>
 <reg32 offset="0x0038" name="RBBM_INT_0_MASK">
  <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
  <bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
  <bitfield name="RBBM_TRANSFER_TIMEOUT" pos="2" type="boolean"/>
  <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
  <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
  <bitfield name="RBBM_ETS_MS_TIMEOUT" pos="5" type="boolean"/>
  <bitfield name="RBBM_ATB_ASYNC_OVERFLOW" pos="6" type="boolean"/>
  <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
  <bitfield name="CP_SW" pos="8" type="boolean"/>
  <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
  <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
  <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
  <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
  <bitfield name="CP_IB2" pos="13" type="boolean"/>
  <bitfield name="CP_IB1" pos="14" type="boolean"/>
  <bitfield name="CP_RB" pos="15" type="boolean"/>
  <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
  <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
  <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
  <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
  <bitfield name="MISC_HANG_DETECT" pos="23" type="boolean"/>
  <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
  <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
  <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
  <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
  <bitfield name="GPMU_VOLTAGE_DROOP" pos="28" type="boolean"/>
  <bitfield name="GPMU_FIRMWARE" pos="29" type="boolean"/>
  <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
  <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
 </reg32>
 <reg32 offset="0x003f" name="RBBM_AHB_DBG_CNTL"/>
 <reg32 offset="0x0041" name="RBBM_EXT_VBIF_DBG_CNTL"/>
 <reg32 offset="0x0043" name="RBBM_SW_RESET_CMD"/>
 <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
 <reg32 offset="0x0046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
 <reg32 offset="0x0048" name="RBBM_DBG_LO_HI_GPIO"/>
 <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CNTL"/>
 <reg32 offset="0x004a" name="RBBM_CLOCK_CNTL_TP0"/>
 <reg32 offset="0x004b" name="RBBM_CLOCK_CNTL_TP1"/>
 <reg32 offset="0x004c" name="RBBM_CLOCK_CNTL_TP2"/>
 <reg32 offset="0x004d" name="RBBM_CLOCK_CNTL_TP3"/>
 <reg32 offset="0x004e" name="RBBM_CLOCK_CNTL2_TP0"/>
 <reg32 offset="0x004f" name="RBBM_CLOCK_CNTL2_TP1"/>
 <reg32 offset="0x0050" name="RBBM_CLOCK_CNTL2_TP2"/>
 <reg32 offset="0x0051" name="RBBM_CLOCK_CNTL2_TP3"/>
 <reg32 offset="0x0052" name="RBBM_CLOCK_CNTL3_TP0"/>
 <reg32 offset="0x0053" name="RBBM_CLOCK_CNTL3_TP1"/>
 <reg32 offset="0x0054" name="RBBM_CLOCK_CNTL3_TP2"/>
 <reg32 offset="0x0055" name="RBBM_CLOCK_CNTL3_TP3"/>
 <reg32 offset="0x0059" name="RBBM_READ_AHB_THROUGH_DBG"/>
 <reg32 offset="0x005a" name="RBBM_CLOCK_CNTL_UCHE"/>
 <reg32 offset="0x005b" name="RBBM_CLOCK_CNTL2_UCHE"/>
 <reg32 offset="0x005c" name="RBBM_CLOCK_CNTL3_UCHE"/>
 <reg32 offset="0x005d" name="RBBM_CLOCK_CNTL4_UCHE"/>
 <reg32 offset="0x005e" name="RBBM_CLOCK_HYST_UCHE"/>
 <reg32 offset="0x005f" name="RBBM_CLOCK_DELAY_UCHE"/>
 <reg32 offset="0x0060" name="RBBM_CLOCK_MODE_GPC"/>
 <reg32 offset="0x0061" name="RBBM_CLOCK_DELAY_GPC"/>
 <reg32 offset="0x0062" name="RBBM_CLOCK_HYST_GPC"/>
 <reg32 offset="0x0063" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
 <reg32 offset="0x0064" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
 <reg32 offset="0x0065" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
 <reg32 offset="0x0066" name="RBBM_CLOCK_DELAY_HLSQ"/>
 <reg32 offset="0x0067" name="RBBM_CLOCK_CNTL"/>
 <reg32 offset="0x0068" name="RBBM_CLOCK_CNTL_SP0"/>
 <reg32 offset="0x0069" name="RBBM_CLOCK_CNTL_SP1"/>
 <reg32 offset="0x006a" name="RBBM_CLOCK_CNTL_SP2"/>
 <reg32 offset="0x006b" name="RBBM_CLOCK_CNTL_SP3"/>
 <reg32 offset="0x006c" name="RBBM_CLOCK_CNTL2_SP0"/>
 <reg32 offset="0x006d" name="RBBM_CLOCK_CNTL2_SP1"/>
 <reg32 offset="0x006e" name="RBBM_CLOCK_CNTL2_SP2"/>
 <reg32 offset="0x006f" name="RBBM_CLOCK_CNTL2_SP3"/>
 <reg32 offset="0x0070" name="RBBM_CLOCK_HYST_SP0"/>
 <reg32 offset="0x0071" name="RBBM_CLOCK_HYST_SP1"/>
 <reg32 offset="0x0072" name="RBBM_CLOCK_HYST_SP2"/>
 <reg32 offset="0x0073" name="RBBM_CLOCK_HYST_SP3"/>
 <reg32 offset="0x0074" name="RBBM_CLOCK_DELAY_SP0"/>
 <reg32 offset="0x0075" name="RBBM_CLOCK_DELAY_SP1"/>
 <reg32 offset="0x0076" name="RBBM_CLOCK_DELAY_SP2"/>
 <reg32 offset="0x0077" name="RBBM_CLOCK_DELAY_SP3"/>
 <reg32 offset="0x0078" name="RBBM_CLOCK_CNTL_RB0"/>
 <reg32 offset="0x0079" name="RBBM_CLOCK_CNTL_RB1"/>
 <reg32 offset="0x007a" name="RBBM_CLOCK_CNTL_RB2"/>
 <reg32 offset="0x007b" name="RBBM_CLOCK_CNTL_RB3"/>
 <reg32 offset="0x007c" name="RBBM_CLOCK_CNTL2_RB0"/>
 <reg32 offset="0x007d" name="RBBM_CLOCK_CNTL2_RB1"/>
 <reg32 offset="0x007e" name="RBBM_CLOCK_CNTL2_RB2"/>
 <reg32 offset="0x007f" name="RBBM_CLOCK_CNTL2_RB3"/>
 <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_RAC"/>
 <reg32 offset="0x0081" name="RBBM_CLOCK_DELAY_RAC"/>
 <reg32 offset="0x0082" name="RBBM_CLOCK_CNTL_CCU0"/>
 <reg32 offset="0x0083" name="RBBM_CLOCK_CNTL_CCU1"/>
 <reg32 offset="0x0084" name="RBBM_CLOCK_CNTL_CCU2"/>
 <reg32 offset="0x0085" name="RBBM_CLOCK_CNTL_CCU3"/>
 <reg32 offset="0x0086" name="RBBM_CLOCK_HYST_RB_CCU0"/>
 <reg32 offset="0x0087" name="RBBM_CLOCK_HYST_RB_CCU1"/>
 <reg32 offset="0x0088" name="RBBM_CLOCK_HYST_RB_CCU2"/>
 <reg32 offset="0x0089" name="RBBM_CLOCK_HYST_RB_CCU3"/>
 <reg32 offset="0x008a" name="RBBM_CLOCK_CNTL_RAC"/>
 <reg32 offset="0x008b" name="RBBM_CLOCK_CNTL2_RAC"/>
 <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_RB_CCU_L1_0"/>
 <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_RB_CCU_L1_1"/>
 <reg32 offset="0x008e" name="RBBM_CLOCK_DELAY_RB_CCU_L1_2"/>
 <reg32 offset="0x008f" name="RBBM_CLOCK_DELAY_RB_CCU_L1_3"/>
 <reg32 offset="0x0090" name="RBBM_CLOCK_HYST_VFD"/>
 <reg32 offset="0x0091" name="RBBM_CLOCK_MODE_VFD"/>
 <reg32 offset="0x0092" name="RBBM_CLOCK_DELAY_VFD"/>
 <reg32 offset="0x0093" name="RBBM_AHB_CNTL0"/>
 <reg32 offset="0x0094" name="RBBM_AHB_CNTL1"/>
 <reg32 offset="0x0095" name="RBBM_AHB_CNTL2"/>
 <reg32 offset="0x0096" name="RBBM_AHB_CMD"/>
 <reg32 offset="0x009c" name="RBBM_INTERFACE_HANG_MASK_CNTL11"/>
 <reg32 offset="0x009d" name="RBBM_INTERFACE_HANG_MASK_CNTL12"/>
 <reg32 offset="0x009e" name="RBBM_INTERFACE_HANG_MASK_CNTL13"/>
 <reg32 offset="0x009f" name="RBBM_INTERFACE_HANG_MASK_CNTL14"/>
 <reg32 offset="0x00a0" name="RBBM_INTERFACE_HANG_MASK_CNTL15"/>
 <reg32 offset="0x00a1" name="RBBM_INTERFACE_HANG_MASK_CNTL16"/>
 <reg32 offset="0x00a2" name="RBBM_INTERFACE_HANG_MASK_CNTL17"/>
 <reg32 offset="0x00a3" name="RBBM_INTERFACE_HANG_MASK_CNTL18"/>
 <reg32 offset="0x00a4" name="RBBM_CLOCK_DELAY_TP0"/>
 <reg32 offset="0x00a5" name="RBBM_CLOCK_DELAY_TP1"/>
 <reg32 offset="0x00a6" name="RBBM_CLOCK_DELAY_TP2"/>
 <reg32 offset="0x00a7" name="RBBM_CLOCK_DELAY_TP3"/>
 <reg32 offset="0x00a8" name="RBBM_CLOCK_DELAY2_TP0"/>
 <reg32 offset="0x00a9" name="RBBM_CLOCK_DELAY2_TP1"/>
 <reg32 offset="0x00aa" name="RBBM_CLOCK_DELAY2_TP2"/>
 <reg32 offset="0x00ab" name="RBBM_CLOCK_DELAY2_TP3"/>
 <reg32 offset="0x00ac" name="RBBM_CLOCK_DELAY3_TP0"/>
 <reg32 offset="0x00ad" name="RBBM_CLOCK_DELAY3_TP1"/>
 <reg32 offset="0x00ae" name="RBBM_CLOCK_DELAY3_TP2"/>
 <reg32 offset="0x00af" name="RBBM_CLOCK_DELAY3_TP3"/>
 <reg32 offset="0x00b0" name="RBBM_CLOCK_HYST_TP0"/>
 <reg32 offset="0x00b1" name="RBBM_CLOCK_HYST_TP1"/>
 <reg32 offset="0x00b2" name="RBBM_CLOCK_HYST_TP2"/>
 <reg32 offset="0x00b3" name="RBBM_CLOCK_HYST_TP3"/>
 <reg32 offset="0x00b4" name="RBBM_CLOCK_HYST2_TP0"/>
 <reg32 offset="0x00b5" name="RBBM_CLOCK_HYST2_TP1"/>
 <reg32 offset="0x00b6" name="RBBM_CLOCK_HYST2_TP2"/>
 <reg32 offset="0x00b7" name="RBBM_CLOCK_HYST2_TP3"/>
 <reg32 offset="0x00b8" name="RBBM_CLOCK_HYST3_TP0"/>
 <reg32 offset="0x00b9" name="RBBM_CLOCK_HYST3_TP1"/>
 <reg32 offset="0x00ba" name="RBBM_CLOCK_HYST3_TP2"/>
 <reg32 offset="0x00bb" name="RBBM_CLOCK_HYST3_TP3"/>
 <reg32 offset="0x00c8" name="RBBM_CLOCK_CNTL_GPMU"/>
 <reg32 offset="0x00c9" name="RBBM_CLOCK_DELAY_GPMU"/>
 <reg32 offset="0x00ca" name="RBBM_CLOCK_HYST_GPMU"/>
 <reg32 offset="0x03a0" name="RBBM_PERFCTR_CP_0_LO"/>
 <reg32 offset="0x03a1" name="RBBM_PERFCTR_CP_0_HI"/>
 <reg32 offset="0x03a2" name="RBBM_PERFCTR_CP_1_LO"/>
 <reg32 offset="0x03a3" name="RBBM_PERFCTR_CP_1_HI"/>
 <reg32 offset="0x03a4" name="RBBM_PERFCTR_CP_2_LO"/>
 <reg32 offset="0x03a5" name="RBBM_PERFCTR_CP_2_HI"/>
 <reg32 offset="0x03a6" name="RBBM_PERFCTR_CP_3_LO"/>
 <reg32 offset="0x03a7" name="RBBM_PERFCTR_CP_3_HI"/>
 <reg32 offset="0x03a8" name="RBBM_PERFCTR_CP_4_LO"/>
 <reg32 offset="0x03a9" name="RBBM_PERFCTR_CP_4_HI"/>
 <reg32 offset="0x03aa" name="RBBM_PERFCTR_CP_5_LO"/>
 <reg32 offset="0x03ab" name="RBBM_PERFCTR_CP_5_HI"/>
 <reg32 offset="0x03ac" name="RBBM_PERFCTR_CP_6_LO"/>
 <reg32 offset="0x03ad" name="RBBM_PERFCTR_CP_6_HI"/>
 <reg32 offset="0x03ae" name="RBBM_PERFCTR_CP_7_LO"/>
 <reg32 offset="0x03af" name="RBBM_PERFCTR_CP_7_HI"/>
 <reg32 offset="0x03b0" name="RBBM_PERFCTR_RBBM_0_LO"/>
 <reg32 offset="0x03b1" name="RBBM_PERFCTR_RBBM_0_HI"/>
 <reg32 offset="0x03b2" name="RBBM_PERFCTR_RBBM_1_LO"/>
 <reg32 offset="0x03b3" name="RBBM_PERFCTR_RBBM_1_HI"/>
 <reg32 offset="0x03b4" name="RBBM_PERFCTR_RBBM_2_LO"/>
 <reg32 offset="0x03b5" name="RBBM_PERFCTR_RBBM_2_HI"/>
 <reg32 offset="0x03b6" name="RBBM_PERFCTR_RBBM_3_LO"/>
 <reg32 offset="0x03b7" name="RBBM_PERFCTR_RBBM_3_HI"/>
 <reg32 offset="0x03b8" name="RBBM_PERFCTR_PC_0_LO"/>
 <reg32 offset="0x03b9" name="RBBM_PERFCTR_PC_0_HI"/>
 <reg32 offset="0x03ba" name="RBBM_PERFCTR_PC_1_LO"/>
 <reg32 offset="0x03bb" name="RBBM_PERFCTR_PC_1_HI"/>
 <reg32 offset="0x03bc" name="RBBM_PERFCTR_PC_2_LO"/>
 <reg32 offset="0x03bd" name="RBBM_PERFCTR_PC_2_HI"/>
 <reg32 offset="0x03be" name="RBBM_PERFCTR_PC_3_LO"/>
 <reg32 offset="0x03bf" name="RBBM_PERFCTR_PC_3_HI"/>
 <reg32 offset="0x03c0" name="RBBM_PERFCTR_PC_4_LO"/>
 <reg32 offset="0x03c1" name="RBBM_PERFCTR_PC_4_HI"/>
 <reg32 offset="0x03c2" name="RBBM_PERFCTR_PC_5_LO"/>
 <reg32 offset="0x03c3" name="RBBM_PERFCTR_PC_5_HI"/>
 <reg32 offset="0x03c4" name="RBBM_PERFCTR_PC_6_LO"/>
 <reg32 offset="0x03c5" name="RBBM_PERFCTR_PC_6_HI"/>
 <reg32 offset="0x03c6" name="RBBM_PERFCTR_PC_7_LO"/>
 <reg32 offset="0x03c7" name="RBBM_PERFCTR_PC_7_HI"/>
 <reg32 offset="0x03c8" name="RBBM_PERFCTR_VFD_0_LO"/>
 <reg32 offset="0x03c9" name="RBBM_PERFCTR_VFD_0_HI"/>
 <reg32 offset="0x03ca" name="RBBM_PERFCTR_VFD_1_LO"/>
 <reg32 offset="0x03cb" name="RBBM_PERFCTR_VFD_1_HI"/>
 <reg32 offset="0x03cc" name="RBBM_PERFCTR_VFD_2_LO"/>
 <reg32 offset="0x03cd" name="RBBM_PERFCTR_VFD_2_HI"/>
 <reg32 offset="0x03ce" name="RBBM_PERFCTR_VFD_3_LO"/>
 <reg32 offset="0x03cf" name="RBBM_PERFCTR_VFD_3_HI"/>
 <reg32 offset="0x03d0" name="RBBM_PERFCTR_VFD_4_LO"/>
 <reg32 offset="0x03d1" name="RBBM_PERFCTR_VFD_4_HI"/>
 <reg32 offset="0x03d2" name="RBBM_PERFCTR_VFD_5_LO"/>
 <reg32 offset="0x03d3" name="RBBM_PERFCTR_VFD_5_HI"/>
 <reg32 offset="0x03d4" name="RBBM_PERFCTR_VFD_6_LO"/>
 <reg32 offset="0x03d5" name="RBBM_PERFCTR_VFD_6_HI"/>
 <reg32 offset="0x03d6" name="RBBM_PERFCTR_VFD_7_LO"/>
 <reg32 offset="0x03d7" name="RBBM_PERFCTR_VFD_7_HI"/>
 <reg32 offset="0x03d8" name="RBBM_PERFCTR_HLSQ_0_LO"/>
 <reg32 offset="0x03d9" name="RBBM_PERFCTR_HLSQ_0_HI"/>
 <reg32 offset="0x03da" name="RBBM_PERFCTR_HLSQ_1_LO"/>
 <reg32 offset="0x03db" name="RBBM_PERFCTR_HLSQ_1_HI"/>
 <reg32 offset="0x03dc" name="RBBM_PERFCTR_HLSQ_2_LO"/>
 <reg32 offset="0x03dd" name="RBBM_PERFCTR_HLSQ_2_HI"/>
 <reg32 offset="0x03de" name="RBBM_PERFCTR_HLSQ_3_LO"/>
 <reg32 offset="0x03df" name="RBBM_PERFCTR_HLSQ_3_HI"/>
 <reg32 offset="0x03e0" name="RBBM_PERFCTR_HLSQ_4_LO"/>
 <reg32 offset="0x03e1" name="RBBM_PERFCTR_HLSQ_4_HI"/>
 <reg32 offset="0x03e2" name="RBBM_PERFCTR_HLSQ_5_LO"/>
 <reg32 offset="0x03e3" name="RBBM_PERFCTR_HLSQ_5_HI"/>
 <reg32 offset="0x03e4" name="RBBM_PERFCTR_HLSQ_6_LO"/>
 <reg32 offset="0x03e5" name="RBBM_PERFCTR_HLSQ_6_HI"/>
 <reg32 offset="0x03e6" name="RBBM_PERFCTR_HLSQ_7_LO"/>
 <reg32 offset="0x03e7" name="RBBM_PERFCTR_HLSQ_7_HI"/>
 <reg32 offset="0x03e8" name="RBBM_PERFCTR_VPC_0_LO"/>
 <reg32 offset="0x03e9" name="RBBM_PERFCTR_VPC_0_HI"/>
 <reg32 offset="0x03ea" name="RBBM_PERFCTR_VPC_1_LO"/>
 <reg32 offset="0x03eb" name="RBBM_PERFCTR_VPC_1_HI"/>
 <reg32 offset="0x03ec" name="RBBM_PERFCTR_VPC_2_LO"/>
 <reg32 offset="0x03ed" name="RBBM_PERFCTR_VPC_2_HI"/>
 <reg32 offset="0x03ee" name="RBBM_PERFCTR_VPC_3_LO"/>
 <reg32 offset="0x03ef" name="RBBM_PERFCTR_VPC_3_HI"/>
 <reg32 offset="0x03f0" name="RBBM_PERFCTR_CCU_0_LO"/>
 <reg32 offset="0x03f1" name="RBBM_PERFCTR_CCU_0_HI"/>
 <reg32 offset="0x03f2" name="RBBM_PERFCTR_CCU_1_LO"/>
 <reg32 offset="0x03f3" name="RBBM_PERFCTR_CCU_1_HI"/>
 <reg32 offset="0x03f4" name="RBBM_PERFCTR_CCU_2_LO"/>
 <reg32 offset="0x03f5" name="RBBM_PERFCTR_CCU_2_HI"/>
 <reg32 offset="0x03f6" name="RBBM_PERFCTR_CCU_3_LO"/>
 <reg32 offset="0x03f7" name="RBBM_PERFCTR_CCU_3_HI"/>
 <reg32 offset="0x03f8" name="RBBM_PERFCTR_TSE_0_LO"/>
 <reg32 offset="0x03f9" name="RBBM_PERFCTR_TSE_0_HI"/>
 <reg32 offset="0x03fa" name="RBBM_PERFCTR_TSE_1_LO"/>
 <reg32 offset="0x03fb" name="RBBM_PERFCTR_TSE_1_HI"/>
 <reg32 offset="0x03fc" name="RBBM_PERFCTR_TSE_2_LO"/>
 <reg32 offset="0x03fd" name="RBBM_PERFCTR_TSE_2_HI"/>
 <reg32 offset="0x03fe" name="RBBM_PERFCTR_TSE_3_LO"/>
 <reg32 offset="0x03ff" name="RBBM_PERFCTR_TSE_3_HI"/>
 <reg32 offset="0x0400" name="RBBM_PERFCTR_RAS_0_LO"/>
 <reg32 offset="0x0401" name="RBBM_PERFCTR_RAS_0_HI"/>
 <reg32 offset="0x0402" name="RBBM_PERFCTR_RAS_1_LO"/>
 <reg32 offset="0x0403" name="RBBM_PERFCTR_RAS_1_HI"/>
 <reg32 offset="0x0404" name="RBBM_PERFCTR_RAS_2_LO"/>
 <reg32 offset="0x0405" name="RBBM_PERFCTR_RAS_2_HI"/>
 <reg32 offset="0x0406" name="RBBM_PERFCTR_RAS_3_LO"/>
 <reg32 offset="0x0407" name="RBBM_PERFCTR_RAS_3_HI"/>
 <reg32 offset="0x0408" name="RBBM_PERFCTR_UCHE_0_LO"/>
 <reg32 offset="0x0409" name="RBBM_PERFCTR_UCHE_0_HI"/>
 <reg32 offset="0x040a" name="RBBM_PERFCTR_UCHE_1_LO"/>
 <reg32 offset="0x040b" name="RBBM_PERFCTR_UCHE_1_HI"/>
 <reg32 offset="0x040c" name="RBBM_PERFCTR_UCHE_2_LO"/>
 <reg32 offset="0x040d" name="RBBM_PERFCTR_UCHE_2_HI"/>
 <reg32 offset="0x040e" name="RBBM_PERFCTR_UCHE_3_LO"/>
 <reg32 offset="0x040f" name="RBBM_PERFCTR_UCHE_3_HI"/>
 <reg32 offset="0x0410" name="RBBM_PERFCTR_UCHE_4_LO"/>
 <reg32 offset="0x0411" name="RBBM_PERFCTR_UCHE_4_HI"/>
 <reg32 offset="0x0412" name="RBBM_PERFCTR_UCHE_5_LO"/>
 <reg32 offset="0x0413" name="RBBM_PERFCTR_UCHE_5_HI"/>
 <reg32 offset="0x0414" name="RBBM_PERFCTR_UCHE_6_LO"/>
 <reg32 offset="0x0415" name="RBBM_PERFCTR_UCHE_6_HI"/>
 <reg32 offset="0x0416" name="RBBM_PERFCTR_UCHE_7_LO"/>
 <reg32 offset="0x0417" name="RBBM_PERFCTR_UCHE_7_HI"/>
 <reg32 offset="0x0418" name="RBBM_PERFCTR_TP_0_LO"/>
 <reg32 offset="0x0419" name="RBBM_PERFCTR_TP_0_HI"/>
 <reg32 offset="0x041a" name="RBBM_PERFCTR_TP_1_LO"/>
 <reg32 offset="0x041b" name="RBBM_PERFCTR_TP_1_HI"/>
 <reg32 offset="0x041c" name="RBBM_PERFCTR_TP_2_LO"/>
 <reg32 offset="0x041d" name="RBBM_PERFCTR_TP_2_HI"/>
 <reg32 offset="0x041e" name="RBBM_PERFCTR_TP_3_LO"/>
 <reg32 offset="0x041f" name="RBBM_PERFCTR_TP_3_HI"/>
 <reg32 offset="0x0420" name="RBBM_PERFCTR_TP_4_LO"/>
 <reg32 offset="0x0421" name="RBBM_PERFCTR_TP_4_HI"/>
 <reg32 offset="0x0422" name="RBBM_PERFCTR_TP_5_LO"/>
 <reg32 offset="0x0423" name="RBBM_PERFCTR_TP_5_HI"/>
 <reg32 offset="0x0424" name="RBBM_PERFCTR_TP_6_LO"/>
 <reg32 offset="0x0425" name="RBBM_PERFCTR_TP_6_HI"/>
 <reg32 offset="0x0426" name="RBBM_PERFCTR_TP_7_LO"/>
 <reg32 offset="0x0427" name="RBBM_PERFCTR_TP_7_HI"/>
 <reg32 offset="0x0428" name="RBBM_PERFCTR_SP_0_LO"/>
 <reg32 offset="0x0429" name="RBBM_PERFCTR_SP_0_HI"/>
 <reg32 offset="0x042a" name="RBBM_PERFCTR_SP_1_LO"/>
 <reg32 offset="0x042b" name="RBBM_PERFCTR_SP_1_HI"/>
 <reg32 offset="0x042c" name="RBBM_PERFCTR_SP_2_LO"/>
 <reg32 offset="0x042d" name="RBBM_PERFCTR_SP_2_HI"/>
 <reg32 offset="0x042e" name="RBBM_PERFCTR_SP_3_LO"/>
 <reg32 offset="0x042f" name="RBBM_PERFCTR_SP_3_HI"/>
 <reg32 offset="0x0430" name="RBBM_PERFCTR_SP_4_LO"/>
 <reg32 offset="0x0431" name="RBBM_PERFCTR_SP_4_HI"/>
 <reg32 offset="0x0432" name="RBBM_PERFCTR_SP_5_LO"/>
 <reg32 offset="0x0433" name="RBBM_PERFCTR_SP_5_HI"/>
 <reg32 offset="0x0434" name="RBBM_PERFCTR_SP_6_LO"/>
 <reg32 offset="0x0435" name="RBBM_PERFCTR_SP_6_HI"/>
 <reg32 offset="0x0436" name="RBBM_PERFCTR_SP_7_LO"/>
 <reg32 offset="0x0437" name="RBBM_PERFCTR_SP_7_HI"/>
 <reg32 offset="0x0438" name="RBBM_PERFCTR_SP_8_LO"/>
 <reg32 offset="0x0439" name="RBBM_PERFCTR_SP_8_HI"/>
 <reg32 offset="0x043a" name="RBBM_PERFCTR_SP_9_LO"/>
 <reg32 offset="0x043b" name="RBBM_PERFCTR_SP_9_HI"/>
 <reg32 offset="0x043c" name="RBBM_PERFCTR_SP_10_LO"/>
 <reg32 offset="0x043d" name="RBBM_PERFCTR_SP_10_HI"/>
 <reg32 offset="0x043e" name="RBBM_PERFCTR_SP_11_LO"/>
 <reg32 offset="0x043f" name="RBBM_PERFCTR_SP_11_HI"/>
 <reg32 offset="0x0440" name="RBBM_PERFCTR_RB_0_LO"/>
 <reg32 offset="0x0441" name="RBBM_PERFCTR_RB_0_HI"/>
 <reg32 offset="0x0442" name="RBBM_PERFCTR_RB_1_LO"/>
 <reg32 offset="0x0443" name="RBBM_PERFCTR_RB_1_HI"/>
 <reg32 offset="0x0444" name="RBBM_PERFCTR_RB_2_LO"/>
 <reg32 offset="0x0445" name="RBBM_PERFCTR_RB_2_HI"/>
 <reg32 offset="0x0446" name="RBBM_PERFCTR_RB_3_LO"/>
 <reg32 offset="0x0447" name="RBBM_PERFCTR_RB_3_HI"/>
 <reg32 offset="0x0448" name="RBBM_PERFCTR_RB_4_LO"/>
--> --------------------

--> maximum size reached

--> --------------------