/* * Copyright 2010 Red Hat Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: Ben Skeggs #include "ctxgf100.h" #include <subdev/fb.h>#include <subdev/mc.h>#include <subdev/timer.h>#include <engine/fifo.h>/******************************************************************************* * PGRAPH context register lists static const struct gf100_gr_initconst struct gf100_gr_packstatic const struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_packconst struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initstatic const struct gf100_gr_initstatic const struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initstatic const struct gf100_gr_initconst struct gf100_gr_packconst struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initstatic const struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_packconst struct gf100_gr_packstatic const struct gf100_gr_initconst struct gf100_gr_packconst struct gf100_gr_initstatic const struct gf100_gr_initconst struct gf100_gr_initconst struct gf100_gr_initstatic const struct gf100_gr_initconst struct gf100_gr_initstatic const struct gf100_gr_initconst struct gf100_gr_pack/******************************************************************************* * PGRAPH context implementation void struct gf100_gr_chan *chan, u32 addr, u32 data)if (unlikely(!chan->mmio)) {return ;void struct gf100_gr *gr)struct nvkm_device *device = gr->base.engine.subdev.device;void struct gf100_gr_chan *chan, u64 addr, u32 size)void struct gf100_gr_chan *chan, u64 addr)void struct gf100_gr_chan *chan)struct gf100_gr *gr = chan->gr;const struct gf100_grctx_func *grctx = gr->func->grctx;const u32 attrib = grctx->attrib_nr;int gpc, tpc;for (gpc = 0; gpc < gr->gpc_nr; gpc++) {for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {const u32 o = TPC_UNIT(gpc, tpc, 0x0520);void struct gf100_gr_chan *chan, u64 addr, u32 size)struct gf100_gr *gr)const struct gf100_grctx_func *grctx = gr->func->grctx;return 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max) * gr->tpc_total;void struct gf100_gr *gr)void struct gf100_gr *gr)struct nvkm_device *device = gr->base.engine.subdev.device;const u8 gpcmax = nvkm_rd32(device, 0x022430);const u8 tpcmax = nvkm_rd32(device, 0x022434) * gpcmax;int i, j, sm = 0;for (i = 0; i < DIV_ROUND_UP(tpcmax, 4); i++) {for (data = 0, j = 0; j < 4; j++) {if (sm < gr->sm_nr)else void struct gf100_gr *gr)struct nvkm_device *device = gr->base.engine.subdev.device;int i;/* Pack tile map into register format. */ for (i = 0; i < 32; i++)/* Magic. */ while (!(ntpcv & (1 << 4))) {for (i = 1; i < 7; i++)/* GPC_BROADCAST */ for (i = 0; i < 6; i++)/* GPC_BROADCAST.TP_BROADCAST */ for (i = 0; i < 6; i++)/* UNK78xx */ for (i = 0; i < 6; i++)void struct gf100_gr *gr)struct nvkm_device *device = gr->base.engine.subdev.device;if (fbps == 1)static const u32//XXX: 3 //XXX: 5 //XXX: 6 //XXX: 9 //XXX: 10 //XXX: 12 //XXX: 13 void struct gf100_gr *gr)struct nvkm_subdev *subdev = &gr->base.engine.subdev;struct nvkm_device *device = subdev->device;int i, gpc;for (i = 0; i < 32; i++) {if (!atarget) {"missing alpha/beta mapping table\n" );while (atarget) {for (gpc = 0; atarget && gpc < gr->gpc_nr; gpc++) {if (abits[gpc] < gr->tpc_nr[gpc]) {for (gpc = 0; gpc < gr->gpc_nr; gpc++) {void struct gf100_gr *gr, int gpc)struct nvkm_device *device = gr->base.engine.subdev.device;void struct gf100_gr *gr, int gpc, int tpc, int sm)struct nvkm_device *device = gr->base.engine.subdev.device;void struct gf100_gr *gr)const struct gf100_grctx_func *func = gr->func->grctx;int sm;for (sm = 0; sm < gr->sm_nr; sm++) {if (func->tpc_nr)false , true );if (!func->skip_pd_num_tpc_per_gpc)true , false );if (func->r4060a8)if (func->alpha_beta_tables)if (func->max_ways_evict)if (func->dist_skip_table)if (func->r406500)if (func->gpc_tpc_nr)if (func->r419f78)if (func->tpc_mask)if (func->smid_config)void struct gf100_gr_chan *chan)struct gf100_gr *gr = chan->gr;struct nvkm_device *device = gr->base.engine.subdev.device;const struct gf100_grctx_func *grctx = gr->func->grctx;if (!gr->sw_ctx) {else {if (gr->func->init_419bd8)if (grctx->r419ea8)if (grctx->patch_ltc)if (grctx->unknown_size)if (grctx->r400088) grctx->r400088(gr, false );if (gr->bundle)else if (gr->bundle_veid)else if (gr->bundle64)else if (grctx->sw_bundle64_init)if (grctx->r400088) grctx->r400088(gr, true );if (gr->method)else if (grctx->r419cb8)if (grctx->r418800)if (grctx->r419eb0)if (grctx->r419e00)if (grctx->r418e94)if (grctx->r419a3c)if (grctx->r408840)if (grctx->r419c0c)#define CB_RESERVED 0x80000int struct gf100_gr *gr, struct gf100_gr_chan *chan, struct nvkm_gpuobj *inst)const struct gf100_grctx_func *grctx = gr->func->grctx;struct nvkm_subdev *subdev = &gr->base.engine.subdev;struct nvkm_device *device = subdev->device;struct nvkm_memory *data = NULL;struct nvkm_vma *ctx = NULL;int ret, i;/* NV_PGRAPH_FE_PWR_MODE_FORCE_ON. */ if (!(nvkm_rd32(device, 0x404170) & 0x00000010))break ;if (grctx->unkn88c)true );/* Reset FECS. */ if (grctx->unkn88c)false );/* NV_PGRAPH_FE_PWR_MODE_AUTO. */ if (!(nvkm_rd32(device, 0x404170) & 0x00000010))break ;/* Init SCC RAM. */ /* Allocate memory to store context, and dummy global context buffers. */ true , &data);if (ret)goto done;if (ret)goto done;if (ret)goto done;/* Setup context pointer. */ /* Make channel current. */ if (gr->firmware) {if (ret)goto done_inst;else {if (nvkm_rd32(device, 0x409800) & 0x80000000)break ;if (!gr->firmware) {/* Trigger a context unload by unsetting the "next channel valid" bit * and faking a context switch interrupt. if (nvkm_msec(device, 2000,if (!(nvkm_rd32(device, 0x409b00) & 0x80000000))break ;goto done_inst;else {if (ret)goto done_inst;if (gr->data) {for (i = 0; i < gr->size; i += 4)else {return ret;const struct gf100_grctx_func
Messung V0.5 C=96 H=96 G=95
