/* * The R8A7779 DU requires a 16 pixels pitch alignment as documented, * but the R8A7790 DU seems to require a 128 bytes pitch alignment.
*/ if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
align = 128; else
align = 16 * args->bpp / 8;
format = rcar_du_format_info(mode_cmd->pixel_format); if (format == NULL) {
dev_dbg(dev->dev, "unsupported pixel format %p4cc\n",
&mode_cmd->pixel_format); return ERR_PTR(-EINVAL);
}
if (rcdu->info->gen < 3) { /* * On Gen2 the DU limits the pitch to 4095 pixels and requires * buffers to be aligned to a 16 pixels boundary (or 128 bytes * on some platforms).
*/ unsignedint bpp = format->planes == 1 ? format->bpp / 8 : 1;
max_pitch = 4095 * bpp;
if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
align = 128; else
align = 16 * bpp;
} else { /* * On Gen3 the memory interface is handled by the VSP that * limits the pitch to 65535 bytes and has no alignment * constraint.
*/
max_pitch = 65535;
align = 1;
}
if (mode_cmd->pitches[0] & (align - 1) ||
mode_cmd->pitches[0] > max_pitch) {
dev_dbg(dev->dev, "invalid pitch value %u\n",
mode_cmd->pitches[0]); return ERR_PTR(-EINVAL);
}
/* * Calculate the chroma plane(s) pitch using the horizontal subsampling * factor. For semi-planar formats, the U and V planes are combined, the * pitch must thus be doubled.
*/
chroma_pitch = mode_cmd->pitches[0] / format->hsub; if (format->planes == 2)
chroma_pitch *= 2;
for (i = 1; i < format->planes; ++i) { if (mode_cmd->pitches[i] != chroma_pitch) {
dev_dbg(dev->dev, "luma and chroma pitches are not compatible\n"); return ERR_PTR(-EINVAL);
}
}
/* Locate the connected entity and initialize the encoder. */
entity = of_graph_get_remote_port_parent(ep->local_node); if (!entity) {
dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
ep->local_node); return -ENODEV;
}
if (!of_device_is_available(entity)) {
dev_dbg(rcdu->dev, "connected entity %pOF is disabled, skipping\n",
entity);
of_node_put(entity); return -ENODEV;
}
ret = rcar_du_encoder_init(rcdu, output, entity); if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)
dev_warn(rcdu->dev, "failed to initialize encoder %pOF on output %s (%d), skipping\n",
entity, rcar_du_output_name(output), ret);
/* * Iterate over the endpoints and create one encoder for each output * pipeline.
*/
for_each_endpoint_of_node(np, ep_node) { enum rcar_du_output output; struct of_endpoint ep; unsignedint i; int ret;
ret = of_graph_parse_endpoint(ep_node, &ep); if (ret < 0) {
of_node_put(ep_node); return ret;
}
/* Find the output route corresponding to the port number. */ for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) { if (rcdu->info->routes[i].possible_crtcs &&
rcdu->info->routes[i].port == ep.port) {
output = i; break;
}
}
if (i == RCAR_DU_OUTPUT_MAX) {
dev_warn(rcdu->dev, "port %u references unexisting output, skipping\n",
ep.port); continue;
}
/* Process the output pipeline. */
ret = rcar_du_encoders_init_one(rcdu, output, &ep); if (ret < 0) { if (ret == -EPROBE_DEFER) {
of_node_put(ep_node); return ret;
}
continue;
}
num_encoders++;
}
return num_encoders;
}
staticint rcar_du_properties_init(struct rcar_du_device *rcdu)
{ /* * The color key is expressed as an RGB888 triplet stored in a 32-bit * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0) * or enable source color keying (1).
*/
rcdu->props.colorkey =
drm_property_create_range(&rcdu->ddev, 0, "colorkey",
0, 0x01ffffff); if (rcdu->props.colorkey == NULL) return -ENOMEM;
/* * First parse the DT vsps property to populate the list of VSPs. Each * entry contains a pointer to the VSP DT node and a bitmask of the * connected DU CRTCs.
*/
ret = of_property_count_u32_elems(np, vsps_prop_name); if (ret < 0) { /* Backward compatibility with old DTBs. */
vsps_prop_name = "vsps";
ret = of_property_count_u32_elems(np, vsps_prop_name);
}
cells = ret / rcdu->num_crtcs - 1; if (cells > 1) return -EINVAL;
for (i = 0; i < rcdu->num_crtcs; ++i) { unsignedint j;
ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,
cells, i, &args); if (ret < 0) goto done;
/* * Add the VSP to the list or update the corresponding existing * entry if the VSP has already been added.
*/ for (j = 0; j < vsps_count; ++j) { if (vsps[j].np == args.np) break;
}
if (j < vsps_count)
of_node_put(args.np); else
vsps[vsps_count++].np = args.np;
vsps[j].crtcs_mask |= BIT(i);
/* * Store the VSP pointer and pipe index in the CRTC. If the * second cell of the 'renesas,vsps' specifier isn't present, * default to 0 to remain compatible with older DT bindings.
*/
rcdu->crtcs[i].vsp = &rcdu->vsps[j];
rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
}
/* * Then initialize all the VSPs from the node pointers and CRTCs bitmask * computed previously.
*/ for (i = 0; i < vsps_count; ++i) { struct rcar_du_vsp *vsp = &rcdu->vsps[i];
vsp->index = i;
vsp->dev = rcdu;
ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask); if (ret) goto done;
}
done: for (i = 0; i < ARRAY_SIZE(vsps); ++i)
of_node_put(vsps[i].np);
cells = of_property_count_u32_elems(np, "renesas,cmms"); if (cells == -EINVAL) return 0;
if (cells > rcdu->num_crtcs) {
dev_err(rcdu->dev, "Invalid number of entries in 'renesas,cmms'\n"); return -EINVAL;
}
for (i = 0; i < cells; ++i) { struct platform_device *pdev; struct device_link *link; struct device_node *cmm; int ret;
cmm = of_parse_phandle(np, "renesas,cmms", i); if (!cmm) {
dev_err(rcdu->dev, "Failed to parse 'renesas,cmms' property\n"); return -EINVAL;
}
if (!of_device_is_available(cmm)) { /* It's fine to have a phandle to a non-enabled CMM. */
of_node_put(cmm); continue;
}
pdev = of_find_device_by_node(cmm); if (!pdev) {
dev_err(rcdu->dev, "No device found for CMM%u\n", i);
of_node_put(cmm); return -EINVAL;
}
of_node_put(cmm);
/* * -ENODEV is used to report that the CMM config option is * disabled: return 0 and let the DU continue probing.
*/
ret = rcar_cmm_init(pdev); if (ret) {
platform_device_put(pdev); return ret == -ENODEV ? 0 : ret;
}
rcdu->cmms[i] = pdev;
/* * Enforce suspend/resume ordering by making the CMM a provider * of the DU: CMM is suspended after and resumed before the DU.
*/
link = device_link_add(rcdu->dev, &pdev->dev, DL_FLAG_STATELESS); if (!link) {
dev_err(rcdu->dev, "Failed to create device link to CMM%u\n", i); return -EINVAL;
}
}
if (rcdu->info->gen < 3) {
dev->mode_config.max_width = 4095;
dev->mode_config.max_height = 2047;
} else { /* * The Gen3 DU uses the VSP1 for memory access, and is limited * to frame sizes of 8190x8190.
*/
dev->mode_config.max_width = 8190;
dev->mode_config.max_height = 8190;
}
ret = rcar_du_properties_init(rcdu); if (ret < 0) return ret;
/* * Initialize vertical blanking interrupts handling. Start with vblank * disabled for all CRTCs.
*/
ret = drm_vblank_init(dev, rcdu->num_crtcs); if (ret < 0) return ret;
/* Initialize the groups. */
num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2);
for (i = 0; i < num_groups; ++i) { struct rcar_du_group *rgrp = &rcdu->groups[i];
mutex_init(&rgrp->lock);
rgrp->dev = rcdu;
rgrp->mmio_offset = mmio_offsets[i];
rgrp->index = i; /* Extract the channel mask for this group only. */
rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
& GENMASK(1, 0);
rgrp->num_crtcs = hweight8(rgrp->channels_mask);
/* * If we have more than one CRTCs in this group pre-associate * the low-order planes with CRTC 0 and the high-order planes * with CRTC 1 to minimize flicker occurring when the * association is changed.
*/
rgrp->dptsr_planes = rgrp->num_crtcs > 1
? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
: 0;
if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
ret = rcar_du_planes_init(rgrp); if (ret < 0) return ret;
}
}
/* Initialize the compositors. */ if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
ret = rcar_du_vsps_init(rcdu); if (ret < 0) return ret;
}
/* Initialize the Color Management Modules. */
ret = rcar_du_cmm_init(rcdu); if (ret) return dev_err_probe(rcdu->dev, ret, "failed to initialize CMM\n");
/* Create the CRTCs. */ for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) { struct rcar_du_group *rgrp;
/* Skip unpopulated DU channels. */ if (!(rcdu->info->channels_mask & BIT(hwindex))) continue;
rgrp = &rcdu->groups[hwindex / 2];
ret = rcar_du_crtc_create(rgrp, swindex++, hwindex); if (ret < 0) return ret;
}
/* Initialize the encoders. */
ret = rcar_du_encoders_init(rcdu); if (ret < 0) return dev_err_probe(rcdu->dev, ret, "failed to initialize encoders\n");
if (ret == 0) {
dev_err(rcdu->dev, "error: no encoder could be initialized\n"); return -EINVAL;
}
num_encoders = ret;
/* * Set the possible CRTCs and possible clones. There's always at least * one way for all encoders to clone each other, set all bits in the * possible clones field.
*/
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { struct rcar_du_encoder *renc = to_rcar_encoder(encoder); conststruct rcar_du_output_routing *route =
&rcdu->info->routes[renc->output];
/* Create the writeback connectors. */ if (rcdu->info->gen >= 3) { for (i = 0; i < rcdu->num_crtcs; ++i) { struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i];
ret = rcar_du_writeback_init(rcdu, rcrtc); if (ret < 0) return ret;
}
}
/* * Initialize the default DPAD0 source to the index of the first DU * channel that can be connected to DPAD0. The exact value doesn't * matter as it should be overwritten by mode setting for the RGB * output, but it is nonetheless required to ensure a valid initial * hardware configuration on Gen3 where DU0 can't always be connected to * DPAD0.
*/
dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
rcdu->dpad0_source = ffs(dpad0_sources) - 1;
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