// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2015 Broadcom * Copyright (c) 2014 The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark <robdclark@gmail.com> #include "vc4_hdmi.h" #include "vc4_regs.h" #include "vc4_hdmi_regs.h" #define VC4_HDMI_TX_PHY_RESET_CTL_PLL_RESETB BIT(5)#define VC4_HDMI_TX_PHY_RESET_CTL_PLLDIV_RESETB BIT(4)#define VC4_HDMI_TX_PHY_RESET_CTL_TX_CK_RESET BIT(3)#define VC4_HDMI_TX_PHY_RESET_CTL_TX_2_RESET BIT(2)#define VC4_HDMI_TX_PHY_RESET_CTL_TX_1_RESET BIT(1)#define VC4_HDMI_TX_PHY_RESET_CTL_TX_0_RESET BIT(0)#define VC4_HDMI_TX_PHY_POWERDOWN_CTL_RNDGEN_PWRDN BIT(4)#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_SHIFT 29#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_PREEMP_MASK VC4_MASK(31, 29)#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_SHIFT 24#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_2_MAINDRV_MASK VC4_MASK(28, 24)#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_SHIFT 21#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_PREEMP_MASK VC4_MASK(23, 21)#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_SHIFT 16#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_1_MAINDRV_MASK VC4_MASK(20, 16)#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_SHIFT 13#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_PREEMP_MASK VC4_MASK(15, 13)#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_SHIFT 8#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_0_MAINDRV_MASK VC4_MASK(12, 8)#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_SHIFT 5#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_PREEMP_MASK VC4_MASK(7, 5)#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_SHIFT 0#define VC4_HDMI_TX_PHY_CTL_0_PREEMP_CK_MAINDRV_MASK VC4_MASK(4, 0)#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_SHIFT 15#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA2_MASK VC4_MASK(19, 15)#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_SHIFT 10#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA1_MASK VC4_MASK(14, 10)#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0_SHIFT 5#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_DATA0_MASK VC4_MASK(9, 5)#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_SHIFT 0#define VC4_HDMI_TX_PHY_CTL_1_RES_SEL_CK_MASK VC4_MASK(4, 0)#define VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN_SHIFT 16#define VC4_HDMI_TX_PHY_CTL_2_VCO_GAIN_MASK VC4_MASK(19, 16)#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2_SHIFT 12#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA2_MASK VC4_MASK(15, 12)#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1_SHIFT 8#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA1_MASK VC4_MASK(11, 8)#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_SHIFT 4#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELDATA0_MASK VC4_MASK(7, 4)#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_SHIFT 0#define VC4_HDMI_TX_PHY_CTL_2_TERM_RES_SELCK_MASK VC4_MASK(3, 0)#define VC4_HDMI_TX_PHY_CTL_3_RP_SHIFT 17#define VC4_HDMI_TX_PHY_CTL_3_RP_MASK VC4_MASK(19, 17)#define VC4_HDMI_TX_PHY_CTL_3_RZ_SHIFT 12#define VC4_HDMI_TX_PHY_CTL_3_RZ_MASK VC4_MASK(16, 12)#define VC4_HDMI_TX_PHY_CTL_3_CP1_SHIFT 10#define VC4_HDMI_TX_PHY_CTL_3_CP1_MASK VC4_MASK(11, 10)#define VC4_HDMI_TX_PHY_CTL_3_CP_SHIFT 8#define VC4_HDMI_TX_PHY_CTL_3_CP_MASK VC4_MASK(9, 8)#define VC4_HDMI_TX_PHY_CTL_3_CZ_SHIFT 6#define VC4_HDMI_TX_PHY_CTL_3_CZ_MASK VC4_MASK(7, 6)#define VC4_HDMI_TX_PHY_CTL_3_ICP_SHIFT 0#define VC4_HDMI_TX_PHY_CTL_3_ICP_MASK VC4_MASK(5, 0)#define VC4_HDMI_TX_PHY_PLL_CTL_0_MASH11_MODE BIT(13)#define VC4_HDMI_TX_PHY_PLL_CTL_0_VC_RANGE_EN BIT(12)#define VC4_HDMI_TX_PHY_PLL_CTL_0_EMULATE_VC_LOW BIT(11)#define VC4_HDMI_TX_PHY_PLL_CTL_0_EMULATE_VC_HIGH BIT(10)#define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL_SHIFT 9#define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_SEL_MASK VC4_MASK(9, 9)#define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_FB_DIV2 BIT(8)#define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_POST_DIV2 BIT(7)#define VC4_HDMI_TX_PHY_PLL_CTL_0_VCO_CONT_EN BIT(6)#define VC4_HDMI_TX_PHY_PLL_CTL_0_ENA_VCO_CLK BIT(5)#define VC4_HDMI_TX_PHY_PLL_CTL_1_CPP_SHIFT 16#define VC4_HDMI_TX_PHY_PLL_CTL_1_CPP_MASK VC4_MASK(27, 16)#define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY_SHIFT 14#define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_DELAY_MASK VC4_MASK(15, 14)#define VC4_HDMI_TX_PHY_PLL_CTL_1_FREQ_DOUBLER_ENABLE BIT(13)#define VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL_SHIFT 11#define VC4_HDMI_TX_PHY_PLL_CTL_1_POST_RST_SEL_MASK VC4_MASK(12, 11)#define VC4_HDMI_TX_PHY_CLK_DIV_VCO_SHIFT 8#define VC4_HDMI_TX_PHY_CLK_DIV_VCO_MASK VC4_MASK(15, 8)#define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_SHIFT 0#define VC4_HDMI_TX_PHY_PLL_CFG_PDIV_MASK VC4_MASK(3, 0)#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL_MASK VC4_MASK(13, 12)#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL_SHIFT 12#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL_MASK VC4_MASK(9, 8)#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL_SHIFT 8#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_MASK VC4_MASK(5, 4)#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL_SHIFT 4#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_MASK VC4_MASK(1, 0)#define VC4_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL_SHIFT 0#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_MASK VC4_MASK(27, 0)#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1_MIN_LIMIT_SHIFT 0#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_MASK VC4_MASK(27, 0)#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2_MAX_LIMIT_SHIFT 0#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD_MASK VC4_MASK(31, 16)#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_STABLE_THRESHOLD_SHIFT 16#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_MASK VC4_MASK(15, 0)#define VC4_HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4_HOLD_THRESHOLD_SHIFT 0#define VC4_HDMI_RM_CONTROL_EN_FREEZE_COUNTERS BIT(19)#define VC4_HDMI_RM_CONTROL_EN_LOAD_INTEGRATOR BIT(17)#define VC4_HDMI_RM_CONTROL_FREE_RUN BIT(4)#define VC4_HDMI_RM_OFFSET_ONLY BIT(31)#define VC4_HDMI_RM_OFFSET_OFFSET_SHIFT 0#define VC4_HDMI_RM_OFFSET_OFFSET_MASK VC4_MASK(30, 0)#define VC4_HDMI_RM_FORMAT_SHIFT_SHIFT 24#define VC4_HDMI_RM_FORMAT_SHIFT_MASK VC4_MASK(25, 24)#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BG_PWRUP BIT(8)#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_LDO_PWRUP BIT(7)#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_BIAS_PWRUP BIT(6)#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_RNDGEN_PWRUP BIT(4)#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_CK_PWRUP BIT(3)#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_2_PWRUP BIT(2)#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_1_PWRUP BIT(1)#define VC6_HDMI_TX_PHY_HDMI_POWERUP_CTL_TX_0_PWRUP BIT(0)#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFCLK_SEL_CMOS BIT(13)#define VC6_HDMI_TX_PHY_PLL_REFCLK_REFFRQ_MASK VC4_MASK(9, 0)#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_CLK0_SEL_MASK VC4_MASK(3, 2)#define VC6_HDMI_TX_PHY_PLL_POST_KDIV_KDIV_MASK VC4_MASK(1, 0)#define VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_EN BIT(10)#define VC6_HDMI_TX_PHY_PLL_VCOCLK_DIV_VCODIV_MASK VC4_MASK(9, 0)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_CTL_MASK VC4_MASK(31, 28)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_ENABLE_MASK VC4_MASK(27, 27)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_RATE_CTL_MASK VC4_MASK(26, 26)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_POST_TAP_EN_MASK VC4_MASK(25, 25)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_LDMOS_BIAS_CTL_MASK VC4_MASK(24, 23)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_COM_MODE_LDMOS_EN_MASK VC4_MASK(22, 22)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EDGE_SEL_MASK VC4_MASK(21, 21)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_HS_EN_MASK VC4_MASK(20, 20)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_TERM_CTL_MASK VC4_MASK(19, 18)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_EXT_CURRENT_SRC_EN_MASK VC4_MASK(17, 17)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_EN_MASK VC4_MASK(16, 16)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_CTL_MASK VC4_MASK(15, 12)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_INT_CURRENT_SRC_HS_EN_MASK VC4_MASK(11, 11)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_MAIN_TAP_CURRENT_SELECT_MASK VC4_MASK(10, 8)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_POST_TAP_CURRENT_SELECT_MASK VC4_MASK(7, 5)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_LOADING_MASK VC4_MASK(4, 3)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_SLEW_CTL_SLOW_DRIVING_MASK VC4_MASK(2, 1)#define VC6_HDMI_TX_PHY_HDMI_CTRL_CHX_FFE_PRE_TAP_EN_MASK VC4_MASK(0, 0)#define VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_PLLPOST_RESETB BIT(1)#define VC6_HDMI_TX_PHY_PLL_RESET_CTL_PLL_RESETB BIT(0)#define VC6_HDMI_TX_PHY_PLL_POWERUP_CTL_PLL_PWRUP BIT(0)#define OSCILLATOR_FREQUENCY 54000000void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,struct drm_connector_state *conn_state)unsigned long flags;/* PHY should be in reset, like * vc4_hdmi_encoder_disable() does. void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)unsigned long flags;void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi)unsigned long flags;void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi)unsigned long flags;static unsigned long long unsigned long long clock, u8 *vco_sel, u8 *vco_div)unsigned long long vco_freq = clock;unsigned int _vco_div = 0;unsigned int _vco_sel = 0;while (vco_freq < 3000000000ULL) {if (vco_freq > 4500000000ULL)return vco_freq;static u8 phy_get_cp_current(unsigned long vco_freq)if (vco_freq < 3700000000ULL)return 0x1c;return 0x18;static u32 phy_get_rm_offset(unsigned long long vco_freq)unsigned long long fref = OSCILLATOR_FREQUENCY;/* RM offset is stored as 9.22 format */ return offset;static u8 phy_get_vco_gain(unsigned long long vco_freq)if (vco_freq < 3350000000ULL)return 0xf;if (vco_freq < 3700000000ULL)return 0xc;if (vco_freq < 4050000000ULL)return 0x6;if (vco_freq < 4800000000ULL)return 0x5;if (vco_freq < 5200000000ULL)return 0x7;return 0x2;struct phy_lane_settings {struct {struct phy_settings {unsigned long long min_rate;unsigned long long max_rate;struct phy_lane_settings channel[3];struct phy_lane_settings clock;static const struct phy_settings vc5_hdmi_phy_settings[] = {static const struct phy_settings *phy_get_settings(unsigned long long tmds_rate)unsigned int count = ARRAY_SIZE(vc5_hdmi_phy_settings);unsigned int i;for (i = 0; i < count; i++) {const struct phy_settings *s = &vc5_hdmi_phy_settings[i];if (tmds_rate >= s->min_rate && tmds_rate <= s->max_rate)return s;/* * If the pixel clock exceeds our max setting, try the max * setting anyway. return &vc5_hdmi_phy_settings[count - 1];static const struct phy_lane_settings *enum vc4_hdmi_phy_channel chan,unsigned long long tmds_rate)const struct phy_settings *settings = phy_get_settings(tmds_rate);if (chan == PHY_LANE_CK)return &settings->clock;return &settings->channel[chan];static void vc5_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi)void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,struct drm_connector_state *conn_state)const struct phy_lane_settings *chan0_settings, *chan1_settings, *chan2_settings, *clock_settings;const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;unsigned long long pixel_freq = conn_state->hdmi.tmds_char_rate;unsigned long long vco_freq;unsigned char word_sel;unsigned long flags;if (pixel_freq >= 340000000)else void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)unsigned long flags;void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi)unsigned long flags;void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi)unsigned long flags;#define VC6_VCO_MIN_FREQ (8ULL * 1000 * 1000 * 1000)#define VC6_VCO_MAX_FREQ (12ULL * 1000 * 1000 * 1000)static unsigned long long unsigned long long tmds_rate, unsigned int *vco_div)unsigned int min_div;unsigned int max_div;unsigned int div;while (tmds_rate * div * 10 < VC6_VCO_MIN_FREQ)while (tmds_rate * (div + 1) * 10 < VC6_VCO_MAX_FREQ)return tmds_rate * div * 10;struct vc6_phy_lane_settings {unsigned int ext_current_ctl:4;unsigned int ffe_enable:1;unsigned int slew_rate_ctl:1;unsigned int ffe_post_tap_en:1;unsigned int ldmos_bias_ctl:2;unsigned int com_mode_ldmos_en:1;unsigned int edge_sel:1;unsigned int ext_current_src_hs_en:1;unsigned int term_ctl:2;unsigned int ext_current_src_en:1;unsigned int int_current_src_en:1;unsigned int int_current_ctl:4;unsigned int int_current_src_hs_en:1;unsigned int main_tap_current_select:3;unsigned int post_tap_current_select:3;unsigned int slew_ctl_slow_loading:2;unsigned int slew_ctl_slow_driving:2;unsigned int ffe_pre_tap_en:1;struct vc6_phy_settings {unsigned long long min_rate;unsigned long long max_rate;struct vc6_phy_lane_settings channel[3];struct vc6_phy_lane_settings clock;static const struct vc6_phy_settings vc6_hdmi_phy_settings[] = {/* 200mA */ /* 0.85V */ /* Enable External Current Source */ /* 200mA */ /* 17.6 mA */ /* 200mA */ /* 0.85V */ /* Enable External Current Source */ /* 200mA */ /* 17.6 mA */ /* 200mA */ /* 0.85V */ /* Enable External Current Source */ /* 200mA */ /* 17.6 mA */ /* 200mA */ /* 0.85V */ /* Enable External Current Source */ /* 200mA */ /* 17.6 mA */ /* 200mA and 180mA ?! */ /* 0.85V */ /* 100 Ohm */ /* Enable External Current Source */ /* Enable Internal Current Source */ /* 200mA and 180mA ?! */ /* 0.85V */ /* 100 Ohm */ /* Enable External Current Source */ /* Enable Internal Current Source */ /* 200mA and 180mA ?! */ /* 0.85V */ /* 100 Ohm */ /* Enable External Current Source */ /* Enable Internal Current Source */ /* 200mA and 180mA ?! */ /* 0.85V */ /* 100 Ohm */ /* Enable External Current Source */ /* Enable Internal Current Source */ /* Internal Current Source Half Swing Enable*/ /* 200mA */ /* Normal Slew Rate Control */ /* 0.85V */ /* 50 Ohms */ /* Enable External Current Source */ /* Enable Internal Current Source */ /* 200mA */ /* 17.6 mA */ /* 200mA */ /* Normal Slew Rate Control */ /* 0.85V */ /* 50 Ohms */ /* Enable External Current Source */ /* Enable Internal Current Source */ /* 200mA */ /* 17.6 mA */ /* 200mA */ /* Normal Slew Rate Control */ /* 0.85V */ /* 50 Ohms */ /* Enable External Current Source */ /* Enable Internal Current Source */ /* 200mA */ /* 17.6 mA */ /* 200mA */ /* Normal Slew Rate Control */ /* 0.85V */ /* External Current Source Half Swing Enable*/ /* 50 Ohms */ /* Enable External Current Source */ /* Enable Internal Current Source */ /* 200mA */ /* Internal Current Source Half Swing Enable*/ /* 17.6 mA */ static const struct vc6_phy_settings *unsigned long long tmds_rate)unsigned int count = ARRAY_SIZE(vc6_hdmi_phy_settings);unsigned int i;for (i = 0; i < count; i++) {const struct vc6_phy_settings *s = &vc6_hdmi_phy_settings[i];if (tmds_rate >= s->min_rate && tmds_rate <= s->max_rate)return s;/* * If the pixel clock exceeds our max setting, try the max * setting anyway. return &vc6_hdmi_phy_settings[count - 1];static const struct vc6_phy_lane_settings *enum vc4_hdmi_phy_channel chan,unsigned long long tmds_rate)const struct vc6_phy_settings *settings = vc6_phy_get_settings(tmds_rate);if (chan == PHY_LANE_CK)return &settings->clock;return &settings->channel[chan];static void vc6_hdmi_reset_phy(struct vc4_hdmi *vc4_hdmi)void vc6_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,struct drm_connector_state *conn_state)const struct vc6_phy_lane_settings *chan0_settings;const struct vc6_phy_lane_settings *chan1_settings;const struct vc6_phy_lane_settings *chan2_settings;const struct vc6_phy_lane_settings *clock_settings;const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;unsigned long long pixel_freq = conn_state->hdmi.tmds_char_rate;unsigned long long vco_freq;unsigned char word_sel;unsigned long flags;unsigned int vco_div;if (pixel_freq >= 340000000)else void vc6_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi)
Messung V0.5 C=95 H=94 G=94
¤ Dauer der Verarbeitung: 0.8 Sekunden
¤ *© Formatika GbR, Deutschland
