/** * DOC: GT Multicast/Replicated (MCR) Register Support * * Some GT registers are designed as "multicast" or "replicated" registers: * multiple instances of the same register share a single MMIO offset. MCR * registers are generally used when the hardware needs to potentially track * independent values of a register per hardware unit (e.g., per-subslice, * per-L3bank, etc.). The specific types of replication that exist vary * per-platform. * * MMIO accesses to MCR registers are controlled according to the settings * programmed in the platform's MCR_SELECTOR register(s). MMIO writes to MCR * registers can be done in either multicast (a single write updates all * instances of the register to the same value) or unicast (a write updates only * one specific instance) form. Reads of MCR registers always operate in a * unicast manner regardless of how the multicast/unicast bit is set in * MCR_SELECTOR. Selection of a specific MCR instance for unicast operations is * referred to as "steering." * * If MCR register operations are steered toward a hardware unit that is * fused off or currently powered down due to power gating, the MMIO operation * is "terminated" by the hardware. Terminated read operations will return a * value of zero and terminated unicast write operations will be silently * ignored. During device initialization, the goal of the various * ``init_steering_*()`` functions is to apply the platform-specific rules for * each MCR register type to identify a steering target that will select a * non-terminated instance. * * MCR registers are not available on Virtual Function (VF).
*/
/* * Although the bspec lists more "MSLICE" ranges than shown here, some of those * are of a "GAM" subclass that has special rules and doesn't need to be * included here.
*/ staticconststruct xe_mmio_range xehp_mslice_steering_table[] = {
{ 0x00DD00, 0x00DDFF },
{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
{},
};
/* * Group selects mslice, instance selects bank within mslice. * Bank 0 is always valid _except_ when the bank mask is 010b.
*/
gt->steering[L3BANK].group_target = __ffs(mslice_mask);
gt->steering[L3BANK].instance_target =
bank_mask & BIT(0) ? 0 : 2;
} elseif (gt_to_xe(gt)->info.platform == XE_DG2) {
u32 mslice_mask = REG_FIELD_GET(MEML3_EN_MASK,
xe_mmio_read32(mmio, MIRROR_FUSE3));
u32 bank = __ffs(mslice_mask) * 8;
/* * Like mslice registers, look for a valid mslice and steer to * the first L3BANK of that quad. Access to the Nth L3 bank is * split between the first bits of group and instance
*/
gt->steering[L3BANK].group_target = (bank >> 2) & 0x7;
gt->steering[L3BANK].instance_target = bank & 0x3;
} else {
u32 fuse = REG_FIELD_GET(L3BANK_MASK,
~xe_mmio_read32(mmio, MIRROR_FUSE3));
/* * mslice registers are valid (not terminated) if either the meml3 * associated with the mslice is present, or at least one DSS associated * with the mslice is present. There will always be at least one meml3 * so we can just use that to find a non-terminated mslice and ignore * the DSS fusing.
*/
gt->steering[MSLICE].group_target = __ffs(mask);
gt->steering[MSLICE].instance_target = 0; /* unused */
/* * LNCF termination is also based on mslice presence, so we'll set * it up here. Either LNCF within a non-terminated mslice will work, * so we just always pick LNCF 0 here.
*/
gt->steering[LNCF].group_target = __ffs(mask) << 1;
gt->steering[LNCF].instance_target = 0; /* unused */
}
/* * Try to query the GuC's hwconfig table for the maximum number of * slices and subslices. These don't reflect the platform's actual * slice/DSS counts, just the physical layout by which we should * determine the steering targets. On older platforms with older GuC * firmware releases it's possible that these attributes may not be * included in the table, so we can always fall back to the old * hardcoded layouts.
*/ #define HWCONFIG_ATTR_MAX_SLICES 1 #define HWCONFIG_ATTR_MAX_SUBSLICES 70
ret = xe_guc_hwconfig_lookup_u32(guc, HWCONFIG_ATTR_MAX_SLICES,
&max_slices); if (ret < 0 || max_slices == 0) goto fallback;
ret = xe_guc_hwconfig_lookup_u32(guc, HWCONFIG_ATTR_MAX_SUBSLICES,
&max_subslices); if (ret < 0 || max_subslices == 0) goto fallback;
return DIV_ROUND_UP(max_subslices, max_slices);
fallback: /* * Some older platforms don't have tables or don't have complete tables. * Newer platforms should always have the required info.
*/ if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 2000 &&
!gt_to_xe(gt)->info.force_execlist)
xe_gt_err(gt, "Slice/Subslice counts missing from hwconfig table; using typical fallback values\n");
/** * xe_gt_mcr_get_dss_steering - Get the group/instance steering for a DSS * @gt: GT structure * @dss: DSS ID to obtain steering for * @group: pointer to storage for steering group ID * @instance: pointer to storage for steering instance ID
*/ void xe_gt_mcr_get_dss_steering(struct xe_gt *gt, unsignedint dss, u16 *group, u16 *instance)
{
xe_gt_assert(gt, dss < XE_MAX_DSS_FUSE_BITS);
staticvoid init_steering_oaddrm(struct xe_gt *gt)
{ /* * First instance is only terminated if the entire first media slice * is absent (i.e., no VCS0 or VECS0).
*/ if (gt->info.engine_mask & (XE_HW_ENGINE_VCS0 | XE_HW_ENGINE_VECS0))
gt->steering[OADDRM].group_target = 0; else
gt->steering[OADDRM].group_target = 1;
/** * xe_gt_mcr_init_early - Early initialization of the MCR support * @gt: GT structure * * Perform early software only initialization of the MCR lock to allow * the synchronization on accessing the STEER_SEMAPHORE register and * use the xe_gt_mcr_multicast_write() function, plus the minimum * safe MCR registers required for VRAM/CCS probing.
*/ void xe_gt_mcr_init_early(struct xe_gt *gt)
{ struct xe_device *xe = gt_to_xe(gt);
/* Mark instance 0 as initialized, we need this early for VRAM and CCS probe. */
gt->steering[INSTANCE0].initialized = true;
}
/** * xe_gt_mcr_init - Normal initialization of the MCR support * @gt: GT structure * * Perform normal initialization of the MCR for all usages.
*/ void xe_gt_mcr_init(struct xe_gt *gt)
{ if (IS_SRIOV_VF(gt_to_xe(gt))) return;
/* Select non-terminated steering target for each type */ for (int i = 0; i < NUM_STEERING_TYPES; i++) {
gt->steering[i].initialized = true; if (gt->steering[i].ranges && xe_steering_types[i].init)
xe_steering_types[i].init(gt);
}
}
/** * xe_gt_mcr_set_implicit_defaults - Initialize steer control registers * @gt: GT structure * * Some register ranges don't need to have their steering control registers * changed on each access - it's sufficient to set them once on initialization. * This function sets those registers for each platform *
*/ void xe_gt_mcr_set_implicit_defaults(struct xe_gt *gt)
{ struct xe_device *xe = gt_to_xe(gt);
xe_mmio_write32(>->mmio, MCFG_MCR_SELECTOR, steer_val);
xe_mmio_write32(>->mmio, SF_MCR_SELECTOR, steer_val); /* * For GAM registers, all reads should be directed to instance 1 * (unicast reads against other instances are not allowed), * and instance 1 is already the hardware's default steering * target, which we never change
*/
}
}
/* * xe_gt_mcr_get_nonterminated_steering - find group/instance values that * will steer a register to a non-terminated instance * @gt: GT structure * @reg: register for which the steering is required * @group: return variable for group steering * @instance: return variable for instance steering * * This function returns a group/instance pair that is guaranteed to work for * read steering of the given register. Note that a value will be returned even * if the register is not replicated and therefore does not actually require * steering. * * Returns true if the caller should steer to the @group/@instance values * returned. Returns false if the caller need not perform any steering
*/ bool xe_gt_mcr_get_nonterminated_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
u8 *group, u8 *instance)
{ conststruct xe_reg reg = to_xe_reg(reg_mcr); conststruct xe_mmio_range *implicit_ranges;
for (int type = 0; type < IMPLICIT_STEERING; type++) { if (!gt->steering[type].ranges) continue;
for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) { if (xe_mmio_in_range(>->mmio, >->steering[type].ranges[i], reg)) {
drm_WARN(>_to_xe(gt)->drm, !gt->steering[type].initialized, "Uninitialized usage of MCR register %s/%#x\n",
xe_steering_types[type].name, reg.addr);
implicit_ranges = gt->steering[IMPLICIT_STEERING].ranges; if (implicit_ranges) for (int i = 0; implicit_ranges[i].end > 0; i++) if (xe_mmio_in_range(>->mmio, &implicit_ranges[i], reg)) returnfalse;
/* * Not found in a steering table and not a register with implicit * steering. Just steer to 0/0 as a guess and raise a warning.
*/
drm_WARN(>_to_xe(gt)->drm, true, "Did not find MCR register %#x in any MCR steering table\n",
reg.addr);
*group = 0;
*instance = 0;
returntrue;
}
/* * Obtain exclusive access to MCR steering. On MTL and beyond we also need * to synchronize with external clients (e.g., firmware), so a semaphore * register will also need to be taken.
*/ staticvoid mcr_lock(struct xe_gt *gt) __acquires(>->mcr_lock)
{ struct xe_device *xe = gt_to_xe(gt); int ret = 0;
spin_lock(>->mcr_lock);
/* * Starting with MTL we also need to grab a semaphore register * to synchronize with external agents (e.g., firmware) that now * shares the same steering control register. The semaphore is obtained * when a read to the relevant register returns 1.
*/ if (GRAPHICS_VERx100(xe) >= 1270)
ret = xe_mmio_wait32(>->mmio, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL, true);
drm_WARN_ON_ONCE(&xe->drm, ret == -ETIMEDOUT);
}
staticvoid mcr_unlock(struct xe_gt *gt) __releases(>->mcr_lock)
{ /* Release hardware semaphore - this is done by writing 1 to the register */ if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270)
xe_mmio_write32(>->mmio, STEER_SEMAPHORE, 0x1);
spin_unlock(>->mcr_lock);
}
/* * Access a register with specific MCR steering * * Caller needs to make sure the relevant forcewake wells are up.
*/ static u32 rw_with_mcr_steering(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
u8 rw_flag, int group, int instance, u32 value)
{ conststruct xe_reg reg = to_xe_reg(reg_mcr); struct xe_mmio *mmio = >->mmio; struct xe_reg steer_reg;
u32 steer_val, val = 0;
/* * Always leave the hardware in multicast mode when doing reads and only * change it to unicast mode when doing writes of a specific instance. * * The setting of the multicast/unicast bit usually wouldn't matter for * read operations (which always return the value from a single register * instance regardless of how that bit is set), but some platforms may * have workarounds requiring us to remain in multicast mode for reads, * e.g. Wa_22013088509 on PVC. There's no real downside to this, so * we'll just go ahead and do so on all platforms; we'll only clear the * multicast bit from the mask when explicitly doing a write operation. * * No need to save old steering reg value.
*/ if (rw_flag == MCR_OP_READ)
steer_val |= MCR_MULTICAST;
xe_mmio_write32(mmio, steer_reg, steer_val);
if (rw_flag == MCR_OP_READ)
val = xe_mmio_read32(mmio, reg); else
xe_mmio_write32(mmio, reg, value);
/* * If we turned off the multicast bit (during a write) we're required * to turn it back on before finishing. The group and instance values * don't matter since they'll be re-programmed on the next MCR * operation.
*/ if (rw_flag == MCR_OP_WRITE)
xe_mmio_write32(mmio, steer_reg, MCR_MULTICAST);
return val;
}
/** * xe_gt_mcr_unicast_read_any - reads a non-terminated instance of an MCR register * @gt: GT structure * @reg_mcr: register to read * * Reads a GT MCR register. The read will be steered to a non-terminated * instance (i.e., one that isn't fused off or powered down by power gating). * This function assumes the caller is already holding any necessary forcewake * domains. * * Returns the value from a non-terminated instance of @reg.
*/
u32 xe_gt_mcr_unicast_read_any(struct xe_gt *gt, struct xe_reg_mcr reg_mcr)
{ conststruct xe_reg reg = to_xe_reg(reg_mcr);
u8 group, instance;
u32 val; bool steer;
if (steer) {
mcr_lock(gt);
val = rw_with_mcr_steering(gt, reg_mcr, MCR_OP_READ,
group, instance, 0);
mcr_unlock(gt);
} else {
val = xe_mmio_read32(>->mmio, reg);
}
return val;
}
/** * xe_gt_mcr_unicast_read - read a specific instance of an MCR register * @gt: GT structure * @reg_mcr: the MCR register to read * @group: the MCR group * @instance: the MCR instance * * Returns the value read from an MCR register after steering toward a specific * group/instance.
*/
u32 xe_gt_mcr_unicast_read(struct xe_gt *gt, struct xe_reg_mcr reg_mcr, int group, int instance)
{
u32 val;
xe_gt_assert(gt, !IS_SRIOV_VF(gt_to_xe(gt)));
mcr_lock(gt);
val = rw_with_mcr_steering(gt, reg_mcr, MCR_OP_READ, group, instance, 0);
mcr_unlock(gt);
return val;
}
/** * xe_gt_mcr_unicast_write - write a specific instance of an MCR register * @gt: GT structure * @reg_mcr: the MCR register to write * @value: value to write * @group: the MCR group * @instance: the MCR instance * * Write an MCR register in unicast mode after steering toward a specific * group/instance.
*/ void xe_gt_mcr_unicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
u32 value, int group, int instance)
{
xe_gt_assert(gt, !IS_SRIOV_VF(gt_to_xe(gt)));
/** * xe_gt_mcr_multicast_write - write a value to all instances of an MCR register * @gt: GT structure * @reg_mcr: the MCR register to write * @value: value to write * * Write an MCR register in multicast mode to update all instances.
*/ void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr reg_mcr,
u32 value)
{ struct xe_reg reg = to_xe_reg(reg_mcr);
xe_gt_assert(gt, !IS_SRIOV_VF(gt_to_xe(gt)));
/* * Synchronize with any unicast operations. Once we have exclusive * access, the MULTICAST bit should already be set, so there's no need * to touch the steering register.
*/
mcr_lock(gt);
xe_mmio_write32(>->mmio, reg, value);
mcr_unlock(gt);
}
void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p)
{ for (int i = 0; i < NUM_STEERING_TYPES; i++) { if (gt->steering[i].ranges) {
drm_printf(p, "%s steering: group=%#x, instance=%#x\n",
xe_steering_types[i].name,
gt->steering[i].group_target,
gt->steering[i].instance_target); for (int j = 0; gt->steering[i].ranges[j].end; j++)
drm_printf(p, "\t0x%06x - 0x%06x\n",
gt->steering[i].ranges[j].start,
gt->steering[i].ranges[j].end);
}
}
}
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