// SPDX-License-Identifier: GPL-2.0 /* * Intel MAX 10 BMC HWMON Driver * * Copyright (C) 2018-2020 Intel Corporation. All rights reserved. * #include <linux/device.h>#include <linux/hwmon.h>#include <linux/mfd/intel-m10-bmc.h>#include <linux/module.h>#include <linux/mod_devicetable.h>#include <linux/platform_device.h>struct m10bmc_sdata {unsigned int reg_input;unsigned int reg_max;unsigned int reg_crit;unsigned int reg_hyst;unsigned int reg_min;unsigned int multiplier;const char *label;struct m10bmc_hwmon_board_data {const struct m10bmc_sdata *tables[hwmon_max];const struct hwmon_channel_info * const *hinfo;struct m10bmc_hwmon {struct device *dev;struct hwmon_chip_info chip;char *hw_name;struct intel_m10bmc *m10bmc;const struct m10bmc_hwmon_board_data *bdata;static const struct m10bmc_sdata n3000bmc_temp_tbl[] = {"Board Temperature" },"FPGA Die Temperature" },"QSFP0 Temperature" },"QSFP1 Temperature" },"Retimer A Temperature" },"Retimer A SerDes Temperature" },"Retimer B Temperature" },"Retimer B SerDes Temperature" },static const struct m10bmc_sdata n3000bmc_in_tbl[] = {"QSFP0 Supply Voltage" },"QSFP1 Supply Voltage" },"FPGA Core Voltage" },"12V Backplane Voltage" },"1.2V Voltage" },"12V AUX Voltage" },"1.8V Voltage" },"3.3V Voltage" },static const struct m10bmc_sdata n3000bmc_curr_tbl[] = {"FPGA Core Current" },"12V Backplane Current" },"12V AUX Current" },static const struct m10bmc_sdata n3000bmc_power_tbl[] = {"Board Power" },static const struct hwmon_channel_info * const n3000bmc_hinfo[] = {static const struct m10bmc_sdata d5005bmc_temp_tbl[] = {"Board Inlet Air Temperature" },"FPGA Core Temperature" },"Board Exhaust Air Temperature" },"FPGA Transceiver Temperature" },"RDIMM0 Temperature" },"RDIMM1 Temperature" },"RDIMM2 Temperature" },"RDIMM3 Temperature" },"QSFP0 Temperature" },"QSFP1 Temperature" },"3.3v Temperature" },"VCCERAM Temperature" },"VCCR Temperature" },"VCCT Temperature" },"1.8v Temperature" },"12v Backplane Temperature" },"12v AUX Temperature" },static const struct m10bmc_sdata d5005bmc_in_tbl[] = {"QSFP0 Supply Voltage" },"QSFP1 Supply Voltage" },"FPGA Core Voltage" },"3.3v Voltage" },"VCCERAM Voltage" },"VCCR Voltage" },"VCCT Voltage" },"1.8v Voltage" },"12v Backplane Voltage" },"12v AUX Voltage" },static const struct m10bmc_sdata d5005bmc_curr_tbl[] = {"FPGA Core Current" },"3.3v Current" },"VCCERAM Current" },"VCCR Current" },"VCCT Current" },"1.8v Current" },"12v Backplane Current" },"12v AUX Current" },static const struct m10bmc_hwmon_board_data n3000bmc_hwmon_bdata = {static const struct hwmon_channel_info * const d5005bmc_hinfo[] = {static const struct m10bmc_hwmon_board_data d5005bmc_hwmon_bdata = {static const struct m10bmc_sdata n5010bmc_temp_tbl[] = {"Board Local Temperature" },"FPGA 1 Temperature" },"FPGA 2 Temperature" },"Card Top Temperature" },"Card Bottom Temperature" },"FPGA 1.2V Temperature" },"FPGA 5V Temperature" },"FPGA 0.9V Temperature" },"FPGA 0.85V Temperature" },"AUX 12V Temperature" },"Backplane 12V Temperature" },"QSFP28-1 Temperature" },"QSFP28-2 Temperature" },"QSFP28-3 Temperature" },"QSFP28-4 Temperature" },"CVL1 Internal Temperature" },"CVL2 Internal Temperature" },static const struct m10bmc_sdata n5010bmc_in_tbl[] = {"FPGA 1.2V Voltage" },"FPGA 5V Voltage" },"FPGA 0.9V Voltage" },"FPGA 0.85V Voltage" },"AUX 12V Voltage" },"Backplane 12V Voltage" },"DDR4 1.2V Voltage" },"FPGA 1.8V Voltage" },"QDR 1.3V Voltage" },"CVL1 0.8V Voltage" },"CVL1 1.05V Voltage" },"CVL2 1.05V Voltage" },"CVL2 0.8V Voltage" },static const struct m10bmc_sdata n5010bmc_curr_tbl[] = {"FPGA 1.2V Current" },"FPGA 5V Current" },"FPGA 0.9V Current" },"FPGA 0.85V Current" },"AUX 12V Current" },"Backplane 12V Current" },"DDR4 1.2V Current" },"FPGA 1.8V Current" },"QDR 1.3V Current" },"CVL1 0.8V Current" },"CVL1 1.05V Current" },"CVL2 1.05V Current" },"CVL2 0.8V Current" },static const struct hwmon_channel_info * const n5010bmc_hinfo[] = {static const struct m10bmc_hwmon_board_data n5010bmc_hwmon_bdata = {static const struct m10bmc_sdata n6000bmc_temp_tbl[] = {"FPGA E-TILE Temperature #1" },"FPGA E-TILE Temperature #2" },"FPGA E-TILE Temperature #3" },"FPGA E-TILE Temperature #4" },"FPGA P-TILE Temperature" },"FPGA FABRIC Digital Temperature #1" },"FPGA FABRIC Digital Temperature #2" },"FPGA FABRIC Digital Temperature #3" },"FPGA FABRIC Digital Temperature #4" },"FPGA FABRIC Digital Temperature #5" },"FPGA FABRIC Remote Digital Temperature #1" },"FPGA FABRIC Remote Digital Temperature #2" },"FPGA FABRIC Remote Digital Temperature #3" },"FPGA FABRIC Remote Digital Temperature #4" },"Board Top Near FPGA Temperature" },"Board Bottom Near CVL Temperature" },"Board Top East Near VRs Temperature" },"CVL Die Temperature" },"Board Rear Side Temperature" },"Board Front Side Temperature" },"QSFP1 Case Temperature" },"QSFP2 Case Temperature" },"FPGA Core Voltage Phase 0 VR Temperature" },"FPGA Core Voltage Phase 1 VR Temperature" },"FPGA Core Voltage Phase 2 VR Temperature" },"FPGA Core Voltage VR Controller Temperature" },"FPGA VCCH VR Temperature" },"FPGA VCC_1V2 VR Temperature" },"FPGA VCCH, VCC_1V2 VR Controller Temperature" },"3V3 VR Temperature" },"CVL Core Voltage VR Temperature" },"FPGA P-Tile Temperature [Remote]" },"FPGA E-Tile Temperature [Remote]" },"FPGA SDM Temperature [Remote]" },"FPGA Corner Temperature [Remote]" },static const struct m10bmc_sdata n6000bmc_in_tbl[] = {"Inlet 12V PCIe Rail Voltage" },"Inlet 12V Aux Rail Voltage" },"Inlet 3V3 PCIe Rail Voltage" },"FPGA Core Voltage Rail Voltage" },"FPGA VCCH Rail Voltage" },"FPGA VCC_1V2 Rail Voltage" },"FPGA VCCH_GXER_1V1, VCCA_1V8 Voltage" },"FPGA VCCIO_1V2 Voltage" },"CVL Non Core Rails Inlet Voltage" },"MAX10 & Board CLK PWR 3V3 Inlet Voltage" },"CVL Core Voltage Rail Voltage" },"Board 3V3 VR Voltage" },"QSFP 3V3 Rail Voltage" },"QSFP (Primary) Supply Rail Voltage" },"QSFP (Secondary) Supply Rail Voltage" },"VCCCLK_GXER_2V5 Voltage" },"AVDDH_1V1_CVL Voltage" },"VDDH_1V8_CVL Voltage" },"VCCA_PLL Voltage" },"VCCRT_GXER_0V9 Voltage" },"VCCRT_GXPL_0V9 Voltage" },"VCCH_GXPL_1V8 Voltage" },"VCCPT_1V8 Voltage" },"VCC_3V3_M10 Voltage" },"VCC_1V8_M10 Voltage" },"VCC_1V2_EMIF1_2_3 Voltage" },"VCC_1V2_EMIF4_5 Voltage" },"VCCA_1V8 Voltage" },"VCCH_GXER_1V1 Voltage" },"AVDD_ETH_0V9_CVL Voltage" },"AVDD_PCIE_0V9_CVL Voltage" },static const struct m10bmc_sdata n6000bmc_curr_tbl[] = {"Inlet 12V PCIe Rail Current" },"Inlet 12V Aux Rail Current" },"Inlet 3V3 PCIe Rail Current" },"FPGA Core Voltage Rail Current" },"FPGA VCCH Rail Current" },"FPGA VCC_1V2 Rail Current" },"FPGA VCCH_GXER_1V1, VCCA_1V8 Current" },"FPGA VCCIO_1V2 Current" },"CVL Non Core Rails Inlet Current" },"MAX10 & Board CLK PWR 3V3 Inlet Current" },"CVL Core Voltage Rail Current" },"Board 3V3 VR Current" },"QSFP 3V3 Rail Current" },static const struct m10bmc_sdata n6000bmc_power_tbl[] = {"Board Power" },static const struct hwmon_channel_info * const n6000bmc_hinfo[] = {static const struct m10bmc_hwmon_board_data n6000bmc_hwmon_bdata = {static const struct m10bmc_sdata *struct m10bmc_hwmon *hw, enum hwmon_sensor_types type,int channel)const struct m10bmc_sdata *tbl;if (!tbl)return ERR_PTR(-EOPNOTSUPP);return &tbl[channel];static int do_sensor_read(struct m10bmc_hwmon *hw,const struct m10bmc_sdata *data,unsigned int regoff, long *val)unsigned int regval;int ret;if (ret)return ret;/* * BMC Firmware will return 0xdeadbeef if the sensor value is invalid * at that time. This usually happens on sensor channels which connect * to external pluggable modules, e.g. QSFP temperature and voltage. * When the QSFP is unplugged from cage, driver will get 0xdeadbeef * from their registers. if (regval == 0xdeadbeef)return -ENODATA;return 0;static int m10bmc_hwmon_read(struct device *dev, enum hwmon_sensor_types type,int channel, long *val)struct m10bmc_hwmon *hw = dev_get_drvdata(dev);unsigned int reg = 0, reg_hyst = 0;const struct m10bmc_sdata *data;long hyst, value;int ret;if (IS_ERR(data))return PTR_ERR(data);switch (type) {case hwmon_temp:switch (attr) {case hwmon_temp_input:break ;case hwmon_temp_max_hyst:case hwmon_temp_max:break ;case hwmon_temp_crit_hyst:case hwmon_temp_crit:break ;default :return -EOPNOTSUPP;break ;case hwmon_in:switch (attr) {case hwmon_in_input:break ;case hwmon_in_max:break ;case hwmon_in_crit:break ;case hwmon_in_min:break ;default :return -EOPNOTSUPP;break ;case hwmon_curr:switch (attr) {case hwmon_curr_input:break ;case hwmon_curr_max:break ;case hwmon_curr_crit:break ;default :return -EOPNOTSUPP;break ;case hwmon_power:switch (attr) {case hwmon_power_input:break ;default :return -EOPNOTSUPP;break ;default :return -EOPNOTSUPP;if (!reg)return -EOPNOTSUPP;if (ret)return ret;if (reg_hyst) {if (ret)return ret;return 0;static int m10bmc_hwmon_read_string(struct device *dev,enum hwmon_sensor_types type,int channel, const char **str)struct m10bmc_hwmon *hw = dev_get_drvdata(dev);const struct m10bmc_sdata *data;if (IS_ERR(data))return PTR_ERR(data);return 0;static const struct hwmon_ops m10bmc_hwmon_ops = {static int m10bmc_hwmon_probe(struct platform_device *pdev)const struct platform_device_id *id = platform_get_device_id(pdev);struct intel_m10bmc *m10bmc = dev_get_drvdata(pdev->dev.parent);struct device *hwmon_dev, *dev = &pdev->dev;struct m10bmc_hwmon *hw;sizeof (*hw), GFP_KERNEL);if (!hw)return -ENOMEM;const struct m10bmc_hwmon_board_data *)id->driver_data;if (IS_ERR(hw->hw_name))return PTR_ERR(hw->hw_name);return PTR_ERR_OR_ZERO(hwmon_dev);static const struct platform_device_id intel_m10bmc_hwmon_ids[] = {"n3000bmc-hwmon" ,unsigned long )&n3000bmc_hwmon_bdata,"d5005bmc-hwmon" ,unsigned long )&d5005bmc_hwmon_bdata,"n5010bmc-hwmon" ,unsigned long )&n5010bmc_hwmon_bdata,"n6000bmc-hwmon" ,unsigned long )&n6000bmc_hwmon_bdata,static struct platform_driver intel_m10bmc_hwmon_driver = {"intel-m10-bmc-hwmon" ,"Intel Corporation" );"Intel MAX 10 BMC hardware monitor" );"GPL" );"INTEL_M10_BMC_CORE" );
Messung V0.5 C=96 H=96 G=95
¤ Dauer der Verarbeitung: 0.7 Sekunden
¤ *© Formatika GbR, Deutschland
