staticvoid mmci_reg_delay(struct mmci_host *host)
{ /* * According to the spec, at least three feedback clock cycles * of max 52 MHz must pass between two writes to the MMCICLOCK reg. * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. * Worst delay time during card init is at 100 kHz => 30 us. * Worst delay time when up and running is at 25 MHz => 120 ns.
*/ if (host->cclk < 25000000)
udelay(30); else
ndelay(120);
}
/* * This must be called with host->lock held
*/ void mmci_write_clkreg(struct mmci_host *host, u32 clk)
{ if (host->clk_reg != clk) {
host->clk_reg = clk;
writel(clk, host->base + MMCICLOCK);
}
}
/* * This must be called with host->lock held
*/ void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
{ if (host->pwr_reg != pwr) {
host->pwr_reg = pwr;
writel(pwr, host->base + MMCIPOWER);
}
}
/* * This must be called with host->lock held
*/ staticvoid mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
{ /* Keep busy mode in DPSM and SDIO mask if enabled */
datactrl |= host->datactrl_reg & (host->variant->busy_dpsm_flag |
host->variant->datactrl_mask_sdio);
/* * This must be called with host->lock held
*/ staticvoid mmci_set_clkreg(struct mmci_host *host, unsignedint desired)
{ struct variant_data *variant = host->variant;
u32 clk = variant->clkreg;
/* Make sure cclk reflects the current calculated clock */
host->cclk = 0;
if (desired) { if (variant->explicit_mclk_control) {
host->cclk = host->mclk;
} elseif (desired >= host->mclk) {
clk = MCI_CLK_BYPASS; if (variant->st_clkdiv)
clk |= MCI_ST_UX500_NEG_EDGE;
host->cclk = host->mclk;
} elseif (variant->st_clkdiv) { /* * DB8500 TRM says f = mclk / (clkdiv + 2) * => clkdiv = (mclk / f) - 2 * Round the divider up so we don't exceed the max * frequency
*/
clk = DIV_ROUND_UP(host->mclk, desired) - 2; if (clk >= 256)
clk = 255;
host->cclk = host->mclk / (clk + 2);
} else { /* * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) * => clkdiv = mclk / (2 * f) - 1
*/
clk = host->mclk / (2 * desired) - 1; if (clk >= 256)
clk = 255;
host->cclk = host->mclk / (2 * (clk + 1));
}
clk |= variant->clkreg_enable;
clk |= MCI_CLK_ENABLE; /* This hasn't proven to be worthwhile */ /* clk |= MCI_CLK_PWRSAVE; */
}
/* Set actual clock for debug */
host->mmc->actual_clock = host->cclk;
if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
clk |= MCI_4BIT_BUS; if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
clk |= variant->clkreg_8bit_bus_enable;
ret = mmci_prep_data(host, data, false); if (ret) return ret;
if (!host->ops || !host->ops->dma_start) return -EINVAL;
/* Okay, go for it. */
dev_vdbg(mmc_dev(host->mmc), "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
data->sg_len, data->blksz, data->blocks, data->flags);
ret = host->ops->dma_start(host, &datactrl); if (ret) return ret;
/* Trigger the DMA transfer */
mmci_write_datactrlreg(host, datactrl);
/* * Let the MMCI say when the data is ended and it's time * to fire next DMA request. When that happens, MMCI will * call mmci_data_end()
*/
writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
host->base + MMCIMASK0); return 0;
}
writel(host->variant->busy_detect_mask, base + MMCICLEAR);
writel(readl(base + MMCIMASK0) &
~host->variant->busy_detect_mask, base + MMCIMASK0);
host->busy_state = MMCI_BUSY_DONE;
host->busy_status = 0;
}
/* * ux500_busy_complete() - this will wait until the busy status * goes off, saving any status that occur in the meantime into * host->busy_status until we know the card is not busy any more. * The function returns true when the busy detection is ended * and we should continue processing the command. * * The Ux500 typically fires two IRQs over a busy cycle like this: * * DAT0 busy +-----------------+ * | | * DAT0 not busy ----+ +-------- * * ^ ^ * | | * IRQ1 IRQ2
*/ staticbool ux500_busy_complete(struct mmci_host *host, struct mmc_command *cmd,
u32 status, u32 err_msk)
{ void __iomem *base = host->base; int retries = 10;
if (status & err_msk) { /* Stop any ongoing busy detection if an error occurs */
ux500_busy_clear_mask_done(host); goto out_ret_state;
}
/* * The state transitions are encoded in a state machine crossing * the edges in this switch statement.
*/ switch (host->busy_state) {
/* * Before unmasking for the busy end IRQ, confirm that the * command was sent successfully. To keep track of having a * command in-progress, waiting for busy signaling to end, * store the status in host->busy_status. * * Note that, the card may need a couple of clock cycles before * it starts signaling busy on DAT0, hence re-read the * MMCISTATUS register here, to allow the busy bit to be set.
*/ case MMCI_BUSY_DONE: /* * Save the first status register read to be sure to catch * all bits that may be lost will retrying. If the command * is still busy this will result in assigning 0 to * host->busy_status, which is what it should be in IDLE.
*/
host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); while (retries) {
status = readl(base + MMCISTATUS); /* Keep accumulating status bits */
host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); if (status & host->variant->busy_detect_flag) {
writel(readl(base + MMCIMASK0) |
host->variant->busy_detect_mask,
base + MMCIMASK0);
host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ;
schedule_delayed_work(&host->ux500_busy_timeout_work,
msecs_to_jiffies(cmd->busy_timeout)); goto out_ret_state;
}
retries--;
}
dev_dbg(mmc_dev(host->mmc), "no busy signalling in time CMD%02x\n", cmd->opcode);
ux500_busy_clear_mask_done(host); break;
/* * If there is a command in-progress that has been successfully * sent, then bail out if busy status is set and wait for the * busy end IRQ. * * Note that, the HW triggers an IRQ on both edges while * monitoring DAT0 for busy completion, but there is only one * status bit in MMCISTATUS for the busy state. Therefore * both the start and the end interrupts needs to be cleared, * one after the other. So, clear the busy start IRQ here.
*/ case MMCI_BUSY_WAITING_FOR_START_IRQ: if (status & host->variant->busy_detect_flag) {
host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND);
writel(host->variant->busy_detect_mask, base + MMCICLEAR);
host->busy_state = MMCI_BUSY_WAITING_FOR_END_IRQ;
} else {
dev_dbg(mmc_dev(host->mmc), "lost busy status when waiting for busy start IRQ CMD%02x\n",
cmd->opcode);
cancel_delayed_work(&host->ux500_busy_timeout_work);
ux500_busy_clear_mask_done(host);
} break;
case MMCI_BUSY_WAITING_FOR_END_IRQ: if (!(status & host->variant->busy_detect_flag)) {
host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND);
writel(host->variant->busy_detect_mask, base + MMCICLEAR);
cancel_delayed_work(&host->ux500_busy_timeout_work);
ux500_busy_clear_mask_done(host);
} else {
dev_dbg(mmc_dev(host->mmc), "busy status still asserted when handling busy end IRQ - will keep waiting CMD%02x\n",
cmd->opcode);
} break;
default:
dev_dbg(mmc_dev(host->mmc), "fell through on state %d, CMD%02x\n",
host->busy_state, cmd->opcode); break;
}
/* * All the DMA operation mode stuff goes inside this ifdef. * This assumes that you have a generic DMA device interface, * no custom DMA interfaces are supported.
*/ #ifdef CONFIG_DMA_ENGINE struct mmci_dmae_next { struct dma_async_tx_descriptor *desc; struct dma_chan *chan;
};
dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); if (!dmae) return -ENOMEM;
host->dma_priv = dmae;
dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx"); if (IS_ERR(dmae->rx_channel)) { int ret = PTR_ERR(dmae->rx_channel);
dmae->rx_channel = NULL; return ret;
}
dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx"); if (IS_ERR(dmae->tx_channel)) { if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER)
dev_warn(mmc_dev(host->mmc), "Deferred probe for TX channel ignored\n");
dmae->tx_channel = NULL;
}
/* * If only an RX channel is specified, the driver will * attempt to use it bidirectionally, however if it * is specified but cannot be located, DMA will be disabled.
*/ if (dmae->rx_channel && !dmae->tx_channel)
dmae->tx_channel = dmae->rx_channel;
if (dmae->rx_channel)
rxname = dma_chan_name(dmae->rx_channel); else
rxname = "none";
if (dmae->tx_channel)
txname = dma_chan_name(dmae->tx_channel); else
txname = "none";
/* * Limit the maximum segment size in any SG entry according to * the parameters of the DMA engine device.
*/ if (dmae->tx_channel) { struct device *dev = dmae->tx_channel->device->dev; unsignedint max_seg_size = dma_get_max_seg_size(dev);
if (max_seg_size < host->mmc->max_seg_size)
host->mmc->max_seg_size = max_seg_size;
} if (dmae->rx_channel) { struct device *dev = dmae->rx_channel->device->dev; unsignedint max_seg_size = dma_get_max_seg_size(dev);
if (max_seg_size < host->mmc->max_seg_size)
host->mmc->max_seg_size = max_seg_size;
}
if (!dmae->tx_channel || !dmae->rx_channel) {
mmci_dmae_release(host); return -EINVAL;
}
return 0;
}
/* * This is used in or so inline it * so it can be discarded.
*/ void mmci_dmae_release(struct mmci_host *host)
{ struct mmci_dmae_priv *dmae = host->dma_priv;
if (dmae->rx_channel)
dma_release_channel(dmae->rx_channel); if (dmae->tx_channel)
dma_release_channel(dmae->tx_channel);
dmae->rx_channel = dmae->tx_channel = NULL;
}
/* Wait up to 1ms for the DMA to complete */ for (i = 0; ; i++) {
status = readl(host->base + MMCISTATUS); if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) break;
udelay(10);
}
/* * Check to see whether we still have some data left in the FIFO - * this catches DMA controllers which are unable to monitor the * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- * contiguous buffers. On TX, we'll get a FIFO underrun error.
*/ if (status & MCI_RXDATAAVLBLMASK) {
mmci_dma_error(host); if (!data->error)
data->error = -EIO;
} elseif (!data->host_cookie) {
mmci_dma_unmap(host, data);
}
/* * Use of DMA with scatter-gather is impossible. * Give up with DMA and switch back to PIO mode.
*/ if (status & MCI_RXDATAAVLBLMASK) {
dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
mmci_dma_release(host);
}
/* If there's no DMA channel, fall back to PIO */ if (!chan) return -EINVAL;
/* If less than or equal to the fifo size, don't bother with DMA */ if (data->blksz * data->blocks <= variant->fifosize) return -EINVAL;
/* * This is necessary to get SDIO working on the Ux500. We do not yet * know if this is a bug in: * - The Ux500 DMA controller (DMA40) * - The MMCI DMA interface on the Ux500 * some power of two blocks (such as 64 bytes) are sent regularly * during SDIO traffic and those work fine so for these we enable DMA * transfers.
*/ if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz)) return -EINVAL;
if (next) return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); /* Check if next job is already prepared. */ if (dmae->cur && dmae->desc_current) return 0;
/* No job were prepared thus do it now. */ return _mmci_dmae_prep_data(host, data, &dmae->cur,
&dmae->desc_current);
}
int mmci_dmae_start(struct mmci_host *host, unsignedint *datactrl)
{ struct mmci_dmae_priv *dmae = host->dma_priv; int ret;
host->dma_in_progress = true;
ret = dma_submit_error(dmaengine_submit(dmae->desc_current)); if (ret < 0) {
host->dma_in_progress = false; return ret;
}
dma_async_issue_pending(dmae->cur);
if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
u32 clk;
datactrl |= variant->datactrl_mask_sdio;
/* * The ST Micro variant for SDIO small write transfers * needs to have clock H/W flow control disabled, * otherwise the transfer will not start. The threshold * depends on the rate of MCLK.
*/ if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
(host->size < 8 ||
(host->size <= 8 && host->mclk > 50000000)))
clk = host->clk_reg & ~variant->clkreg_enable; else
clk = host->clk_reg | variant->clkreg_enable;
/* * Attempt to use DMA operation mode, if this * should fail, fall back to PIO mode
*/ if (!mmci_dma_start(host, datactrl)) return;
/* IRQ mode, map the SG list for CPU reading/writing */
mmci_init_sg(host, data);
if (data->flags & MMC_DATA_READ) {
irqmask = MCI_RXFIFOHALFFULLMASK;
/* * If we have less than the fifo 'half-full' threshold to * transfer, trigger a PIO interrupt as soon as any data * is available.
*/ if (host->size < variant->fifohalfsize)
irqmask |= MCI_RXDATAAVLBLMASK;
} else { /* * We don't actually need to include "FIFO empty" here * since its implicit in "FIFO half empty".
*/
irqmask = MCI_TXFIFOHALFEMPTYMASK;
}
if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
writel(0, base + MMCICOMMAND);
mmci_reg_delay(host);
}
if (host->variant->cmdreg_stop &&
cmd->opcode == MMC_STOP_TRANSMISSION)
c |= host->variant->cmdreg_stop;
c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; if (cmd->flags & MMC_RSP_PRESENT) { if (cmd->flags & MMC_RSP_136)
c |= host->variant->cmdreg_lrsp_crc; elseif (cmd->flags & MMC_RSP_CRC)
c |= host->variant->cmdreg_srsp_crc; else
c |= host->variant->cmdreg_srsp;
}
/* Make sure we have data to handle */ if (!data) return;
/* First check for errors */
status_err = status & (host->variant->start_err |
MCI_DATACRCFAIL | MCI_DATATIMEOUT |
MCI_TXUNDERRUN | MCI_RXOVERRUN);
if (status_err) {
u32 remain, success;
/* Terminate the DMA transfer */
mmci_dma_error(host);
/* * Calculate how far we are into the transfer. Note that * the data counter gives the number of bytes transferred * on the MMC bus, not on the host side. On reads, this * can be as much as a FIFO-worth of data ahead. This * matters for FIFO overruns only.
*/ if (!host->variant->datacnt_useless) {
remain = readl(host->base + MMCIDATACNT);
success = data->blksz * data->blocks - remain;
} else {
success = 0;
}
/* * We need to be one of these interrupts to be considered worth * handling. Note that we tag on any latent IRQs postponed * due to waiting for busy status.
*/ if (host->variant->busy_timeout && busy_resp)
err_msk |= MCI_DATATIMEOUT;
/* Handle busy detection on DAT0 if the variant supports it. */ if (busy_resp && host->variant->busy_detect) if (!host->ops->busy_complete(host, cmd, status, err_msk)) return;
host->cmd = NULL;
if (status & MCI_CMDTIMEOUT) {
cmd->error = -ETIMEDOUT;
} elseif (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
cmd->error = -EILSEQ;
} elseif (host->variant->busy_timeout && busy_resp &&
status & MCI_DATATIMEOUT) {
cmd->error = -ETIMEDOUT; /* * This will wake up mmci_irq_thread() which will issue * a hardware reset of the MMCI block.
*/
host->irq_action = IRQ_WAKE_THREAD;
} else {
cmd->resp[0] = readl(base + MMCIRESPONSE0);
cmd->resp[1] = readl(base + MMCIRESPONSE1);
cmd->resp[2] = readl(base + MMCIRESPONSE2);
cmd->resp[3] = readl(base + MMCIRESPONSE3);
}
if ((!sbc && !cmd->data) || cmd->error) { if (host->data) { /* Terminate the DMA transfer */
mmci_dma_error(host);
mmci_stop_data(host); if (host->variant->cmdreg_stop && cmd->error) {
mmci_stop_command(host); return;
}
}
if (host->irq_action != IRQ_WAKE_THREAD)
mmci_request_end(host, host->mrq);
staticchar *ux500_state_str(struct mmci_host *host)
{ switch (host->busy_state) { case MMCI_BUSY_WAITING_FOR_START_IRQ: return"waiting for start IRQ"; case MMCI_BUSY_WAITING_FOR_END_IRQ: return"waiting for end IRQ"; case MMCI_BUSY_DONE: return"not waiting for IRQs"; default: return"unknown";
}
}
/* * This busy timeout worker is used to "kick" the command IRQ if a * busy detect IRQ fails to appear in reasonable time. Only used on * variants with busy detection IRQ delivery.
*/ staticvoid ux500_busy_timeout_work(struct work_struct *work)
{ struct mmci_host *host = container_of(work, struct mmci_host,
ux500_busy_timeout_work.work); unsignedlong flags;
u32 status;
spin_lock_irqsave(&host->lock, flags);
if (host->cmd) { /* If we are still busy let's tag on a cmd-timeout error. */
status = readl(host->base + MMCISTATUS); if (status & host->variant->busy_detect_flag) {
status |= MCI_CMDTIMEOUT;
dev_err(mmc_dev(host->mmc), "timeout in state %s still busy with CMD%02x\n",
ux500_state_str(host), host->cmd->opcode);
} else {
dev_err(mmc_dev(host->mmc), "timeout in state %s waiting for busy CMD%02x\n",
ux500_state_str(host), host->cmd->opcode);
}
staticint mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
{ /* * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses * from the fifo range should be used
*/ if (status & MCI_RXFIFOHALFFULL) return host->variant->fifohalfsize; elseif (status & MCI_RXDATAAVLBL) return 4;
do { int count = host->get_rx_fifocnt(host, status, host_remain);
if (count > remain)
count = remain;
if (count <= 0) break;
/* * SDIO especially may want to send something that is * not divisible by 4 (as opposed to card sectors * etc). Therefore make sure to always read the last bytes * while only doing full 32-bit reads towards the FIFO.
*/ if (unlikely(count & 0x3)) { if (count < 4) { unsignedchar buf[4];
ioread32_rep(base + MMCIFIFO, buf, 1);
memcpy(ptr, buf, count);
} else {
ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
count &= ~0x3;
}
} else {
ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
}
/* * SDIO especially may want to send something that is * not divisible by 4 (as opposed to card sectors * etc), and the FIFO only accept full 32-bit writes. * So compensate by adding +3 on the count, a single * byte become a 32bit write, 7 bytes will be two * 32bit writes etc.
*/
iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
ptr += count;
remain -= count;
if (remain == 0) break;
status = readl(base + MMCISTATUS);
} while (status & MCI_TXFIFOHALFEMPTY);
/* * For write, we only need to test the half-empty flag * here - if the FIFO is completely empty, then by * definition it is more than half empty. * * For read, check for data available.
*/ if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) break;
len = 0; if (status & MCI_RXACTIVE)
len = mmci_pio_read(host, buffer, remain); if (status & MCI_TXACTIVE)
len = mmci_pio_write(host, buffer, remain, status);
sg_miter->consumed = len;
host->size -= len;
remain -= len;
if (remain) break;
status = readl(base + MMCISTATUS);
} while (1);
sg_miter_stop(sg_miter);
/* * If we have less than the fifo 'half-full' threshold to transfer, * trigger a PIO interrupt as soon as any data is available.
*/ if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
/* * If we run out of data, disable the data IRQs; this * prevents a race where the FIFO becomes empty before * the chip itself has disabled the data path, and * stops us racing with our data end IRQ.
*/ if (host->size == 0) {
mmci_set_mask1(host, 0);
writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
}
do {
status = readl(host->base + MMCISTATUS); if (!status) break;
if (host->singleirq) { if (status & host->mask1_reg)
mmci_pio_irq(irq, dev_id);
status &= ~host->variant->irq_pio_mask;
}
/* * Busy detection is managed by mmci_cmd_irq(), including to * clear the corresponding IRQ.
*/
status &= readl(host->base + MMCIMASK0); if (host->variant->busy_detect)
writel(status & ~host->variant->busy_detect_mask,
host->base + MMCICLEAR); else
writel(status, host->base + MMCICLEAR);
if (host->variant->supports_sdio_irq)
mmci_signal_sdio_irq(host, status);
/* * Busy detection has been handled by mmci_cmd_irq() above. * Clear the status bit to prevent polling in IRQ context.
*/ if (host->variant->busy_detect_flag)
status &= ~host->variant->busy_detect_flag;
} while (status);
spin_unlock(&host->lock);
return host->irq_action;
}
/* * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW. * * A reset is needed for some variants, where a datatimeout for a R1B request * causes the DPSM to stay busy (non-functional).
*/ static irqreturn_t mmci_irq_thread(int irq, void *dev_id)
{ struct mmci_host *host = dev_id; unsignedlong flags;
if (host->rst) {
reset_control_assert(host->rst);
udelay(2);
reset_control_deassert(host->rst);
}
switch (ios->power_mode) { case MMC_POWER_OFF: if (!IS_ERR(mmc->supply.vmmc))
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
regulator_disable(mmc->supply.vqmmc);
host->vqmmc_enabled = false;
}
break; case MMC_POWER_UP: if (!IS_ERR(mmc->supply.vmmc))
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
/* * The ST Micro variant doesn't have the PL180s MCI_PWR_UP * and instead uses MCI_PWR_ON so apply whatever value is * configured in the variant data.
*/
pwr |= variant->pwrreg_powerup;
break; case MMC_POWER_ON: if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
ret = regulator_enable(mmc->supply.vqmmc); if (ret < 0)
dev_err(mmc_dev(mmc), "failed to enable vqmmc regulator\n"); else
host->vqmmc_enabled = true;
}
pwr |= MCI_PWR_ON; break;
}
if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { /* * The ST Micro variant has some additional bits * indicating signal direction for the signals in * the SD/MMC bus and feedback-clock usage.
*/
pwr |= host->pwr_reg_add;
if (variant->opendrain) { if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
pwr |= variant->opendrain;
} else { /* * If the variant cannot configure the pads by its own, then we * expect the pinctrl to be able to do that for us
*/ if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
pinctrl_select_state(host->pinctrl, host->pins_opendrain); else
pinctrl_select_default_state(mmc_dev(mmc));
}
/* * If clock = 0 and the variant requires the MMCIPOWER to be used for * gating the clock, the MCI_PWR_ON bit is cleared.
*/ if (!ios->clock && variant->pwrreg_clkgate)
pwr &= ~MCI_PWR_ON;
if (host->variant->explicit_mclk_control &&
ios->clock != host->clock_cache) {
ret = clk_set_rate(host->clk, ios->clock); if (ret < 0)
dev_err(mmc_dev(host->mmc), "Error setting clock rate (%d)\n", ret); else
host->mclk = clk_get_rate(host->clk);
}
host->clock_cache = ios->clock;
spin_lock_irqsave(&host->lock, flags);
if (host->ops && host->ops->set_clkreg)
host->ops->set_clkreg(host, ios->clock); else
mmci_set_clkreg(host, ios->clock);
mmci_set_max_busy_timeout(mmc);
if (host->ops && host->ops->set_pwrreg)
host->ops->set_pwrreg(host, pwr); else
mmci_write_pwrreg(host, pwr);
/* * Assume the level translator is present if st,use-ckin is set. * This is to cater for DTs which do not implement this test.
*/
host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
cmd_gpio = gpiod_get(dev, "st,cmd", GPIOD_OUT_HIGH); if (IS_ERR(cmd_gpio)) goto exit_cmd;
ck_gpio = gpiod_get(dev, "st,ck", GPIOD_OUT_HIGH); if (IS_ERR(ck_gpio)) goto exit_ck;
ckin_gpio = gpiod_get(dev, "st,ckin", GPIOD_IN); if (IS_ERR(ckin_gpio)) goto exit_ckin;
/* All GPIOs are valid, test whether level translator works */
/* Tristate all */
gpiod_direction_input(cmd_gpio);
gpiod_direction_input(ck_gpio);
/* Level translator is present if CK signal is propagated to CKIN */ if (!clk_hi || clk_lo) {
host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN;
dev_warn(dev, "Level translator inoperable, CK signal not detected on CKIN, disabling.\n");
}
ret = mmci_of_parse(np, mmc); if (ret) return ret;
/* * Some variant (STM32) doesn't have opendrain bit, nevertheless * pins can be set accordingly using pinctrl
*/ if (!variant->opendrain) {
host->pinctrl = devm_pinctrl_get(&dev->dev); if (IS_ERR(host->pinctrl)) return dev_err_probe(&dev->dev, PTR_ERR(host->pinctrl), "failed to get pinctrl\n");
host->clk = devm_clk_get(&dev->dev, NULL); if (IS_ERR(host->clk)) return PTR_ERR(host->clk);
ret = clk_prepare_enable(host->clk); if (ret) return ret;
if (variant->qcom_fifo)
host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; else
host->get_rx_fifocnt = mmci_get_rx_fifocnt;
host->plat = plat;
host->variant = variant;
host->mclk = clk_get_rate(host->clk); /* * According to the spec, mclk is max 100 MHz, * so we try to adjust the clock down to this, * (if possible).
*/ if (host->mclk > variant->f_max) {
ret = clk_set_rate(host->clk, variant->f_max); if (ret < 0) goto clk_disable;
host->mclk = clk_get_rate(host->clk);
dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
host->mclk);
}
host->phybase = dev->res.start;
host->base = devm_ioremap_resource(&dev->dev, &dev->res); if (IS_ERR(host->base)) {
ret = PTR_ERR(host->base); goto clk_disable;
}
if (variant->init)
variant->init(host);
/* * The ARM and ST versions of the block have slightly different * clock divider equations which means that the minimum divider * differs too. * on Qualcomm like controllers get the nearest minimum clock to 100Khz
*/ if (variant->st_clkdiv)
mmc->f_min = DIV_ROUND_UP(host->mclk, 257); elseif (variant->stm32_clkdiv)
mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); elseif (variant->explicit_mclk_control)
mmc->f_min = clk_round_rate(host->clk, 100000); else
mmc->f_min = DIV_ROUND_UP(host->mclk, 512); /* * If no maximum operating frequency is supplied, fall back to use * the module parameter, which has a (low) default value in case it * is not specified. Either value must not exceed the clock rate into * the block, of course.
*/ if (mmc->f_max)
mmc->f_max = variant->explicit_mclk_control ?
min(variant->f_max, mmc->f_max) :
min(host->mclk, mmc->f_max); else
mmc->f_max = variant->explicit_mclk_control ?
fmax : min(host->mclk, fmax);
dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); if (IS_ERR(host->rst)) {
ret = PTR_ERR(host->rst); goto clk_disable;
}
ret = reset_control_deassert(host->rst); if (ret)
dev_err(mmc_dev(mmc), "failed to de-assert reset\n");
/* Get regulators and the supported OCR mask */
ret = mmc_regulator_get_supply(mmc); if (ret) goto clk_disable;
if (!mmc->ocr_avail)
mmc->ocr_avail = plat->ocr_mask; elseif (plat->ocr_mask)
dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
/* We support these capabilities. */
mmc->caps |= MMC_CAP_CMD23;
/* * Enable busy detection.
*/ if (variant->busy_detect) {
mmci_ops.card_busy = mmci_card_busy; /* * Not all variants have a flag to enable busy detection * in the DPSM, but if they do, set it here.
*/ if (variant->busy_dpsm_flag)
mmci_write_datactrlreg(host,
host->variant->busy_dpsm_flag);
mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
}
if (variant->supports_sdio_irq && host->mmc->caps & MMC_CAP_SDIO_IRQ) {
mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
/* Variants with mandatory busy timeout in HW needs R1B responses. */ if (variant->busy_timeout)
mmc->caps |= MMC_CAP_NEED_RSP_BUSY;
/* Prepare a CMD12 - needed to clear the DPSM on some variants. */
host->stop_abort.opcode = MMC_STOP_TRANSMISSION;
host->stop_abort.arg = 0;
host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC;
/* We support these PM capabilities. */
mmc->pm_caps |= MMC_PM_KEEP_POWER;
/* * We can do SGIO
*/
mmc->max_segs = NR_SG;
/* * Since only a certain number of bits are valid in the data length * register, we must ensure that we don't exceed 2^num-1 bytes in a * single request.
*/
mmc->max_req_size = (1 << variant->datalength_bits) - 1;
/* * Set the maximum segment size. Since we aren't doing DMA * (yet) we are only limited by the data length register.
*/
mmc->max_seg_size = mmc->max_req_size;
/* * Block size can be up to 2048 bytes, but must be a power of two.
*/
mmc->max_blk_size = 1 << variant->datactrl_blocksz;
/* * Limit the number of blocks transferred so that we don't overflow * the maximum request size.
*/
mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz;
spin_lock_init(&host->lock);
writel(0, host->base + MMCIMASK0);
if (variant->mmcimask1)
writel(0, host->base + MMCIMASK1);
writel(0xfff, host->base + MMCICLEAR);
/* * If: * - not using DT but using a descriptor table, or * - using a table of descriptors ALONGSIDE DT, or * look up these descriptors named "cd" and "wp" right here, fail * silently of these do not exist
*/ if (!np) {
ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0); if (ret == -EPROBE_DEFER) goto clk_disable;
ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0); if (ret == -EPROBE_DEFER) goto clk_disable;
}
ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq,
mmci_irq_thread, IRQF_SHARED,
DRIVER_NAME " (cmd)", host); if (ret) goto clk_disable;
if (!dev->irq[1])
host->singleirq = true; else {
ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
IRQF_SHARED, DRIVER_NAME " (pio)", host); if (ret) goto clk_disable;
}
if (host->variant->busy_detect)
INIT_DELAYED_WORK(&host->ux500_busy_timeout_work,
ux500_busy_timeout_work);
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