/* * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, * but bit28 is used as the INT DMA ERR in fsl eSDHC design. * Define this macro DMA error INT for fsl eSDHC
*/ #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
/* the address offset of CQHCI */ #define ESDHC_CQHCI_ADDR_OFFSET 0x100
/* * The CMDTYPE of the CMD register (offset 0xE) should be set to * "11" when the STOP CMD12 is issued on imx53 to abort one * open ended multi-blk IO. Otherwise the TC INT wouldn't * be generated. * In exact block transfer, the controller doesn't complete the * operations automatically as required at the end of the * transfer and remains on hold if the abort command is not sent. * As a result, the TC flag is not asserted and SW received timeout * exception. Bit1 of Vendor Spec register is used to fix it.
*/ #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) /* * The flag tells that the ESDHC controller is an USDHC block that is * integrated on the i.MX6 series.
*/ #define ESDHC_FLAG_USDHC BIT(3) /* The IP supports manual tuning process */ #define ESDHC_FLAG_MAN_TUNING BIT(4) /* The IP supports standard tuning process */ #define ESDHC_FLAG_STD_TUNING BIT(5) /* The IP has SDHCI_CAPABILITIES_1 register */ #define ESDHC_FLAG_HAVE_CAP1 BIT(6) /* * The IP has erratum ERR004536 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, * when reading data from the card * This flag is also set for i.MX25 and i.MX35 in order to get * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits).
*/ #define ESDHC_FLAG_ERR004536 BIT(7) /* The IP supports HS200 mode */ #define ESDHC_FLAG_HS200 BIT(8) /* The IP supports HS400 mode */ #define ESDHC_FLAG_HS400 BIT(9) /* * The IP has errata ERR010450 * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz.
*/ #define ESDHC_FLAG_ERR010450 BIT(10) /* The IP supports HS400ES mode */ #define ESDHC_FLAG_HS400_ES BIT(11) /* The IP has Host Controller Interface for Command Queuing */ #define ESDHC_FLAG_CQHCI BIT(12) /* need request pmqos during low power */ #define ESDHC_FLAG_PMQOS BIT(13) /* The IP state got lost in low power mode */ #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14) /* The IP lost clock rate in PM_RUNTIME */ #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15) /* * The IP do not support the ACMD23 feature completely when use ADMA mode. * In ADMA mode, it only use the 16 bit block count of the register 0x4 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will * ignore the upper 16 bit of the CMD23's argument. This will block the reliable * write operation in RPMB, because RPMB reliable write need to set the bit31 * of the CMD23's argument. * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA * do not has this limitation. so when these SoC use ADMA mode, it need to * disable the ACMD23 feature.
*/ #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16)
/* ERR004536 is not applicable for the IP */ #define ESDHC_FLAG_SKIP_ERR004536 BIT(17)
/* The IP does not have GPIO CD wake capabilities */ #define ESDHC_FLAG_SKIP_CD_WAKE BIT(18)
/* the controller has dummy pad for clock loopback */ #define ESDHC_FLAG_DUMMY_PAD BIT(19)
#define ESDHC_AUTO_TUNING_WINDOW 3
enum wp_types {
ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
ESDHC_WP_GPIO, /* external gpio pin for WP */
};
enum cd_types {
ESDHC_CD_NONE, /* no CD, neither controller nor gpio */
ESDHC_CD_CONTROLLER, /* mmc controller internal CD */
ESDHC_CD_GPIO, /* external gpio pin for CD */
ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */
};
/* * struct esdhc_platform_data - platform data for esdhc on i.MX * * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35. * * @wp_type: type of write_protect method (see wp_types enum above) * @cd_type: type of card_detect method (see cd_types enum above)
*/
struct esdhc_platform_data { enum wp_types wp_type; enum cd_types cd_type; int max_bus_width; unsignedint delay_line; unsignedint tuning_step; /* The delay cell steps in tuning procedure */ unsignedint tuning_start_tap; /* The start delay cell point in tuning procedure */ unsignedint strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ unsignedint saved_tuning_delay_cell; /* save the value of tuning delay cell */ unsignedint saved_auto_tuning_window; /* save the auto tuning window width */
};
/* * USDHC has one limition, require the SDIO device a different * register setting. Driver has to recognize card type during * the card init, but at this stage, mmc_host->card is not * available. So involve this field to save the card type * during card init through usdhc_init_card().
*/ unsignedint init_card_type;
enum {
NO_CMD_PENDING, /* no multiblock command pending */
MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
WAIT_FOR_INT, /* sent CMD12, waiting for response INT */
} multiblock_status;
u32 is_ddr; struct pm_qos_request pm_qos_req;
};
staticinlinevoid esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host)
{
u32 present_state; int ret;
ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state,
(present_state & ESDHC_CLOCK_GATE_OFF), 2, 100); if (ret == -ETIMEDOUT)
dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__);
}
/* Enable the auto tuning circuit to check the CMD line and BUS line */ staticinlinevoid usdhc_auto_tuning_mode_sel_and_en(struct sdhci_host *host)
{ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
u32 buswidth, auto_tune_buswidth;
u32 reg;
/* * For USDHC, auto tuning circuit can not handle the async sdio * device interrupt correctly. When sdio device use 4 data lines, * async sdio interrupt will use the shared DAT[1], if enable auto * tuning circuit check these 4 data lines, include the DAT[1], * this circuit will detect this interrupt, take this as a data on * DAT[1], and adjust the delay cell wrongly. * This is the hardware design limitation, to avoid this, for sdio * device, config the auto tuning circuit only check DAT[0] and CMD * line.
*/ if (imx_data->init_card_type == MMC_TYPE_SDIO)
auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
if (unlikely(reg == SDHCI_PRESENT_STATE)) {
u32 fsl_prss = val; /* save the least 20 bits */
val = fsl_prss & 0x000FFFFF; /* move dat[0-3] bits */
val |= (fsl_prss & 0x0F000000) >> 4; /* move cmd line bit */
val |= (fsl_prss & 0x00800000) << 1;
}
if (unlikely(reg == SDHCI_CAPABILITIES)) { /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
val &= 0xffff0000;
/* In FSL esdhc IC module, only bit20 is used to indicate the * ADMA2 capability of esdhc, but this bit is messed up on * some SOCs (e.g. on MX25, MX35 this bit is set, but they * don't actually support ADMA2). So set the BROKEN_ADMA * quirk on MX25/35 platforms.
*/
if (val & SDHCI_CAN_DO_ADMA1) {
val &= ~SDHCI_CAN_DO_ADMA1;
val |= SDHCI_CAN_DO_ADMA2;
}
}
if (unlikely(reg == SDHCI_CAPABILITIES_1)) { if (esdhc_is_usdhc(imx_data)) { if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; else /* imx6q/dl does not have cap_1 register, fake one */
val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
| SDHCI_USE_SDR50_TUNING
| FIELD_PREP(SDHCI_RETUNING_MODE_MASK,
SDHCI_TUNING_MODE_3);
/* * Do not advertise faster UHS modes if there are no * pinctrl states for 100MHz/200MHz.
*/ if (IS_ERR_OR_NULL(imx_data->pins_100mhz))
val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); if (IS_ERR_OR_NULL(imx_data->pins_200mhz))
val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400);
}
}
if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
val = 0;
val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF);
val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF);
val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF);
}
if (unlikely(reg == SDHCI_INT_STATUS)) { if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
val |= SDHCI_INT_ADMA_ERROR;
}
/* * mask off the interrupt we get in response to the manually * sent CMD12
*/ if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
val &= ~SDHCI_INT_RESPONSE;
writel(SDHCI_INT_RESPONSE, host->ioaddr +
SDHCI_INT_STATUS);
imx_data->multiblock_status = NO_CMD_PENDING;
}
}
if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE ||
reg == SDHCI_INT_STATUS)) { if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { /* * Clear and then set D3CD bit to avoid missing the * card interrupt. This is an eSDHC controller problem * so we need to apply the following workaround: clear * and set D3CD bit will make eSDHC re-sample the card * interrupt. In case a card interrupt was lost, * re-sample it by the following steps.
*/
data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
data &= ~ESDHC_CTRL_D3CD;
writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
data |= ESDHC_CTRL_D3CD;
writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
}
if (val & SDHCI_INT_ADMA_ERROR) {
val &= ~SDHCI_INT_ADMA_ERROR;
val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
}
}
if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
&& (reg == SDHCI_INT_STATUS)
&& (val & SDHCI_INT_DATA_END))) {
u32 v;
v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
{ /* send a manual CMD12 with RESPTYP=none */
data = MMC_STOP_TRANSMISSION << 24 |
SDHCI_CMD_ABORTCMD << 16;
writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
imx_data->multiblock_status = WAIT_FOR_INT;
}
}
if (unlikely(reg == SDHCI_HOST_VERSION)) {
reg ^= 2; if (esdhc_is_usdhc(imx_data)) { /* * The usdhc register returns a wrong host version. * Correct it here.
*/ return SDHCI_SPEC_300;
}
}
if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); if (val & ESDHC_VENDOR_SPEC_VSELECT)
ret |= SDHCI_CTRL_VDD_180;
if (esdhc_is_usdhc(imx_data)) { if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
val = readl(host->ioaddr + ESDHC_MIX_CTRL); elseif (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) /* the std tuning bits is in ACMD12_ERR for imx6sl */
val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
}
if (val & ESDHC_MIX_CTRL_EXE_TUNE)
ret |= SDHCI_CTRL_EXEC_TUNING; if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
ret |= SDHCI_CTRL_TUNED_CLK;
ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
return ret;
}
if (unlikely(reg == SDHCI_TRANSFER_MODE)) { if (esdhc_is_usdhc(imx_data)) {
u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; /* Swap AC23 bit */ if (m & ESDHC_MIX_CTRL_AC23EN) {
ret &= ~ESDHC_MIX_CTRL_AC23EN;
ret |= SDHCI_TRNS_AUTO_CMD23;
}
} else {
ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
}
switch (reg) { case SDHCI_CLOCK_CONTROL:
new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); if (val & SDHCI_CLOCK_CARD_EN)
new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; else
new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON))
esdhc_wait_for_card_clock_gate_off(host); return; case SDHCI_HOST_CONTROL2:
new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); if (val & SDHCI_CTRL_VDD_180)
new_val |= ESDHC_VENDOR_SPEC_VSELECT; else
new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); if (val & SDHCI_CTRL_TUNED_CLK)
v |= ESDHC_MIX_CTRL_SMPCLK_SEL; else
v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
if (val & SDHCI_CTRL_EXEC_TUNING)
v |= ESDHC_MIX_CTRL_EXE_TUNE; else
v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
} return; case SDHCI_TRANSFER_MODE: if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
&& (host->cmd->data->blocks > 1)
&& (host->cmd->data->flags & MMC_DATA_READ)) {
u32 v;
v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
}
if (esdhc_is_usdhc(imx_data)) {
u32 wml;
u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); /* Swap AC23 bit */ if (val & SDHCI_TRNS_AUTO_CMD23) {
val &= ~SDHCI_TRNS_AUTO_CMD23;
val |= ESDHC_MIX_CTRL_AC23EN;
}
m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
writel(m, host->ioaddr + ESDHC_MIX_CTRL);
/* Set watermark levels for PIO access to maximum value * (128 words) to accommodate full 512 bytes buffer. * For DMA access restore the levels to default value.
*/
m = readl(host->ioaddr + ESDHC_WTMK_LVL); if (val & SDHCI_TRNS_DMA) {
wml = ESDHC_WTMK_LVL_WML_VAL_DEF;
} else {
u8 ctrl;
wml = ESDHC_WTMK_LVL_WML_VAL_MAX;
/* * Since already disable DMA mode, so also need * to clear the DMASEL. Otherwise, for standard * tuning, when send tuning command, usdhc will * still prefetch the ADMA script from wrong * DMA address, then we will see IOMMU report * some error which show lack of TLB mapping.
*/
ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
ctrl &= ~SDHCI_CTRL_DMA_MASK;
sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
}
m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK |
ESDHC_WTMK_LVL_WR_WML_MASK);
m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) |
(wml << ESDHC_WTMK_LVL_WR_WML_SHIFT);
writel(m, host->ioaddr + ESDHC_WTMK_LVL);
} else { /* * Postpone this write, we must do it together with a * command write that is down below.
*/
imx_data->scratchpad = val;
} return; case SDHCI_COMMAND: if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
val |= SDHCI_CMD_ABORTCMD;
switch (reg) { case SDHCI_POWER_CONTROL: /* * FSL put some DMA bits here * If your board has a regulator, code should be here
*/ return; case SDHCI_HOST_CONTROL: /* FSL messed up here, so we need to manually compose it. */
new_val = val & SDHCI_CTRL_LED; /* ensure the endianness */
new_val |= ESDHC_HOST_CONTROL_LE; /* bits 8&9 are reserved on mx25 */ if (!is_imx25_esdhc(imx_data)) { /* DMA mode bits are shifted */
new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
}
/* * Do not touch buswidth bits here. This is done in * esdhc_pltfm_bus_width. * Do not touch the D3CD bit either which is used for the * SDIO interrupt erratum workaround.
*/
mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
esdhc_clrset_le(host, mask, new_val, reg); return; case SDHCI_TIMEOUT_CONTROL:
esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK,
FIELD_PREP(ESDHC_SYS_CTRL_DTOCV_MASK, val),
ESDHC_SYSTEM_CONTROL); return; case SDHCI_SOFTWARE_RESET: if (val & SDHCI_RESET_DATA)
new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); break;
}
esdhc_clrset_le(host, 0xff, val, reg);
if (reg == SDHCI_SOFTWARE_RESET) { if (val & SDHCI_RESET_ALL) { /* * The esdhc has a design violation to SDHC spec which * tells that software reset should not affect card * detection circuit. But esdhc clears its SYSCTL * register bits [0..2] during the software reset. This * will stop those clocks that card detection circuit * relies on. To work around it, we turn the clocks on * back to keep card detection circuit functional.
*/
esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); /* * The reset on usdhc fails to clear MIX_CTRL register. * Do it manually here.
*/ if (esdhc_is_usdhc(imx_data)) { /* * the tuning bits should be kept during reset
*/
new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
host->ioaddr + ESDHC_MIX_CTRL);
imx_data->is_ddr = 0;
}
} elseif (val & SDHCI_RESET_DATA) { /* * The eSDHC DAT line software reset clears at least the * data transfer width on i.MX25, so make sure that the * Host Control register is unaffected.
*/
esdhc_clrset_le(host, 0xff, new_val,
SDHCI_HOST_CONTROL);
}
}
}
staticinlinevoid esdhc_pltfm_set_clock(struct sdhci_host *host, unsignedint clock)
{ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); unsignedint host_clock = pltfm_host->clock; int ddr_pre_div = imx_data->is_ddr ? 2 : 1; int pre_div = 1; int div = 1; int ret;
u32 temp, val;
if (esdhc_is_usdhc(imx_data)) {
val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
host->ioaddr + ESDHC_VENDOR_SPEC);
esdhc_wait_for_card_clock_gate_off(host);
}
if (clock == 0) {
host->mmc->actual_clock = 0; return;
}
/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ if (is_imx53_esdhc(imx_data)) { /* * According to the i.MX53 reference manual, if DLLCTRL[10] can * be set, then the controller is eSDHCv3, else it is eSDHCv2.
*/
val = readl(host->ioaddr + ESDHC_DLL_CTRL);
writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL);
temp = readl(host->ioaddr + ESDHC_DLL_CTRL);
writel(val, host->ioaddr + ESDHC_DLL_CTRL); if (temp & BIT(10))
pre_div = 2;
}
/* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */
ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp,
(temp & ESDHC_CLOCK_STABLE), 2, 100); if (ret == -ETIMEDOUT)
dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n");
if (esdhc_is_usdhc(imx_data)) {
val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
host->ioaddr + ESDHC_VENDOR_SPEC);
}
/* Reset the tuning circuit */ if (esdhc_is_usdhc(imx_data)) {
ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL);
ctrl &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
} elseif (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); /* * enable the std tuning just in case it cleared in * sdhc_esdhc_tuning_restore.
*/
tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL); if (!(tuning_ctrl & ESDHC_STD_TUNING_EN)) {
tuning_ctrl |= ESDHC_STD_TUNING_EN;
writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL);
}
/* set the reset tuning bit */
sys_ctrl = readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
sys_ctrl |= ESDHC_SYS_CTRL_RESET_TUNING;
writel(sys_ctrl, host->ioaddr + ESDHC_SYSTEM_CONTROL);
ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE;
writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */
ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS,
ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); if (ret == -ETIMEDOUT)
dev_warn(mmc_dev(host->mmc), "Warning! clear execute tuning bit failed\n"); /* * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the * usdhc IP internal logic flag execute_tuning_with_clr_buf, which * will finally make sure the normal data transfer logic correct.
*/
ctrl = readl(host->ioaddr + SDHCI_INT_STATUS);
ctrl |= SDHCI_INT_DATA_AVAIL;
writel(ctrl, host->ioaddr + SDHCI_INT_STATUS);
}
}
}
/* * i.MX uSDHC internally already uses a fixed optimized timing for * DDR50, normally does not require tuning for DDR50 mode.
*/ if (host->timing == MMC_TIMING_UHS_DDR50) return 0;
/* * Reset tuning circuit logic. If not, the previous tuning result * will impact current tuning, make current tuning can't set the * correct delay cell.
*/
esdhc_reset_tuning(host);
err = sdhci_execute_tuning(mmc, opcode); /* If tuning done, enable auto tuning */ if (!err && !host->tuning_err)
usdhc_auto_tuning_mode_sel_and_en(host);
/* FIXME: delay a bit for card to be ready for next tuning due to errors */
mdelay(1);
/* IC suggest to reset USDHC before every tuning command */
esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET);
ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst,
!(sw_rst & SDHCI_RESET_ALL), 10, 100); if (ret == -ETIMEDOUT)
dev_warn(mmc_dev(host->mmc), "warning! RESET_ALL never complete before sending tuning command\n");
/* set RST_FIFO to reset the async FIFO, and wat it to self-clear */
sys_ctrl = readl(host->ioaddr + ESDHC_SYSTEM_CONTROL);
sys_ctrl |= ESDHC_SYS_CTRL_RST_FIFO;
writel(sys_ctrl, host->ioaddr + ESDHC_SYSTEM_CONTROL);
ret = readl_poll_timeout(host->ioaddr + ESDHC_SYSTEM_CONTROL, sys_ctrl,
!(sys_ctrl & ESDHC_SYS_CTRL_RST_FIFO), 10, 100); if (ret == -ETIMEDOUT)
dev_warn(mmc_dev(host->mmc), "warning! RST_FIFO not clear in 100us\n");
}
/* * find the largest pass window, and use the average delay of this * largest window to get the best timing.
*/ staticint esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
{ int min, max, avg, ret; int win_length, target_min, target_max, target_win_length;
u32 clk_tune_ctrl_status, temp;
min = target_min = ESDHC_TUNE_CTRL_MIN;
max = target_max = ESDHC_TUNE_CTRL_MIN;
target_win_length = 0; while (max < ESDHC_TUNE_CTRL_MAX) { /* find the mininum delay first which can pass tuning */ while (min < ESDHC_TUNE_CTRL_MAX) {
esdhc_prepare_tuning(host, min); if (!mmc_send_tuning(host->mmc, opcode, NULL)) break;
min += ESDHC_TUNE_CTRL_STEP;
}
/* find the maxinum delay which can not pass tuning */
max = min + ESDHC_TUNE_CTRL_STEP; while (max < ESDHC_TUNE_CTRL_MAX) {
esdhc_prepare_tuning(host, max); if (mmc_send_tuning(host->mmc, opcode, NULL)) {
max -= ESDHC_TUNE_CTRL_STEP; break;
}
max += ESDHC_TUNE_CTRL_STEP;
}
win_length = max - min + 1; /* get the largest pass window */ if (win_length > target_win_length) {
target_win_length = win_length;
target_min = min;
target_max = max;
}
/* continue to find the next pass window */
min = max + ESDHC_TUNE_CTRL_STEP;
}
/* use average delay to get the best timing */
avg = (target_min + target_max) / 2;
esdhc_prepare_tuning(host, avg);
/* * adjust the delay according to tuning window, make preparation * for the auto-tuning logic. According to hardware suggest, need * to config the auto tuning window width to 3, to make the auto * tuning logic have enough space to handle the sample point shift * caused by temperature change.
*/
clk_tune_ctrl_status = FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK,
avg - ESDHC_AUTO_TUNING_WINDOW) |
FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK,
ESDHC_AUTO_TUNING_WINDOW) |
FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK,
ESDHC_AUTO_TUNING_WINDOW);
writel(clk_tune_ctrl_status, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
ret = readl_poll_timeout(host->ioaddr + ESDHC_TUNE_CTRL_STATUS, temp,
clk_tune_ctrl_status ==
FIELD_GET(ESDHC_TUNE_CTRL_STATUS_TAP_SEL_MASK, temp),
1, 10); if (ret == -ETIMEDOUT)
dev_warn(mmc_dev(host->mmc), "clock tuning control status not set in 10us\n");
ret = mmc_send_tuning(host->mmc, opcode, NULL);
esdhc_post_tuning(host);
dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n",
ret ? "failed" : "passed", avg, ret);
m = readl(host->ioaddr + ESDHC_MIX_CTRL); if (ios->enhanced_strobe)
m |= ESDHC_MIX_CTRL_HS400_ES_EN; else
m &= ~ESDHC_MIX_CTRL_HS400_ES_EN;
writel(m, host->ioaddr + ESDHC_MIX_CTRL);
}
dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
if (IS_ERR(imx_data->pinctrl) ||
IS_ERR(imx_data->pins_100mhz) ||
IS_ERR(imx_data->pins_200mhz)) return -EINVAL;
switch (uhs) { case MMC_TIMING_UHS_SDR50: case MMC_TIMING_UHS_DDR50:
pinctrl = imx_data->pins_100mhz; break; case MMC_TIMING_UHS_SDR104: case MMC_TIMING_MMC_HS200: case MMC_TIMING_MMC_HS400:
pinctrl = imx_data->pins_200mhz; break; default: /* back to default state for other legacy timing */ return pinctrl_select_default_state(mmc_dev(host->mmc));
}
/* * For HS400 eMMC, there is a data_strobe line. This signal is generated * by the device and used for data output and CRC status response output * in HS400 mode. The frequency of this signal follows the frequency of * CLK generated by host. The host receives the data which is aligned to the * edge of data_strobe line. Due to the time delay between CLK line and * data_strobe line, if the delay time is larger than one clock cycle, * then CLK and data_strobe line will be misaligned, read error shows up.
*/ staticvoid esdhc_set_strobe_dll(struct sdhci_host *host)
{ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host);
u32 strobe_delay;
u32 v; int ret;
/* force a reset on strobe dll */
writel(ESDHC_STROBE_DLL_CTRL_RESET,
host->ioaddr + ESDHC_STROBE_DLL_CTRL); /* clear the reset bit on strobe dll before any setting */
writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
/* * enable strobe dll ctrl and adjust the delay target * for the uSDHC loopback read clock
*/ if (imx_data->boarddata.strobe_dll_delay_target)
strobe_delay = imx_data->boarddata.strobe_dll_delay_target; else
strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT;
v = ESDHC_STROBE_DLL_CTRL_ENABLE |
ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT |
(strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
/* wait max 50us to get the REF/SLV lock */
ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v,
((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50); if (ret == -ETIMEDOUT)
dev_warn(mmc_dev(host->mmc), "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v);
}
if (esdhc_is_usdhc(imx_data)) { /* * The imx6q ROM code will change the default watermark * level setting to something insane. Change it back here.
*/
writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL);
/* * ROM code will change the bit burst_length_enable setting * to zero if this usdhc is chosen to boot system. Change * it back here, otherwise it will impact the performance a * lot. This bit is used to enable/disable the burst length * for the external AHB2AXI bridge. It's useful especially * for INCR transfer because without burst length indicator, * the AHB2AXI bridge does not know the burst length in * advance. And without burst length indicator, AHB INCR * transfer can only be converted to singles on the AXI side.
*/
writel(readl(host->ioaddr + SDHCI_HOST_CONTROL)
| ESDHC_BURST_LEN_EN_INCR,
host->ioaddr + SDHCI_HOST_CONTROL);
/* * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL * TO1.1, it's harmless for MX6SL
*/ if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) {
writel(readl(host->ioaddr + 0x6c) & ~BIT(7),
host->ioaddr + 0x6c);
}
/* * For the case of command with busy, if set the bit * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a * transfer complete interrupt when busy is deasserted. * When CQHCI use DCMD to send a CMD need R1b respons, * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, * otherwise DCMD will always meet timeout waiting for * hardware interrupt issue.
*/ if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) {
tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2);
tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ;
writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2);
/* * ROM code or bootloader may config the start tap * and step, unmask them first.
*/
tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK); if (imx_data->boarddata.tuning_start_tap)
tmp |= imx_data->boarddata.tuning_start_tap; else
tmp |= ESDHC_TUNING_START_TAP_DEFAULT;
/* * Config the tuning window to the hardware suggested value 3. * This tuning window is used for auto tuning logic. The default * tuning window is 2, here change to 3 make the window a bit * wider, give auto tuning enough space to handle the sample * point shift cause by temperature change.
*/
tmp &= ~ESDHC_TUNING_WINDOW_MASK;
tmp |= FIELD_PREP(ESDHC_TUNING_WINDOW_MASK, ESDHC_AUTO_TUNING_WINDOW);
/* Disable the CMD CRC check for tuning, if not, need to * add some delay after every tuning command, because * hardware standard tuning logic will directly go to next * step once it detect the CMD CRC error, will not wait for * the card side to finally send out the tuning data, trigger * the buffer read ready interrupt immediately. If usdhc send * the next tuning command some eMMC card will stuck, can't * response, block the tuning procedure or the first command * after the whole tuning procedure always can't get any response.
*/
tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
} elseif (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { /* * ESDHC_STD_TUNING_EN may be configured in bootloader * or ROM code, so clear this bit here to make sure * the manual tuning can work.
*/
tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL);
tmp &= ~ESDHC_STD_TUNING_EN;
writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL);
}
/* * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let * the 1st linux configure power/clock for the 2nd Linux. * * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump. * After we clear the pending interrupt and halt CQCTL, issue gone.
*/ if (cq_host) {
tmp = cqhci_readl(cq_host, CQHCI_IS);
cqhci_writel(cq_host, tmp, CQHCI_IS);
cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL);
}
}
}
/* * SD/eMMC do not need this tuning save because it will re-init * after system resume back. * Here save the tuning delay value for SDIO device since it may * keep power during system PM. And for usdhc, only SDR50 and * SDR104 mode for SDIO device need to do tuning, and need to * save/restore.
*/ if (host->timing == MMC_TIMING_UHS_SDR50 ||
host->timing == MMC_TIMING_UHS_SDR104) {
reg = readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
reg = FIELD_GET(ESDHC_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK, reg);
imx_data->boarddata.saved_tuning_delay_cell = reg;
}
}
if (host->timing == MMC_TIMING_UHS_SDR50 ||
host->timing == MMC_TIMING_UHS_SDR104) { /* * restore the tuning delay value actually is a * manual tuning method, so clear the standard * tuning enable bit here. Will set back this * ESDHC_STD_TUNING_EN in esdhc_reset_tuning() * when trigger re-tuning.
*/
reg = readl(host->ioaddr + ESDHC_TUNING_CTRL);
reg &= ~ESDHC_STD_TUNING_EN;
writel(reg, host->ioaddr + ESDHC_TUNING_CTRL);
/* * CQE gets stuck if it sees Buffer Read Enable bit set, which can be * the case after tuning, so ensure the buffer is drained.
*/
reg = sdhci_readl(host, SDHCI_PRESENT_STATE); while (reg & SDHCI_DATA_AVAILABLE) {
sdhci_readl(host, SDHCI_BUFFER);
reg = sdhci_readl(host, SDHCI_PRESENT_STATE); if (count-- == 0) {
dev_warn(mmc_dev(host->mmc), "CQE may get stuck because the Buffer Read Enable bit is set\n"); break;
}
mdelay(1);
}
/* * Runtime resume will reset the entire host controller, which * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. * Here set DMAEN and BCEN when enable CMDQ.
*/
mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); if (host->flags & SDHCI_REQ_USE_DMA)
mode |= SDHCI_TRNS_DMA; if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
mode |= SDHCI_TRNS_BLK_CNT_EN;
sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
/* * Though Runtime resume reset the entire host controller, * but do not impact the CQHCI side, need to clear the * HALT bit, avoid CQHCI stuck in the first request when * system resume back.
*/
cqhci_writel(cq_host, 0, CQHCI_CTL); if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT)
dev_err(mmc_dev(host->mmc), "failed to exit halt state when enable CQE\n");
if (of_property_read_bool(np, "fsl,wp-controller"))
boarddata->wp_type = ESDHC_WP_CONTROLLER;
/* * If we have this property, then activate WP check. * Retrieving and requesting the actual WP GPIO will happen * in the call to mmc_of_parse().
*/ if (of_property_present(np, "wp-gpios"))
boarddata->wp_type = ESDHC_WP_GPIO;
/* GPIO CD can be set as a wakeup source */ if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_CD_WAKE))
host->mmc->caps |= MMC_CAP_CD_WAKE;
if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200))
host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
/* clear tuning bits in case ROM has set it already */
writel(0x0, host->ioaddr + ESDHC_MIX_CTRL);
writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
/* * Link usdhc specific mmc_host_ops execute_tuning function, * to replace the standard one in sdhci_ops.
*/
host->mmc_host_ops.execute_tuning = usdhc_execute_tuning;
/* * Link usdhc specific mmc_host_ops init card function, * to distinguish the card type.
*/
host->mmc_host_ops.init_card = usdhc_init_card;
host->max_timeout_count = 0xF;
}
if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
sdhci_esdhc_ops.platform_execute_tuning =
esdhc_executing_tuning;
if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
host->mmc->caps2 |= MMC_CAP2_HS400;
if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23)
host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN;
err = cqhci_init(cq_host, host->mmc, false); if (err) goto disable_ahb_clk;
}
err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); if (err) goto disable_ahb_clk;
sdhci_esdhc_imx_hwinit(host);
err = sdhci_add_host(host); if (err) goto disable_ahb_clk;
/* * Setup the wakeup capability here, let user to decide * whether need to enable this wakeup through sysfs interface.
*/ if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) &&
(host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ))
device_set_wakeup_capable(&pdev->dev, true);
/* * Switch to runtime resume for two reasons: * 1, there is register access (e.g., wakeup control register), so * need to make sure gate on ipg clock. * 2, make sure the pm_runtime_force_resume() in sdhci_esdhc_resume() really * invoke its ->runtime_resume callback (needs_force_resume = 1).
*/
pm_runtime_get_sync(dev);
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