// SPDX-License-Identifier: GPL-2.0-only /* * PMC551 PCI Mezzanine Ram Device * * Author: * Mark Ferrell <mferrell@mvista.com> * Copyright 1999,2000 Nortel Networks * * Description: * This driver is intended to support the PMC551 PCI Ram device * from Ramix Inc. The PMC551 is a PMC Mezzanine module for * cPCI embedded systems. The device contains a single SROM * that initially programs the V370PDC chipset onboard the * device, and various banks of DRAM/SDRAM onboard. This driver * implements this PCI Ram device as an MTD (Memory Technology * Device) so that it can be used to hold a file system, or for * added swap space in embedded systems. Since the memory on * this board isn't as fast as main memory we do not try to hook * it into main memory as that would simply reduce performance * on the system. Using it as a block device allows us to use * it as high speed swap or for a high speed disk device of some * sort. Which becomes very useful on diskless systems in the * embedded market I might add. * * Notes: * Due to what I assume is more buggy SROM, the 64M PMC551 I * have available claims that all 4 of its DRAM banks have 64MiB * of ram configured (making a grand total of 256MiB onboard). * This is slightly annoying since the BAR0 size reflects the * aperture size, not the dram size, and the V370PDC supplies no * other method for memory size discovery. This problem is * mostly only relevant when compiled as a module, as the * unloading of the module with an aperture size smaller than * the ram will cause the driver to detect the onboard memory * size to be equal to the aperture size when the module is * reloaded. Soooo, to help, the module supports an msize * option to allow the specification of the onboard memory, and * an asize option, to allow the specification of the aperture * size. The aperture must be equal to or less then the memory * size, the driver will correct this if you screw it up. This * problem is not relevant for compiled in drivers as compiled * in drivers only init once. * * Credits: * Saeed Karamooz <saeed@ramix.com> of Ramix INC. for the * initial example code of how to initialize this device and for * help with questions I had concerning operation of the device. * * Most of the MTD code for this driver was originally written * for the slram.o module in the MTD drivers package which * allows the mapping of system memory into an MTD device. * Since the PMC551 memory module is accessed in the same * fashion as system memory, the slram.c code became a very nice * fit to the needs of this driver. All we added was PCI * detection/initialization to the driver and automatically figure * out the size via the PCI detection.o, later changes by Corey * Minyard set up the card to utilize a 1M sliding apature. * * Corey Minyard <minyard@nortelnetworks.com> * * Modified driver to utilize a sliding aperture instead of * mapping all memory into kernel space which turned out to * be very wasteful. * * Located a bug in the SROM's initialization sequence that * made the memory unusable, added a fix to code to touch up * the DRAM some. * * Bugs/FIXMEs: * * MUST fix the init function to not spin on a register * waiting for it to set .. this does not safely handle busted * devices that never reset the register correctly which will * cause the system to hang w/ a reboot being the only chance at * recover. [sort of fixed, could be better] * * Add I2C handling of the SROM so we can read the SROM's information * about the aperture size. This should always accurately reflect the * onboard memory size. * * Comb the init routine. It's still a bit cludgy on a few things.
*/
if (soff_hi == eoff_hi || mtd->size == priv->asize) { /* The whole thing fits within one access, so just one shot
will do it. */
memset(ptr, 0xff, instr->len);
} else { /* We have to do multiple writes to get all the data
written. */ while (soff_hi != eoff_hi) { #ifdef CONFIG_MTD_PMC551_DEBUG
printk(KERN_DEBUG "pmc551_erase() soff_hi: %ld, " "eoff_hi: %ld\n", (long)soff_hi, (long)eoff_hi); #endif
memset(ptr, 0xff, priv->asize); if (soff_hi + priv->asize >= mtd->size) { goto out;
}
soff_hi += priv->asize;
pmc551_point(mtd, (priv->base_map0 | soff_hi),
priv->asize, &retlen,
(void **)&ptr, NULL);
}
memset(ptr, 0xff, eoff_lo);
}
if (soff_hi == eoff_hi) { /* The whole thing fits within one access, so just one shot
will do it. */
memcpy(copyto, ptr, len);
copyto += len;
} else { /* We have to do multiple writes to get all the data
written. */ while (soff_hi != eoff_hi) { #ifdef CONFIG_MTD_PMC551_DEBUG
printk(KERN_DEBUG "pmc551_read() soff_hi: %ld, " "eoff_hi: %ld\n", (long)soff_hi, (long)eoff_hi); #endif
memcpy(copyto, ptr, priv->asize);
copyto += priv->asize; if (soff_hi + priv->asize >= mtd->size) { goto out;
}
soff_hi += priv->asize;
pmc551_point(mtd, soff_hi, priv->asize, retlen,
(void **)&ptr, NULL);
}
memcpy(copyto, ptr, eoff_lo);
copyto += eoff_lo;
}
end = to + len - 1;
soff_hi = to & ~(priv->asize - 1);
eoff_hi = end & ~(priv->asize - 1);
eoff_lo = end & (priv->asize - 1);
pmc551_point(mtd, to, len, retlen, (void **)&ptr, NULL);
if (soff_hi == eoff_hi) { /* The whole thing fits within one access, so just one shot
will do it. */
memcpy(ptr, copyfrom, len);
copyfrom += len;
} else { /* We have to do multiple writes to get all the data
written. */ while (soff_hi != eoff_hi) { #ifdef CONFIG_MTD_PMC551_DEBUG
printk(KERN_DEBUG "pmc551_write() soff_hi: %ld, " "eoff_hi: %ld\n", (long)soff_hi, (long)eoff_hi); #endif
memcpy(ptr, copyfrom, priv->asize);
copyfrom += priv->asize; if (soff_hi >= mtd->size) { goto out;
}
soff_hi += priv->asize;
pmc551_point(mtd, soff_hi, priv->asize, retlen,
(void **)&ptr, NULL);
}
memcpy(ptr, copyfrom, eoff_lo);
copyfrom += eoff_lo;
}
/* * Fixup routines for the V370PDC * PCI device ID 0x020011b0 * * This function basically kick starts the DRAM oboard the card and gets it * ready to be used. Before this is done the device reads VERY erratic, so * much that it can crash the Linux 2.2.x series kernels when a user cat's * /proc/pci .. though that is mainly a kernel bug in handling the PCI DEVSEL * register. FIXME: stop spinning on registers .. must implement a timeout * mechanism * returns the size of the memory region found.
*/ staticint __init fixup_pmc551(struct pci_dev *dev)
{ #ifdef CONFIG_MTD_PMC551_BUGFIX
u32 dram_data; #endif
u32 size, dcmd, cfg, dtmp;
u16 cmd, tmp, i;
u8 bcmd, counter;
/* Sanity Check */ if (!dev) { return -ENODEV;
}
/* * Attempt to reset the card * FIXME: Stop Spinning registers
*/
counter = 0; /* unlock registers */
pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, 0xA5); /* read in old data */
pci_read_config_byte(dev, PMC551_SYS_CTRL_REG, &bcmd); /* bang the reset line up and down for a few */ for (i = 0; i < 10; i++) {
counter = 0;
bcmd &= ~0x80; while (counter++ < 100) {
pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd);
}
counter = 0;
bcmd |= 0x80; while (counter++ < 100) {
pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd);
}
}
bcmd |= (0x40 | 0x20);
pci_write_config_byte(dev, PMC551_SYS_CTRL_REG, bcmd);
/* * Take care and turn off the memory on the device while we * tweak the configurations
*/
pci_read_config_word(dev, PCI_COMMAND, &cmd);
tmp = cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
pci_write_config_word(dev, PCI_COMMAND, tmp);
/* * Disable existing aperture before probing memory size
*/
pci_read_config_dword(dev, PMC551_PCI_MEM_MAP0, &dcmd);
dtmp = (dcmd | PMC551_PCI_MEM_MAP_ENABLE | PMC551_PCI_MEM_MAP_REG_EN);
pci_write_config_dword(dev, PMC551_PCI_MEM_MAP0, dtmp); /* * Grab old BAR0 config so that we can figure out memory size * This is another bit of kludge going on. The reason for the * redundancy is I am hoping to retain the original configuration * previously assigned to the card by the BIOS or some previous * fixup routine in the kernel. So we read the old config into cfg, * then write all 1's to the memory space, read back the result into * "size", and then write back all the old config.
*/
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &cfg); #ifndef CONFIG_MTD_PMC551_BUGFIX
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, ~0);
pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &size);
size = (size & PCI_BASE_ADDRESS_MEM_MASK);
size &= ~(size - 1);
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, cfg); #else /* * Get the size of the memory by reading all the DRAM size values * and adding them up. * * KLUDGE ALERT: the boards we are using have invalid column and * row mux values. We fix them here, but this will break other * memory configurations.
*/
pci_read_config_dword(dev, PMC551_DRAM_BLK0, &dram_data);
size = PMC551_DRAM_BLK_GET_SIZE(dram_data);
dram_data = PMC551_DRAM_BLK_SET_COL_MUX(dram_data, 0x5);
dram_data = PMC551_DRAM_BLK_SET_ROW_MUX(dram_data, 0x9);
pci_write_config_dword(dev, PMC551_DRAM_BLK0, dram_data);
/* * Wait until command has gone through * FIXME: register spinning issue
*/ do {
pci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd); if (counter++ > 100) break;
} while ((PCI_COMMAND_IO) & cmd);
/* * Turn on auto refresh * The loop is taken directly from Ramix's example code. I assume that * this must be held high for some duration of time, but I can find no * documentation refrencing the reasons why.
*/ for (i = 1; i <= 8; i++) {
pci_write_config_word(dev, PMC551_SDRAM_CMD, 0x0df);
/* * Make certain command has gone through * FIXME: register spinning issue
*/
counter = 0; do {
pci_read_config_word(dev, PMC551_SDRAM_CMD, &cmd); if (counter++ > 100) break;
} while ((PCI_COMMAND_IO) & cmd);
}
/* * Check to make certain fast back-to-back, if not * then set it so
*/
pci_read_config_word(dev, PCI_STATUS, &cmd); if ((cmd & PCI_COMMAND_FAST_BACK) == 0) {
cmd |= PCI_COMMAND_FAST_BACK;
pci_write_config_word(dev, PCI_STATUS, cmd);
}
/* * Check to make certain the DEVSEL is set correctly, this device * has a tendency to assert DEVSEL and TRDY when a write is performed * to the memory when memory is read-only
*/ if ((cmd & PCI_STATUS_DEVSEL_MASK) != 0x0) {
cmd &= ~PCI_STATUS_DEVSEL_MASK;
pci_write_config_word(dev, PCI_STATUS, cmd);
} /* * Set to be prefetchable and put everything back based on old cfg. * it's possible that the reset of the V370PDC nuked the original * setup
*/ /* cfg |= PCI_BASE_ADDRESS_MEM_PREFETCH; pci_write_config_dword( dev, PCI_BASE_ADDRESS_0, cfg );
*/
/* * Turn PCI memory and I/O bus access back on
*/
pci_write_config_word(dev, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); #ifdef CONFIG_MTD_PMC551_DEBUG /* * Some screen fun
*/
printk(KERN_DEBUG "pmc551: %d%sB (0x%x) of %sprefetchable memory at " "0x%llx\n", (size < 1024) ? size : (size < 1048576) ?
size >> 10 : size >> 20,
(size < 1024) ? "" : (size < 1048576) ? "Ki" : "Mi", size,
((dcmd & (0x1 << 3)) == 0) ? "non-" : "",
(unsignedlonglong)pci_resource_start(dev, 0));
/* * Check to see the state of the memory
*/
pci_read_config_dword(dev, PMC551_DRAM_BLK0, &dcmd);
printk(KERN_DEBUG "pmc551: DRAM_BLK0 Flags: %s,%s\n" "pmc551: DRAM_BLK0 Size: %d at %d\n" "pmc551: DRAM_BLK0 Row MUX: %d, Col MUX: %d\n",
(((0x1 << 1) & dcmd) == 0) ? "RW" : "RO",
(((0x1 << 0) & dcmd) == 0) ? "Off" : "On",
PMC551_DRAM_BLK_GET_SIZE(dcmd),
((dcmd >> 20) & 0x7FF), ((dcmd >> 13) & 0x7),
((dcmd >> 9) & 0xF));
printk(KERN_NOTICE "pmc551: Found PCI V370PDC at 0x%llx\n",
(unsignedlonglong)pci_resource_start(PCI_Device, 0));
/* * The PMC551 device acts VERY weird if you don't init it * first. i.e. it will not correctly report devsel. If for * some reason the sdram is in a wrote-protected state the * device will DEVSEL when it is written to causing problems * with the oldproc.c driver in * some kernels (2.2.*)
*/ if ((length = fixup_pmc551(PCI_Device)) <= 0) {
printk(KERN_NOTICE "pmc551: Cannot init SDRAM\n"); break;
}
/* * This is needed until the driver is capable of reading the * onboard I2C SROM to discover the "real" memory size.
*/ if (msize) {
length = msize;
printk(KERN_NOTICE "pmc551: Using specified memory " "size 0x%x\n", length);
} else {
msize = length;
}
mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL); if (!mtd) break;
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