// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* Copyright 2017 Microsemi Corporation * Copyright 2018-2019 NXP #include <linux/fsl/enetc_mdio.h>#include <soc/mscc/ocelot_qsys.h>#include <soc/mscc/ocelot_vcap.h>#include <soc/mscc/ocelot_ana.h>#include <soc/mscc/ocelot_dev.h>#include <soc/mscc/ocelot_ptp.h>#include <soc/mscc/ocelot_sys.h>#include <net/tc_act/tc_gate.h>#include <soc/mscc/ocelot.h>#include <linux/dsa/ocelot.h>#include <linux/pcs-lynx.h>#include <net/pkt_sched.h>#include <linux/iopoll.h>#include <linux/mdio.h>#include <linux/of.h>#include <linux/pci.h>#include <linux/time.h>#include "felix.h" #define VSC9959_NUM_PORTS 6#define VSC9959_TAS_GCL_ENTRY_MAX 63#define VSC9959_TAS_MIN_GATE_LEN_NS 35#define VSC9959_VCAP_POLICER_BASE 63#define VSC9959_VCAP_POLICER_MAX 383#define VSC9959_SWITCH_PCI_BAR 4#define VSC9959_IMDIO_PCI_BAR 0#define VSC9959_PORT_MODE_SERDES (OCELOT_PORT_MODE_SGMII | \static const u32 vsc9959_port_modes[VSC9959_NUM_PORTS] = {static const u32 vsc9959_ana_regmap[] = {static const u32 vsc9959_qs_regmap[] = {static const u32 vsc9959_vcap_regmap[] = {/* VCAP_CORE_CFG */ /* VCAP_CORE_CACHE */ /* VCAP_CONST */ static const u32 vsc9959_qsys_regmap[] = {static const u32 vsc9959_rew_regmap[] = {static const u32 vsc9959_sys_regmap[] = {static const u32 vsc9959_ptp_regmap[] = {static const u32 vsc9959_gcb_regmap[] = {static const u32 vsc9959_dev_gmii_regmap[] = {static const u32 *vsc9959_regmap[TARGET_MAX] = {/* Addresses are relative to the PCI device's base address */ static const struct resource vsc9959_resources[] = {"sys" ),"rew" ),"s0" ),"s1" ),"s2" ),"devcpu_gcb" ),"qs" ),"ptp" ),"port0" ),"port1" ),"port2" ),"port3" ),"port4" ),"port5" ),"qsys" ),"ana" ),static const char * const vsc9959_resource_names[TARGET_MAX] = {"sys" ,"rew" ,"s0" ,"s1" ,"s2" ,"devcpu_gcb" ,"qs" ,"ptp" ,"qsys" ,"ana" ,/* Port MAC 0 Internal MDIO bus through which the SerDes acting as an * SGMII/QSGMII MAC PCS can be found. static const struct resource vsc9959_imdio_res ="imdio" );static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {/* Replicated per number of ports (7), register size 4 per port */ 4),, 7, 4),static const struct vcap_field vsc9959_vcap_es0_keys[] = {static const struct vcap_field vsc9959_vcap_es0_actions[] = {static const struct vcap_field vsc9959_vcap_is1_keys[] = {/* Specific Fields for IS1 Half Key S1_NORMAL */ /* Layer-3 Information */ /* Layer-4 Information */ /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ static const struct vcap_field vsc9959_vcap_is1_actions[] = {/* The fields below are incorrectly shifted by 2 in the manual */ static struct vcap_field vsc9959_vcap_is2_keys[] = {/* Common: 41 bits */ /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ /* MAC_ETYPE (TYPE=000) */ /* MAC_LLC (TYPE=001) */ /* MAC_SNAP (TYPE=010) */ /* MAC_ARP (TYPE=011) */ /* IP4_TCP_UDP / IP4_OTHER common */ /* IP4_TCP_UDP (TYPE=100) */ /* IP4_OTHER (TYPE=101) */ /* IP6_STD (TYPE=110) */ /* OAM (TYPE=111) */ static struct vcap_field vsc9959_vcap_is2_actions[] = {static struct vcap_props vsc9959_vcap_props[] = {/* HIT_STICKY not included */ /* HIT_STICKY not included */ static const struct ptp_clock_info vsc9959_ptp_caps = {"felix ptp" ,#define VSC9959_INIT_TIMEOUT 50000#define VSC9959_GCB_RST_SLEEP 100#define VSC9959_SYS_RAMINIT_SLEEP 80static int vsc9959_gcb_soft_rst_status(struct ocelot *ocelot)int val;return val;static int vsc9959_sys_ram_init_status(struct ocelot *ocelot)return ocelot_read(ocelot, SYS_RAM_INIT);/* CORE_ENA is in SYS:SYSTEM:RESET_CFG * RAM_INIT is in SYS:RAM_CTRL:RAM_INIT static int vsc9959_reset(struct ocelot *ocelot)int val, err;/* soft-reset the switch core */ if (err) {"timeout: switch core reset\n" );return err;/* initialize switch mem ~40us */ if (err) {"timeout: switch sram init\n" );return err;/* enable switch core */ return 0;/* Watermark encode * Bit 8: Unit; 0:1, 1:16 * Bit 7-0: Value to be multiplied with unit static u16 vsc9959_wm_enc(u16 value)if (value >= BIT(8))return BIT(8) | (value / 16);return value;static u16 vsc9959_wm_dec(u16 wm)if (wm & BIT(8))return (wm & GENMASK(7, 0)) * 16;return wm;static void vsc9959_wm_stat(u32 val, u32 *inuse, u32 *maxuse)static int vsc9959_mdio_bus_alloc(struct ocelot *ocelot)struct pci_dev *pdev = to_pci_dev(ocelot->dev);struct felix *felix = ocelot_to_felix(ocelot);struct enetc_mdio_priv *mdio_priv;struct device *dev = ocelot->dev;void __iomem *imdio_regs;struct resource res;struct enetc_hw *hw;struct mii_bus *bus;int port;int rc;sizeof (struct phylink_pcs *),if (!felix->pcs) {"failed to allocate array for PCS PHYs\n" );return -ENOMEM;sizeof (res));if (IS_ERR(imdio_regs))return PTR_ERR(imdio_regs);if (IS_ERR(hw)) {"failed to allocate ENETC HW structure\n" );return PTR_ERR(hw);sizeof (*mdio_priv));if (!bus)return -ENOMEM;"VSC9959 internal MDIO bus" ;/* This gets added to imdio_regs, which already maps addresses * starting with the proper offset. "%s-imdio" , dev_name(dev));/* Needed in order to initialize the bus mutex lock */ if (rc < 0) {"failed to register MDIO bus\n" );return rc;for (port = 0; port < felix->info->num_ports; port++) {struct ocelot_port *ocelot_port = ocelot->ports[port];struct phylink_pcs *phylink_pcs;if (dsa_is_unused_port(felix->ds, port))continue ;if (ocelot_port->phy_mode == PHY_INTERFACE_MODE_INTERNAL)continue ;if (IS_ERR(phylink_pcs))continue ;"Found PCS at internal MDIO address %d\n" , port);return 0;static void vsc9959_mdio_bus_free(struct ocelot *ocelot)struct felix *felix = ocelot_to_felix(ocelot);int port;for (port = 0; port < ocelot->num_phys_ports; port++) {struct phylink_pcs *phylink_pcs = felix->pcs[port];if (phylink_pcs)/* The switch considers any frame (regardless of size) as eligible * for transmission if the traffic class gate is open for at least * VSC9959_TAS_MIN_GATE_LEN_NS. * * Overruns are prevented by cropping an interval at the end of the gate time * slot for which egress scheduling is blocked, but we need to still keep * VSC9959_TAS_MIN_GATE_LEN_NS available for one packet to be transmitted, * otherwise the port tc will hang. * * This function returns the size of a gate interval that remains available for * setting the guard band, after reserving the space for one egress frame. static u64 vsc9959_tas_remaining_gate_len_ps(u64 gate_len_ns)/* Gate always open */ if (gate_len_ns == U64_MAX)return U64_MAX;if (gate_len_ns < VSC9959_TAS_MIN_GATE_LEN_NS)return 0;return (gate_len_ns - VSC9959_TAS_MIN_GATE_LEN_NS) * PSEC_PER_NSEC;/* Extract shortest continuous gate open intervals in ns for each traffic class * of a cyclic tc-taprio schedule. If a gate is always open, the duration is * considered U64_MAX. If the gate is always closed, it is considered 0. static void vsc9959_tas_min_gate_lengths(struct tc_taprio_qopt_offload *taprio,struct tc_taprio_sched_entry *entry;int tc, i, n;/* Initialize arrays */ for (tc = 0; tc < OCELOT_NUM_TC; tc++) {/* If we don't have taprio, consider all gates as permanently open */ if (!taprio)return ;/* Walk through the gate list twice to determine the length * of consecutively open gates for a traffic class, including * open gates that wrap around. We are just interested in the * minimum window size, and this doesn't change what the * minimum is (if the gate never closes, min_gate_len will * remain U64_MAX). for (i = 0; i < 2 * n; i++) {for (tc = 0; tc < OCELOT_NUM_TC; tc++) {if (entry->gate_mask & BIT(tc)) {else {/* Gate closes now, record a potential new * minimum and reinitialize length if (min_gate_len[tc] > gate_len[tc] &&/* min_gate_len[tc] actually tracks minimum *open* gate time, so for * permanently closed gates, min_gate_len[tc] will still be U64_MAX. * Therefore they are currently indistinguishable from permanently * open gates. Overwrite the gate len with 0 when we know they're * actually permanently closed, i.e. after the loop above. for (tc = 0; tc < OCELOT_NUM_TC; tc++)if (!(gates_ever_opened & BIT(tc)))/* ocelot_write_rix is a macro that concatenates QSYS_MAXSDU_CFG_* with _RSZ, * so we need to spell out the register access to each traffic class in helper * functions, to simplify callers static void vsc9959_port_qmaxsdu_set(struct ocelot *ocelot, int port, int tc,switch (tc) {case 0:break ;case 1:break ;case 2:break ;case 3:break ;case 4:break ;case 5:break ;case 6:break ;case 7:break ;static u32 vsc9959_port_qmaxsdu_get(struct ocelot *ocelot, int port, int tc)switch (tc) {case 0: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_0, port);case 1: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_1, port);case 2: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_2, port);case 3: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_3, port);case 4: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_4, port);case 5: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_5, port);case 6: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_6, port);case 7: return ocelot_read_rix(ocelot, QSYS_QMAXSDU_CFG_7, port);default :return 0;static u32 vsc9959_tas_tc_max_sdu(struct tc_taprio_qopt_offload *taprio, int tc)if (!taprio || !taprio->max_sdu[tc])return 0;return taprio->max_sdu[tc] + ETH_HLEN + 2 * VLAN_HLEN + ETH_FCS_LEN;/* Update QSYS_PORT_MAX_SDU to make sure the static guard bands added by the * switch (see the ALWAYS_GUARD_BAND_SCH_Q comment) are correct at all MTU * values (the default value is 1518). Also, for traffic class windows smaller * than one MTU sized frame, update QSYS_QMAXSDU_CFG to enable oversized frame * dropping, such that these won't hang the port, as they will never be sent. static void vsc9959_tas_guard_bands_update(struct ocelot *ocelot, int port)struct ocelot_port *ocelot_port = ocelot->ports[port];struct ocelot_mm_state *mm = &ocelot->mm[port];struct tc_taprio_qopt_offload *taprio;int speed, picos_per_byte;int tc;switch (tas_speed) {case OCELOT_SPEED_10:break ;case OCELOT_SPEED_100:break ;case OCELOT_SPEED_1000:break ;case OCELOT_SPEED_2500:break ;default :return ;/* MAXLEN_CFG accounts automatically for VLAN. We need to include it * manually in the bit time calculation, plus the preamble and SFD. /* Consider the standard Ethernet overhead of 8 octets preamble+SFD, * 4 octets FCS, 12 octets IFG. /* Preemptible TCs don't need to pass a full MTU, the port will * automatically emit a HOLD request when a preemptible TC gate closes "port %d: max frame size %d needs %llu ps, %llu ps for mPackets at speed %d\n" ,for (tc = 0; tc < OCELOT_NUM_TC; tc++) {if ((mm->active_preemptible_tcs & BIT(tc)) ?/* Setting QMAXSDU_CFG to 0 disables oversized frame * dropping. "port %d tc %d min gate len %llu" ", sending all frames\n" ,else {/* If traffic class doesn't support a full MTU sized * frame, make sure to enable oversize frame dropping * for frames larger than the smallest that would fit. * * However, the exact same register, QSYS_QMAXSDU_CFG_*, * controls not only oversized frame dropping, but also * per-tc static guard band lengths, so it reduces the * useful gate interval length. Therefore, be careful * to calculate a guard band (and therefore max_sdu) * that still leaves VSC9959_TAS_MIN_GATE_LEN_NS * available in the time slot. /* A TC gate may be completely closed, which is a * special case where all packets are oversized. * Any limit smaller than 64 octets accomplishes this if (!max_sdu)/* Take L1 overhead into account, but just don't allow * max_sdu to go negative or to 0. Here we use 20 * because QSYS_MAXSDU_CFG_* already counts the 4 FCS * octets as part of packet size. if (max_sdu > 20)if (requested_max_sdu && requested_max_sdu < max_sdu)"port %d tc %d min gate length %llu" " ns not enough for max frame size %d at %d" " Mbps, dropping frames over %d" " octets including FCS\n" ,static void vsc9959_sched_speed_set(struct ocelot *ocelot, int port,struct ocelot_port *ocelot_port = ocelot->ports[port];switch (speed) {case SPEED_10:break ;case SPEED_100:break ;case SPEED_1000:break ;case SPEED_2500:break ;default :break ;if (ocelot_port->taprio)static void vsc9959_new_base_time(struct ocelot *ocelot, ktime_t base_time,struct timespec64 *new_base_ts)struct timespec64 ts;if (base_time < current_time) {static u32 vsc9959_tas_read_cfg_status(struct ocelot *ocelot)return ocelot_read(ocelot, QSYS_TAS_PARAM_CFG_CTRL);static void vsc9959_tas_gcl_set(struct ocelot *ocelot, const u32 gcl_ix,struct tc_taprio_sched_entry *entry)static int vsc9959_qos_port_tas_set(struct ocelot *ocelot, int port,struct tc_taprio_qopt_offload *taprio)struct ocelot_port *ocelot_port = ocelot->ports[port];struct timespec64 base_ts;int ret, i;if (taprio->cmd == TAPRIO_CMD_DESTROY) {return 0;else if (taprio->cmd != TAPRIO_CMD_REPLACE) {goto err_unlock;if (ret)goto err_unlock;if (taprio->cycle_time > NSEC_PER_SEC ||goto err_reset_tc;if (taprio->num_entries > VSC9959_TAS_GCL_ENTRY_MAX) {goto err_reset_tc;/* Enable guard band. The switch will schedule frames without taking * their length into account. Thus we'll always need to enable the * guard band which reserves the time of a maximum sized frame at the * end of the time window. * * Although the ALWAYS_GUARD_BAND_SCH_Q bit is global for all ports, we * need to set PORT_NUM, because subsequent writes to PARAM_CFG_REG_n * operate on the port number. /* Hardware errata - Admin config could not be overwritten if * config is pending, need reset the TAS module if (val & QSYS_TAG_CONFIG_ENABLE) {if (val & QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING) {goto err_reset_tc;for (i = 0; i < taprio->num_entries; i++)if (ret)goto err_reset_tc;return 0;return ret;static void vsc9959_tas_clock_adjust(struct ocelot *ocelot)struct tc_taprio_qopt_offload *taprio;struct ocelot_port *ocelot_port;struct timespec64 base_ts;int i, port;for (port = 0; port < ocelot->num_phys_ports; port++) {if (!taprio)continue ;/* Disable time-aware shaper */ for (i = 0; i < taprio->num_entries; i++)/* Re-enable time-aware shaper */ static int vsc9959_qos_port_cbs_set(struct dsa_switch *ds, int port,struct tc_cbs_qopt_offload *cbs_qopt)struct ocelot *ocelot = ds->priv;int port_ix = port * 8 + cbs_qopt->queue;if (cbs_qopt->queue >= ds->num_tx_queues)return -EINVAL;if (!cbs_qopt->enable) {return 0;/* Rate unit is 100 kbps */ /* Avoid using zero rate */ /* Burst unit is 4kB */ /* Avoid using zero burst size */ return 0;static int vsc9959_qos_query_caps(struct tc_query_caps_base *base)switch (base->type) {case TC_SETUP_QDISC_MQPRIO: {struct tc_mqprio_caps *caps = base->caps;true ;return 0;case TC_SETUP_QDISC_TAPRIO: {struct tc_taprio_caps *caps = base->caps;true ;return 0;default :return -EOPNOTSUPP;static int vsc9959_qos_port_mqprio(struct ocelot *ocelot, int port,struct tc_mqprio_qopt_offload *mqprio)int ret;return ret;static int vsc9959_port_setup_tc(struct dsa_switch *ds, int port,enum tc_setup_type type,void *type_data)struct ocelot *ocelot = ds->priv;switch (type) {case TC_QUERY_CAPS:return vsc9959_qos_query_caps(type_data);case TC_SETUP_QDISC_TAPRIO:return vsc9959_qos_port_tas_set(ocelot, port, type_data);case TC_SETUP_QDISC_MQPRIO:return vsc9959_qos_port_mqprio(ocelot, port, type_data);case TC_SETUP_QDISC_CBS:return vsc9959_qos_port_cbs_set(ds, port, type_data);default :return -EOPNOTSUPP;#define VSC9959_PSFP_SFID_MAX 175#define VSC9959_PSFP_GATE_ID_MAX 183#define VSC9959_PSFP_POLICER_BASE 63#define VSC9959_PSFP_POLICER_MAX 383#define VSC9959_PSFP_GATE_LIST_NUM 4#define VSC9959_PSFP_GATE_CYCLETIME_MIN 5000struct felix_stream {struct list_head list;unsigned long id;bool dummy;int ports;int port;struct felix_stream_filter_counters {struct felix_stream_filter {struct felix_stream_filter_counters stats;struct list_head list;int portmask;struct felix_stream_gate {struct action_gate_entry entries[] __counted_by(num_entries);struct felix_stream_gate_entry {struct list_head list;static int vsc9959_stream_identify(struct flow_cls_offload *f,struct felix_stream *stream)struct flow_rule *rule = flow_cls_offload_flow_rule(f);struct flow_dissector *dissector = rule->match.dissector;if (dissector->used_keys &return -EOPNOTSUPP;if (flow_rule_match_has_control_flags(rule, f->common.extack))return -EOPNOTSUPP;if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {struct flow_match_eth_addrs match;if (!is_zero_ether_addr(match.mask->src))return -EOPNOTSUPP;else {return -EOPNOTSUPP;if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {struct flow_match_vlan match;if (match.mask->vlan_priority)else if (!match.mask->vlan_id)return -EOPNOTSUPP;else {return -EOPNOTSUPP;return 0;static int vsc9959_mact_stream_set(struct ocelot *ocelot,struct felix_stream *stream,struct netlink_ext_ack *extack)enum macaccess_entry_type type;int ret, sfid, ssid;/* Stream identification desn't support to add a stream with non * existent MAC (The MAC entry has not been learned in MAC table). if (ret) {if (extack)"Stream is not learned in MAC table" );return -EOPNOTSUPP;if ((stream->sfid_valid || stream->ssid_valid) &&return ret;static struct felix_stream *struct list_head *stream_list,struct felix_stream *stream)struct felix_stream *tmp;if (ether_addr_equal(tmp->dmac, stream->dmac) &&return tmp;return NULL;static int vsc9959_stream_table_add(struct ocelot *ocelot,struct list_head *stream_list,struct felix_stream *stream,struct netlink_ext_ack *extack)struct felix_stream *stream_entry;int ret;sizeof (*stream_entry), GFP_KERNEL);if (!stream_entry)return -ENOMEM;if (!stream->dummy) {if (ret) {return ret;return 0;static struct felix_stream *struct list_head *stream_list, unsigned long id)struct felix_stream *tmp;if (tmp->id == id)return tmp;return NULL;static void vsc9959_stream_table_del(struct ocelot *ocelot,struct felix_stream *stream)if (!stream->dummy)static u32 vsc9959_sfi_access_status(struct ocelot *ocelot)return ocelot_read(ocelot, ANA_TABLES_SFIDACCESS);static int vsc9959_psfp_sfi_set(struct ocelot *ocelot,struct felix_stream_filter *sfi)if (sfi->index > VSC9959_PSFP_SFID_MAX)return -EINVAL;if (!sfi->enable) {return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,if (sfi->sgid > VSC9959_PSFP_GATE_ID_MAX ||return -EINVAL;return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,static int vsc9959_psfp_sfidmask_set(struct ocelot *ocelot, u32 sfid, int ports)return readx_poll_timeout(vsc9959_sfi_access_status, ocelot, val,static int vsc9959_psfp_sfi_list_add(struct ocelot *ocelot,struct felix_stream_filter *sfi,struct list_head *pos)struct felix_stream_filter *sfi_entry;int ret;sizeof (*sfi_entry), GFP_KERNEL);if (!sfi_entry)return -ENOMEM;if (ret) {return ret;return 0;static int vsc9959_psfp_sfi_table_add(struct ocelot *ocelot,struct felix_stream_filter *sfi)struct list_head *pos, *q, *last;struct felix_stream_filter *tmp;struct ocelot_psfp_list *psfp;struct felix_stream_filter, list);if (sfi->sg_valid == tmp->sg_valid &&return 0;/* Make sure that the index is increasing in order. */ if (tmp->index == insert) {return vsc9959_psfp_sfi_list_add(ocelot, sfi, last);static int vsc9959_psfp_sfi_table_add2(struct ocelot *ocelot,struct felix_stream_filter *sfi,struct felix_stream_filter *sfi2)struct felix_stream_filter *tmp;struct list_head *pos, *q, *last;struct ocelot_psfp_list *psfp;int ret;struct felix_stream_filter, list);/* Make sure that the index is increasing in order. */ if (tmp->index >= insert + 2)break ;if (ret)return ret;return vsc9959_psfp_sfi_list_add(ocelot, sfi2, last->next);static struct felix_stream_filter *struct list_head *sfi_list, u32 index)struct felix_stream_filter *tmp;if (tmp->index == index)return tmp;return NULL;static void vsc9959_psfp_sfi_table_del(struct ocelot *ocelot, u32 index)struct felix_stream_filter *tmp, *n;struct ocelot_psfp_list *psfp;if (tmp->index == index) {if (z) {break ;static void vsc9959_psfp_parse_gate(const struct flow_action_entry *entry,struct felix_stream_gate *sgi)sizeof (struct action_gate_entry));static u32 vsc9959_sgi_cfg_status(struct ocelot *ocelot)
Messung V0.5 C=97 H=92 G=94
¤ Dauer der Verarbeitung: 0.20 Sekunden
¤ *© Formatika GbR, Deutschland
