/* * This file is part of the Chelsio T4 Ethernet driver for Linux. * * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved. * * This software is available to you under a choice of one of two * licenses. You may choose to be licensed under the terms of the GNU * General Public License (GPL) Version 2, available from the file * COPYING in the main directory of this source tree, or the * OpenIB.org BSD license below: * * Redistribution and use in source and binary forms, with or * without modification, are permitted provided that the following * conditions are met: * * - Redistributions of source code must retain the above * copyright notice, this list of conditions and the following * disclaimer. * * - Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials * provided with the distribution. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. #ifndef _T4FW_INTERFACE_H_#define _T4FW_INTERFACE_H_enum fw_retval {/* completed successfully */ /* operation not permitted */ /* no such file or directory */ /* input/output error; hw bad */ /* exec format error; inv microcode */ /* try again */ /* out of memory */ /* bad address; fw bad */ /* resource busy */ /* file exists */ /* no such device */ /* invalid argument */ /* no space left on device */ /* functionality not implemented */ /* no data available */ /* protocol error */ /* address already in use */ /* cannot assigned requested address */ /* network is down */ /* network is unreachable */ /* no buffer space available */ /* timeout */ /* fw internal */ /* */ /* */ /* */ /* */ /* */ /* */ /* */ /* */ /* */ /* */ /* */ /* */ /* */ /* DDP error*/ /* No SCSI tasks available */ #define FW_T4VF_SGE_BASE_ADDR 0x0000#define FW_T4VF_MPS_BASE_ADDR 0x0100#define FW_T4VF_PL_BASE_ADDR 0x0200#define FW_T4VF_MBDATA_BASE_ADDR 0x0240#define FW_T4VF_CIM_BASE_ADDR 0x0300enum fw_wr_opcodes {struct fw_wr_hdr {/* work request opcode (hi) */ #define FW_WR_OP_S 24#define FW_WR_OP_M 0xff#define FW_WR_OP_V(x) ((x) << FW_WR_OP_S)#define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M)/* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */ #define FW_WR_ATOMIC_S 23#define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S)/* flush flag (hi) - firmware flushes flushable work request buffered * in the flow context. #define FW_WR_FLUSH_S 22#define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S)/* completion flag (hi) - firmware generates a cpl_fw6_ack */ #define FW_WR_COMPL_S 21#define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S)#define FW_WR_COMPL_F FW_WR_COMPL_V(1U)/* work request immediate data length (hi) */ #define FW_WR_IMMDLEN_S 0#define FW_WR_IMMDLEN_M 0xff#define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S)/* egress queue status update to associated ingress queue entry (lo) */ #define FW_WR_EQUIQ_S 31#define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S)#define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U)/* egress queue status update to egress queue status entry (lo) */ #define FW_WR_EQUEQ_S 30#define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S)#define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U)/* flow context identifier (lo) */ #define FW_WR_FLOWID_S 8#define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S)/* length in units of 16-bytes (lo) */ #define FW_WR_LEN16_S 0#define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S)#define HW_TPL_FR_MT_PR_IV_P_FC 0X32B#define HW_TPL_FR_MT_PR_OV_P_FC 0X327/* filter wr reply code in cookie in CPL_SET_TCB_RPL */ enum fw_filter_wr_cookie {struct fw_filter_wr {struct fw_filter2_wr {#define FW_FILTER_WR_TID_S 12#define FW_FILTER_WR_TID_M 0xfffff#define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)#define FW_FILTER_WR_TID_G(x) \#define FW_FILTER_WR_RQTYPE_S 11#define FW_FILTER_WR_RQTYPE_M 0x1#define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S)#define FW_FILTER_WR_RQTYPE_G(x) \#define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U)#define FW_FILTER_WR_NOREPLY_S 10#define FW_FILTER_WR_NOREPLY_M 0x1#define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S)#define FW_FILTER_WR_NOREPLY_G(x) \#define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U)#define FW_FILTER_WR_IQ_S 0#define FW_FILTER_WR_IQ_M 0x3ff#define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S)#define FW_FILTER_WR_IQ_G(x) \#define FW_FILTER_WR_DEL_FILTER_S 31#define FW_FILTER_WR_DEL_FILTER_M 0x1#define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S)#define FW_FILTER_WR_DEL_FILTER_G(x) \#define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U)#define FW_FILTER_WR_RPTTID_S 25#define FW_FILTER_WR_RPTTID_M 0x1#define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S)#define FW_FILTER_WR_RPTTID_G(x) \#define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U)#define FW_FILTER_WR_DROP_S 24#define FW_FILTER_WR_DROP_M 0x1#define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S)#define FW_FILTER_WR_DROP_G(x) \#define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U)#define FW_FILTER_WR_DIRSTEER_S 23#define FW_FILTER_WR_DIRSTEER_M 0x1#define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S)#define FW_FILTER_WR_DIRSTEER_G(x) \#define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)#define FW_FILTER_WR_MASKHASH_S 22#define FW_FILTER_WR_MASKHASH_M 0x1#define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S)#define FW_FILTER_WR_MASKHASH_G(x) \#define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)#define FW_FILTER_WR_DIRSTEERHASH_S 21#define FW_FILTER_WR_DIRSTEERHASH_M 0x1#define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S)#define FW_FILTER_WR_DIRSTEERHASH_G(x) \#define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U)#define FW_FILTER_WR_LPBK_S 20#define FW_FILTER_WR_LPBK_M 0x1#define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S)#define FW_FILTER_WR_LPBK_G(x) \#define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U)#define FW_FILTER_WR_DMAC_S 19#define FW_FILTER_WR_DMAC_M 0x1#define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S)#define FW_FILTER_WR_DMAC_G(x) \#define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U)#define FW_FILTER_WR_SMAC_S 18#define FW_FILTER_WR_SMAC_M 0x1#define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S)#define FW_FILTER_WR_SMAC_G(x) \#define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U)#define FW_FILTER_WR_INSVLAN_S 17#define FW_FILTER_WR_INSVLAN_M 0x1#define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S)#define FW_FILTER_WR_INSVLAN_G(x) \#define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U)#define FW_FILTER_WR_RMVLAN_S 16#define FW_FILTER_WR_RMVLAN_M 0x1#define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S)#define FW_FILTER_WR_RMVLAN_G(x) \#define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U)#define FW_FILTER_WR_HITCNTS_S 15#define FW_FILTER_WR_HITCNTS_M 0x1#define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S)#define FW_FILTER_WR_HITCNTS_G(x) \#define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U)#define FW_FILTER_WR_TXCHAN_S 13#define FW_FILTER_WR_TXCHAN_M 0x3#define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S)#define FW_FILTER_WR_TXCHAN_G(x) \#define FW_FILTER_WR_PRIO_S 12#define FW_FILTER_WR_PRIO_M 0x1#define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S)#define FW_FILTER_WR_PRIO_G(x) \#define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U)#define FW_FILTER_WR_L2TIX_S 0#define FW_FILTER_WR_L2TIX_M 0xfff#define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)#define FW_FILTER_WR_L2TIX_G(x) \#define FW_FILTER_WR_FRAG_S 7#define FW_FILTER_WR_FRAG_M 0x1#define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S)#define FW_FILTER_WR_FRAG_G(x) \#define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U)#define FW_FILTER_WR_FRAGM_S 6#define FW_FILTER_WR_FRAGM_M 0x1#define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)#define FW_FILTER_WR_FRAGM_G(x) \#define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U)#define FW_FILTER_WR_IVLAN_VLD_S 5#define FW_FILTER_WR_IVLAN_VLD_M 0x1#define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S)#define FW_FILTER_WR_IVLAN_VLD_G(x) \#define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U)#define FW_FILTER_WR_OVLAN_VLD_S 4#define FW_FILTER_WR_OVLAN_VLD_M 0x1#define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S)#define FW_FILTER_WR_OVLAN_VLD_G(x) \#define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U)#define FW_FILTER_WR_IVLAN_VLDM_S 3#define FW_FILTER_WR_IVLAN_VLDM_M 0x1#define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S)#define FW_FILTER_WR_IVLAN_VLDM_G(x) \#define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U)#define FW_FILTER_WR_OVLAN_VLDM_S 2#define FW_FILTER_WR_OVLAN_VLDM_M 0x1#define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S)#define FW_FILTER_WR_OVLAN_VLDM_G(x) \#define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U)#define FW_FILTER_WR_RX_CHAN_S 15#define FW_FILTER_WR_RX_CHAN_M 0x1#define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S)#define FW_FILTER_WR_RX_CHAN_G(x) \#define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U)#define FW_FILTER_WR_RX_RPL_IQ_S 0#define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff#define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S)#define FW_FILTER_WR_RX_RPL_IQ_G(x) \#define FW_FILTER2_WR_FILTER_TYPE_S 1#define FW_FILTER2_WR_FILTER_TYPE_M 0x1#define FW_FILTER2_WR_FILTER_TYPE_V(x) ((x) << FW_FILTER2_WR_FILTER_TYPE_S)#define FW_FILTER2_WR_FILTER_TYPE_G(x) \#define FW_FILTER2_WR_FILTER_TYPE_F FW_FILTER2_WR_FILTER_TYPE_V(1U)#define FW_FILTER2_WR_NATMODE_S 5#define FW_FILTER2_WR_NATMODE_M 0x7#define FW_FILTER2_WR_NATMODE_V(x) ((x) << FW_FILTER2_WR_NATMODE_S)#define FW_FILTER2_WR_NATMODE_G(x) \#define FW_FILTER2_WR_NATFLAGCHECK_S 4#define FW_FILTER2_WR_NATFLAGCHECK_M 0x1#define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S)#define FW_FILTER2_WR_NATFLAGCHECK_G(x) \#define FW_FILTER2_WR_NATFLAGCHECK_F FW_FILTER2_WR_NATFLAGCHECK_V(1U)#define FW_FILTER2_WR_ULP_TYPE_S 0#define FW_FILTER2_WR_ULP_TYPE_M 0xf#define FW_FILTER2_WR_ULP_TYPE_V(x) ((x) << FW_FILTER2_WR_ULP_TYPE_S)#define FW_FILTER2_WR_ULP_TYPE_G(x) \#define FW_FILTER_WR_MACI_S 23#define FW_FILTER_WR_MACI_M 0x1ff#define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)#define FW_FILTER_WR_MACI_G(x) \#define FW_FILTER_WR_MACIM_S 14#define FW_FILTER_WR_MACIM_M 0x1ff#define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)#define FW_FILTER_WR_MACIM_G(x) \#define FW_FILTER_WR_FCOE_S 13#define FW_FILTER_WR_FCOE_M 0x1#define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S)#define FW_FILTER_WR_FCOE_G(x) \#define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U)#define FW_FILTER_WR_FCOEM_S 12#define FW_FILTER_WR_FCOEM_M 0x1#define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)#define FW_FILTER_WR_FCOEM_G(x) \#define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U)#define FW_FILTER_WR_PORT_S 9#define FW_FILTER_WR_PORT_M 0x7#define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S)#define FW_FILTER_WR_PORT_G(x) \#define FW_FILTER_WR_PORTM_S 6#define FW_FILTER_WR_PORTM_M 0x7#define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)#define FW_FILTER_WR_PORTM_G(x) \#define FW_FILTER_WR_MATCHTYPE_S 3#define FW_FILTER_WR_MATCHTYPE_M 0x7#define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S)#define FW_FILTER_WR_MATCHTYPE_G(x) \#define FW_FILTER_WR_MATCHTYPEM_S 0#define FW_FILTER_WR_MATCHTYPEM_M 0x7#define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S)#define FW_FILTER_WR_MATCHTYPEM_G(x) \struct fw_ulptx_wr {#define FW_ULPTX_WR_DATA_S 28#define FW_ULPTX_WR_DATA_M 0x1#define FW_ULPTX_WR_DATA_V(x) ((x) << FW_ULPTX_WR_DATA_S)#define FW_ULPTX_WR_DATA_G(x) \#define FW_ULPTX_WR_DATA_F FW_ULPTX_WR_DATA_V(1U)struct fw_tp_wr {struct fw_eth_tx_pkt_wr {enum fw_eth_tx_eo_type {struct fw_eth_tx_eo_wr {union fw_eth_tx_eo {struct fw_eth_tx_eo_udpseg {struct fw_eth_tx_eo_tcpseg {#define FW_ETH_TX_EO_WR_IMMDLEN_S 0#define FW_ETH_TX_EO_WR_IMMDLEN_M 0x1ff#define FW_ETH_TX_EO_WR_IMMDLEN_V(x) ((x) << FW_ETH_TX_EO_WR_IMMDLEN_S)#define FW_ETH_TX_EO_WR_IMMDLEN_G(x) \struct fw_ofld_connection_wr {struct fw_ofld_connection_le {union fw_ofld_connection_leip {struct fw_ofld_connection_le_ipv4 {struct fw_ofld_connection_le_ipv6 {struct fw_ofld_connection_tcb {#define FW_OFLD_CONNECTION_WR_VERSION_S 31#define FW_OFLD_CONNECTION_WR_VERSION_M 0x1#define FW_OFLD_CONNECTION_WR_VERSION_V(x) \#define FW_OFLD_CONNECTION_WR_VERSION_G(x) \#define FW_OFLD_CONNECTION_WR_VERSION_F \#define FW_OFLD_CONNECTION_WR_CPL_S 30#define FW_OFLD_CONNECTION_WR_CPL_M 0x1#define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)#define FW_OFLD_CONNECTION_WR_CPL_G(x) \#define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U)#define FW_OFLD_CONNECTION_WR_T_STATE_S 28#define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf#define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \#define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \#define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24#define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf#define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \#define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \#define FW_OFLD_CONNECTION_WR_ASTID_S 0#define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff#define FW_OFLD_CONNECTION_WR_ASTID_V(x) \#define FW_OFLD_CONNECTION_WR_ASTID_G(x) \#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \#define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \#define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \enum fw_flowc_mnem_tcpstate {/* illegal */ /* illegal */ /* illegal */ /* illegal */ /* default */ /* got peer close already */ /* haven't gotten ACK for FIN and * will resend FIN - equiv ESTAB /* haven't gotten ACK for FIN and * will resend FIN but have * received FIN /* haven't gotten ACK for FIN and * will resend FIN but have * received FIN /* sent FIN and got FIN + ACK, * waiting for FIN /* not expected */ enum fw_flowc_mnem_eostate {/* default */ /* graceful close, after sending outstanding payload */ enum fw_flowc_mnem {/* PFN [15:8] VFN [7:0] */ struct fw_flowc_mnemval {struct fw_flowc_wr {struct fw_flowc_mnemval mnemval[];#define FW_FLOWC_WR_NPARAMS_S 0#define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S)struct fw_ofld_tx_data_wr {#define FW_OFLD_TX_DATA_WR_ALIGNPLD_S 30#define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S)#define FW_OFLD_TX_DATA_WR_ALIGNPLD_F FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U)#define FW_OFLD_TX_DATA_WR_SHOVE_S 29#define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)#define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U)#define FW_OFLD_TX_DATA_WR_TUNNEL_S 19#define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)#define FW_OFLD_TX_DATA_WR_SAVE_S 18#define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)#define FW_OFLD_TX_DATA_WR_FLUSH_S 17#define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)#define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U)#define FW_OFLD_TX_DATA_WR_URGENT_S 16#define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)#define FW_OFLD_TX_DATA_WR_MORE_S 15#define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S)#define FW_OFLD_TX_DATA_WR_ULPMODE_S 10#define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)#define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6#define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \struct fw_cmd_wr {#define FW_CMD_WR_DMA_S 17#define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S)struct fw_eth_tx_pkt_vm_wr {#define FW_CMD_MAX_TIMEOUT 10000/* * If a host driver does a HELLO and discovers that there's already a MASTER * selected, we may have to wait for that MASTER to finish issuing RESET, * configuration and INITIALIZE commands. Also, there's a possibility that * our own HELLO may get lost if it happens right as the MASTER is issuign a * RESET command, so we need to be willing to make a few retries of our HELLO. #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)#define FW_CMD_HELLO_RETRIES 3enum fw_cmd_opcodes {enum fw_cmd_cap {/* * Generic command header flit0 struct fw_cmd_hdr {#define FW_CMD_OP_S 24#define FW_CMD_OP_M 0xff#define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S)#define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)#define FW_CMD_REQUEST_S 23#define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S)#define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U)#define FW_CMD_READ_S 22#define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S)#define FW_CMD_READ_F FW_CMD_READ_V(1U)#define FW_CMD_WRITE_S 21#define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S)#define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U)#define FW_CMD_EXEC_S 20#define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S)#define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U)#define FW_CMD_RAMASK_S 20#define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S)#define FW_CMD_RETVAL_S 8#define FW_CMD_RETVAL_M 0xff#define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S)#define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)#define FW_CMD_LEN16_S 0#define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S)#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof (fw_struct) / 16)enum fw_ldst_addrspc {enum fw_ldst_mps_fid {enum fw_ldst_func_access_ctl {enum fw_ldst_func_mod_index {struct fw_ldst_cmd {union fw_ldst {struct fw_ldst_addrval {struct fw_ldst_idctxt {struct fw_ldst_mdio {struct fw_ldst_cim_rq {union fw_ldst_mps {struct fw_ldst_mps_rplc {struct fw_ldst_mps_atrb {struct fw_ldst_func {struct fw_ldst_pcie {struct fw_ldst_i2c_deprecated {struct fw_ldst_i2c {struct fw_ldst_le {#define FW_LDST_CMD_ADDRSPACE_S 0#define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S)#define FW_LDST_CMD_MSG_S 31#define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S)#define FW_LDST_CMD_CTXTFLUSH_S 30#define FW_LDST_CMD_CTXTFLUSH_V(x) ((x) << FW_LDST_CMD_CTXTFLUSH_S)#define FW_LDST_CMD_CTXTFLUSH_F FW_LDST_CMD_CTXTFLUSH_V(1U)#define FW_LDST_CMD_PADDR_S 8#define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S)#define FW_LDST_CMD_MMD_S 0#define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S)#define FW_LDST_CMD_FID_S 15#define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S)#define FW_LDST_CMD_IDX_S 0#define FW_LDST_CMD_IDX_V(x) ((x) << FW_LDST_CMD_IDX_S)#define FW_LDST_CMD_RPLCPF_S 0#define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)#define FW_LDST_CMD_LC_S 4#define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S)#define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U)#define FW_LDST_CMD_FN_S 0#define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S)#define FW_LDST_CMD_NACCESS_S 0#define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S)struct fw_reset_cmd {#define FW_RESET_CMD_HALT_S 31#define FW_RESET_CMD_HALT_M 0x1#define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S)#define FW_RESET_CMD_HALT_G(x) \#define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U)enum fw_hellow_cmd {struct fw_hello_cmd {#define FW_HELLO_CMD_ERR_S 31#define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S)#define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U)#define FW_HELLO_CMD_INIT_S 30#define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S)#define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U)#define FW_HELLO_CMD_MASTERDIS_S 29#define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S)#define FW_HELLO_CMD_MASTERFORCE_S 28#define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S)#define FW_HELLO_CMD_MBMASTER_S 24#define FW_HELLO_CMD_MBMASTER_M 0xfU#define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S)#define FW_HELLO_CMD_MBMASTER_G(x) \#define FW_HELLO_CMD_MBASYNCNOTINT_S 23#define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)#define FW_HELLO_CMD_MBASYNCNOT_S 20#define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S)#define FW_HELLO_CMD_STAGE_S 17#define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S)#define FW_HELLO_CMD_CLEARINIT_S 16#define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S)#define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U)struct fw_bye_cmd {struct fw_initialize_cmd {enum fw_caps_config_hm {enum fw_caps_config_nbm {enum fw_caps_config_link {enum fw_caps_config_switch {enum fw_caps_config_nic {enum fw_caps_config_ofld {enum fw_caps_config_rdma {enum fw_caps_config_iscsi {enum fw_caps_config_crypto {enum fw_caps_config_fcoe {enum fw_memtype_cf {struct fw_caps_config_cmd {#define FW_CAPS_CONFIG_CMD_CFVALID_S 27#define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)#define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U)#define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24#define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \#define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16#define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \/* * params command mnemonics enum fw_params_mnem {/* device params */ /* function params */ /* limited register access */ /* dma queue params */ /* chnet params */ /* * device parameters #define FW_PARAMS_PARAM_FILTER_MODE_S 16#define FW_PARAMS_PARAM_FILTER_MODE_M 0xffff#define FW_PARAMS_PARAM_FILTER_MODE_V(x) \#define FW_PARAMS_PARAM_FILTER_MODE_G(x) \#define FW_PARAMS_PARAM_FILTER_MASK_S 0#define FW_PARAMS_PARAM_FILTER_MASK_M 0xffff#define FW_PARAMS_PARAM_FILTER_MASK_V(x) \#define FW_PARAMS_PARAM_FILTER_MASK_G(x) \enum fw_params_param_dev {/* chip core clock in khz */ /* the port vector */ /* reads the number of TIDs * allocated by the device's * Lookup Engine /* max supported QP IRD/ORD */ /* max supported adap IRD */ /* * physical and virtual function parameters enum fw_params_param_pfvf {/* Virtual link state as seen by the specified VF */ enum vf_link_states {/* * dma queue parameters enum fw_params_param_dmaq {enum fw_params_param_dev_ktls_hw {enum fw_params_param_dev_phyfw {enum fw_params_param_dev_diag {enum fw_params_param_dev_filter {enum fw_params_param_dev_fwcache {#define FW_PARAMS_MNEM_S 24#define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S)#define FW_PARAMS_PARAM_X_S 16#define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S)#define FW_PARAMS_PARAM_Y_S 8#define FW_PARAMS_PARAM_Y_M 0xffU#define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S)#define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\#define FW_PARAMS_PARAM_Z_S 0#define FW_PARAMS_PARAM_Z_M 0xffu#define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S)#define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\#define FW_PARAMS_PARAM_XYZ_S 0#define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S)#define FW_PARAMS_PARAM_YZ_S 0#define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S)struct fw_params_cmd {struct fw_params_param {#define FW_PARAMS_CMD_PFN_S 8#define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S)#define FW_PARAMS_CMD_VFN_S 0#define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S)struct fw_pfvf_cmd {#define FW_PFVF_CMD_PFN_S 8#define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S)#define FW_PFVF_CMD_VFN_S 0#define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S)#define FW_PFVF_CMD_NIQFLINT_S 20#define FW_PFVF_CMD_NIQFLINT_M 0xfff#define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S)#define FW_PFVF_CMD_NIQFLINT_G(x) \#define FW_PFVF_CMD_NIQ_S 0#define FW_PFVF_CMD_NIQ_M 0xfffff#define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S)#define FW_PFVF_CMD_NIQ_G(x) \#define FW_PFVF_CMD_TYPE_S 31#define FW_PFVF_CMD_TYPE_M 0x1#define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S)#define FW_PFVF_CMD_TYPE_G(x) \#define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U)#define FW_PFVF_CMD_CMASK_S 24#define FW_PFVF_CMD_CMASK_M 0xf#define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S)#define FW_PFVF_CMD_CMASK_G(x) \#define FW_PFVF_CMD_PMASK_S 20#define FW_PFVF_CMD_PMASK_M 0xf#define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S)#define FW_PFVF_CMD_PMASK_G(x) \#define FW_PFVF_CMD_NEQ_S 0#define FW_PFVF_CMD_NEQ_M 0xfffff#define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S)#define FW_PFVF_CMD_NEQ_G(x) \#define FW_PFVF_CMD_TC_S 24#define FW_PFVF_CMD_TC_M 0xff#define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S)#define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)#define FW_PFVF_CMD_NVI_S 16#define FW_PFVF_CMD_NVI_M 0xff#define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S)#define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)#define FW_PFVF_CMD_NEXACTF_S 0#define FW_PFVF_CMD_NEXACTF_M 0xffff#define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S)#define FW_PFVF_CMD_NEXACTF_G(x) \#define FW_PFVF_CMD_R_CAPS_S 24#define FW_PFVF_CMD_R_CAPS_M 0xff#define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)#define FW_PFVF_CMD_R_CAPS_G(x) \#define FW_PFVF_CMD_WX_CAPS_S 16#define FW_PFVF_CMD_WX_CAPS_M 0xff#define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S)#define FW_PFVF_CMD_WX_CAPS_G(x) \#define FW_PFVF_CMD_NETHCTRL_S 0#define FW_PFVF_CMD_NETHCTRL_M 0xffff#define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S)#define FW_PFVF_CMD_NETHCTRL_G(x) \enum fw_iq_type {enum fw_iq_iqtype {struct fw_iq_cmd {#define FW_IQ_CMD_PFN_S 8#define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S)#define FW_IQ_CMD_VFN_S 0#define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S)#define FW_IQ_CMD_ALLOC_S 31#define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S)#define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U)#define FW_IQ_CMD_FREE_S 30#define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S)#define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U)#define FW_IQ_CMD_MODIFY_S 29#define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S)#define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U)#define FW_IQ_CMD_IQSTART_S 28#define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S)#define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U)#define FW_IQ_CMD_IQSTOP_S 27#define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S)#define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U)#define FW_IQ_CMD_TYPE_S 29#define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S)#define FW_IQ_CMD_IQASYNCH_S 28#define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)#define FW_IQ_CMD_VIID_S 16#define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S)#define FW_IQ_CMD_IQANDST_S 15#define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S)#define FW_IQ_CMD_IQANUS_S 14#define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S)#define FW_IQ_CMD_IQANUD_S 12#define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S)#define FW_IQ_CMD_IQANDSTINDEX_S 0#define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S)#define FW_IQ_CMD_IQDROPRSS_S 15#define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S)#define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U)#define FW_IQ_CMD_IQGTSMODE_S 14#define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S)#define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U)#define FW_IQ_CMD_IQPCIECH_S 12#define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)#define FW_IQ_CMD_IQDCAEN_S 11#define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S)#define FW_IQ_CMD_IQDCACPU_S 6#define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)#define FW_IQ_CMD_IQINTCNTTHRESH_S 4#define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)#define FW_IQ_CMD_IQO_S 3#define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S)#define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U)#define FW_IQ_CMD_IQCPRIO_S 2#define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S)#define FW_IQ_CMD_IQESIZE_S 0#define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S)#define FW_IQ_CMD_IQNS_S 31#define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S)#define FW_IQ_CMD_IQRO_S 30#define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S)#define FW_IQ_CMD_IQFLINTIQHSEN_S 28#define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)#define FW_IQ_CMD_IQFLINTCONGEN_S 27#define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)#define FW_IQ_CMD_IQFLINTCONGEN_F FW_IQ_CMD_IQFLINTCONGEN_V(1U)#define FW_IQ_CMD_IQFLINTISCSIC_S 26#define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)#define FW_IQ_CMD_IQTYPE_S 24#define FW_IQ_CMD_IQTYPE_M 0x3#define FW_IQ_CMD_IQTYPE_V(x) ((x) << FW_IQ_CMD_IQTYPE_S)#define FW_IQ_CMD_IQTYPE_G(x) \#define FW_IQ_CMD_FL0CNGCHMAP_S 20#define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)#define FW_IQ_CMD_FL0CACHELOCK_S 15#define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S)#define FW_IQ_CMD_FL0DBP_S 14#define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S)#define FW_IQ_CMD_FL0DATANS_S 13#define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S)#define FW_IQ_CMD_FL0DATARO_S 12#define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S)#define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U)#define FW_IQ_CMD_FL0CONGCIF_S 11#define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S)#define FW_IQ_CMD_FL0CONGCIF_F FW_IQ_CMD_FL0CONGCIF_V(1U)#define FW_IQ_CMD_FL0ONCHIP_S 10#define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S)#define FW_IQ_CMD_FL0STATUSPGNS_S 9#define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)#define FW_IQ_CMD_FL0STATUSPGRO_S 8#define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)#define FW_IQ_CMD_FL0FETCHNS_S 7#define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S)#define FW_IQ_CMD_FL0FETCHRO_S 6#define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S)#define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U)#define FW_IQ_CMD_FL0HOSTFCMODE_S 4#define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)#define FW_IQ_CMD_FL0CPRIO_S 3#define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)#define FW_IQ_CMD_FL0PADEN_S 2#define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)#define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U)#define FW_IQ_CMD_FL0PACKEN_S 1#define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S)#define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U)#define FW_IQ_CMD_FL0CONGEN_S 0#define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S)#define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U)#define FW_IQ_CMD_FL0DCAEN_S 15#define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)#define FW_IQ_CMD_FL0DCACPU_S 10#define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S)#define FW_IQ_CMD_FL0FBMIN_S 7#define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)#define FW_IQ_CMD_FL0FBMAX_S 4#define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)#define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3#define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)#define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)#define FW_IQ_CMD_FL0CIDXFTHRESH_S 0#define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)#define FW_IQ_CMD_FL1CNGCHMAP_S 20#define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)#define FW_IQ_CMD_FL1CACHELOCK_S 15#define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S)#define FW_IQ_CMD_FL1DBP_S 14#define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S)#define FW_IQ_CMD_FL1DATANS_S 13#define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S)#define FW_IQ_CMD_FL1DATARO_S 12#define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S)#define FW_IQ_CMD_FL1CONGCIF_S 11#define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S)#define FW_IQ_CMD_FL1ONCHIP_S 10#define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S)#define FW_IQ_CMD_FL1STATUSPGNS_S 9#define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)#define FW_IQ_CMD_FL1STATUSPGRO_S 8#define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)#define FW_IQ_CMD_FL1FETCHNS_S 7#define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S)#define FW_IQ_CMD_FL1FETCHRO_S 6#define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S)#define FW_IQ_CMD_FL1HOSTFCMODE_S 4#define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)#define FW_IQ_CMD_FL1CPRIO_S 3#define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)#define FW_IQ_CMD_FL1PADEN_S 2#define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)#define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U)#define FW_IQ_CMD_FL1PACKEN_S 1#define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S)#define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U)#define FW_IQ_CMD_FL1CONGEN_S 0#define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S)#define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U)#define FW_IQ_CMD_FL1DCAEN_S 15#define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)#define FW_IQ_CMD_FL1DCACPU_S 10#define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S)#define FW_IQ_CMD_FL1FBMIN_S 7#define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)#define FW_IQ_CMD_FL1FBMAX_S 4#define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)#define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3#define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)#define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)#define FW_IQ_CMD_FL1CIDXFTHRESH_S 0#define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)struct fw_eq_eth_cmd {#define FW_EQ_ETH_CMD_PFN_S 8#define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S)#define FW_EQ_ETH_CMD_VFN_S 0#define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S)#define FW_EQ_ETH_CMD_ALLOC_S 31#define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S)#define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U)#define FW_EQ_ETH_CMD_FREE_S 30#define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)#define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U)#define FW_EQ_ETH_CMD_MODIFY_S 29#define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S)#define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U)#define FW_EQ_ETH_CMD_EQSTART_S 28#define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S)#define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)#define FW_EQ_ETH_CMD_EQSTOP_S 27#define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S)#define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U)#define FW_EQ_ETH_CMD_EQID_S 0#define FW_EQ_ETH_CMD_EQID_M 0xfffff#define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)#define FW_EQ_ETH_CMD_EQID_G(x) \#define FW_EQ_ETH_CMD_PHYSEQID_S 0#define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff#define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)#define FW_EQ_ETH_CMD_PHYSEQID_G(x) \#define FW_EQ_ETH_CMD_FETCHSZM_S 26#define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)#define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U)#define FW_EQ_ETH_CMD_STATUSPGNS_S 25#define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)#define FW_EQ_ETH_CMD_STATUSPGRO_S 24#define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)#define FW_EQ_ETH_CMD_FETCHNS_S 23#define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S)#define FW_EQ_ETH_CMD_FETCHRO_S 22#define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S)#define FW_EQ_ETH_CMD_FETCHRO_F FW_EQ_ETH_CMD_FETCHRO_V(1U)#define FW_EQ_ETH_CMD_HOSTFCMODE_S 20#define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)#define FW_EQ_ETH_CMD_CPRIO_S 19#define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S)#define FW_EQ_ETH_CMD_ONCHIP_S 18#define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S)#define FW_EQ_ETH_CMD_PCIECHN_S 16#define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S)#define FW_EQ_ETH_CMD_IQID_S 0#define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)#define FW_EQ_ETH_CMD_DCAEN_S 31#define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S)#define FW_EQ_ETH_CMD_DCACPU_S 26#define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S)#define FW_EQ_ETH_CMD_FBMIN_S 23#define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S)#define FW_EQ_ETH_CMD_FBMAX_S 20#define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S)#define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19#define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)#define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16#define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)#define FW_EQ_ETH_CMD_EQSIZE_S 0#define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S)#define FW_EQ_ETH_CMD_AUTOEQUIQE_S 31#define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S)#define FW_EQ_ETH_CMD_AUTOEQUIQE_F FW_EQ_ETH_CMD_AUTOEQUIQE_V(1U)#define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30#define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)#define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)#define FW_EQ_ETH_CMD_VIID_S 16#define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)#define FW_EQ_ETH_CMD_TIMEREN_S 3#define FW_EQ_ETH_CMD_TIMEREN_M 0x1#define FW_EQ_ETH_CMD_TIMEREN_V(x) ((x) << FW_EQ_ETH_CMD_TIMEREN_S)#define FW_EQ_ETH_CMD_TIMEREN_G(x) \#define FW_EQ_ETH_CMD_TIMEREN_F FW_EQ_ETH_CMD_TIMEREN_V(1U)#define FW_EQ_ETH_CMD_TIMERIX_S 0#define FW_EQ_ETH_CMD_TIMERIX_M 0x7#define FW_EQ_ETH_CMD_TIMERIX_V(x) ((x) << FW_EQ_ETH_CMD_TIMERIX_S)#define FW_EQ_ETH_CMD_TIMERIX_G(x) \struct fw_eq_ctrl_cmd {#define FW_EQ_CTRL_CMD_PFN_S 8#define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)#define FW_EQ_CTRL_CMD_VFN_S 0#define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)#define FW_EQ_CTRL_CMD_ALLOC_S 31#define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S)#define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U)#define FW_EQ_CTRL_CMD_FREE_S 30#define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S)#define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U)#define FW_EQ_CTRL_CMD_MODIFY_S 29#define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S)#define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U)#define FW_EQ_CTRL_CMD_EQSTART_S 28#define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S)#define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U)#define FW_EQ_CTRL_CMD_EQSTOP_S 27#define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)#define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U)#define FW_EQ_CTRL_CMD_CMPLIQID_S 20#define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)#define FW_EQ_CTRL_CMD_EQID_S 0#define FW_EQ_CTRL_CMD_EQID_M 0xfffff#define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S)#define FW_EQ_CTRL_CMD_EQID_G(x) \
Messung V0.5 C=96 H=92 G=93
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