/* SPDX-License-Identifier: GPL-2.0 */ /* Renesas Ethernet Switch device driver * * Copyright (C) 2022 Renesas Electronics Corporation #ifndef __RSWITCH_H__#define __RSWITCH_H__#include <linux/platform_device.h>#include "rcar_gen4_ptp.h" #define RSWITCH_MAX_NUM_QUEUES 128#define RSWITCH_NUM_AGENTS 5#define RSWITCH_NUM_PORTS 3#define rswitch_for_each_enabled_port(priv, i) \for (i = 0; i < RSWITCH_NUM_PORTS; i++) \if (priv->rdev[i]->disabled) \continue ; \else #define rswitch_for_each_enabled_port_continue_reverse(priv, i) \for (; i-- > 0; ) \if (priv->rdev[i]->disabled) \continue ; \else #define TX_RING_SIZE 1024#define RX_RING_SIZE 4096#define TS_RING_SIZE (TX_RING_SIZE * RSWITCH_NUM_PORTS)#define RSWITCH_MAX_MTU 9600#define RSWITCH_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN)#define RSWITCH_DESC_BUF_SIZE 2048#define RSWITCH_TAILROOM SKB_DATA_ALIGN(sizeof (struct skb_shared_info))#define RSWITCH_ALIGN 128#define RSWITCH_BUF_SIZE (RSWITCH_HEADROOM + RSWITCH_DESC_BUF_SIZE + \#define RSWITCH_MAP_BUF_SIZE (RSWITCH_BUF_SIZE - RSWITCH_HEADROOM)#define RSWITCH_MAX_CTAG_PCP 7#define RSWITCH_TIMEOUT_US 100000#define RSWITCH_TOP_OFFSET 0x00008000#define RSWITCH_COMA_OFFSET 0x00009000#define RSWITCH_ETHA_OFFSET 0x0000a000 /* with RMAC */ #define RSWITCH_ETHA_SIZE 0x00002000 /* with RMAC */ #define RSWITCH_GWCA0_OFFSET 0x00010000#define RSWITCH_GWCA1_OFFSET 0x00012000/* TODO: hardcoded ETHA/GWCA settings for now */ #define GWCA_IRQ_RESOURCE_NAME "gwca0_rxtx%d" #define GWCA_IRQ_NAME "rswitch: gwca0_rxtx%d" #define GWCA_NUM_IRQS 8#define GWCA_INDEX 0#define AGENT_INDEX_GWCA 3#define GWCA_IPV_NUM 0#define GWRO RSWITCH_GWCA0_OFFSET#define GWCA_TS_IRQ_RESOURCE_NAME "gwca0_rxts0" #define GWCA_TS_IRQ_NAME "rswitch: gwca0_rxts0" #define GWCA_TS_IRQ_BIT BIT(0)#define FWRO 0#define TPRO RSWITCH_TOP_OFFSET#define CARO RSWITCH_COMA_OFFSET#define TARO 0#define RMRO 0x1000enum rswitch_reg {/* ETHA/RMAC */ enum rswitch_etha_mode {#define EAMS_OPS_MASK EAMC_OPC_OPERATION#define EAVCC_VEM_SC_TAG (0x3 << 16)#define MPIC_PIS GENMASK(2, 0)#define MPIC_PIS_GMII 2#define MPIC_PIS_XGMII 4#define MPIC_LSC GENMASK(5, 3)#define MPIC_LSC_100M 1#define MPIC_LSC_1G 2#define MPIC_LSC_2_5G 3#define MPIC_PSMCS GENMASK(22, 16)#define MPIC_PSMHT GENMASK(26, 24)#define MPSM_PSME BIT(0)#define MPSM_MFF BIT(2)#define MPSM_MMF_C22 0#define MPSM_MMF_C45 1#define MPSM_PDA GENMASK(7, 3)#define MPSM_PRA GENMASK(12, 8)#define MPSM_POP GENMASK(14, 13)#define MPSM_POP_ADDRESS 0#define MPSM_POP_WRITE 1#define MPSM_POP_READ_C22 2#define MPSM_POP_READ_C45 3#define MPSM_PRD GENMASK(31, 16)#define MLVC_PLV BIT(16)/* GWCA */ enum rswitch_gwca_mode {#define GWMS_OPS_MASK GWMC_OPC_OPERATION#define GWMTIRM_MTIOG BIT(0)#define GWMTIRM_MTR BIT(1)#define GWVCC_VEM_SC_TAG (0x3 << 16)#define GWARIRM_ARIOG BIT(0)#define GWARIRM_ARR BIT(1)#define GWMDNC_TSDMN(num) (((num) << 16) & GENMASK(17, 16))#define GWMDNC_TXDMN(num) (((num) << 8) & GENMASK(12, 8))#define GWMDNC_RXDMN(num) ((num) & GENMASK(4, 0))#define GWDCC_BALR BIT(24)#define GWDCC_DCP_MASK GENMASK(18, 16)#define GWDCC_DCP(prio) FIELD_PREP(GWDCC_DCP_MASK, (prio))#define GWDCC_DQT BIT(11)#define GWDCC_ETS BIT(9)#define GWDCC_EDE BIT(8)#define GWTRC(queue) (GWTRC0 + (queue) / 32 * 4)#define GWTPC_PPPL(ipv) BIT(ipv)#define GWDCC_OFFS(queue) (GWDCC0 + (queue) * 4)#define GWDIS(i) (GWDIS0 + (i) * 0x10)#define GWDIE(i) (GWDIE0 + (i) * 0x10)#define GWDID(i) (GWDID0 + (i) * 0x10)/* COMA */ #define RRC_RR BIT(0)#define RRC_RR_CLR 0#define RCEC_ACE_DEFAULT (BIT(0) | BIT(AGENT_INDEX_GWCA))#define RCEC_RCE BIT(16)#define RCDC_RCD BIT(16)#define CABPIRM_BPIOG BIT(0)#define CABPIRM_BPR BIT(1)#define CABPPFLC_INIT_VALUE 0x00800080/* MFWD */ #define FWPC0(i) (FWPC00 + (i) * 0x10)#define FWPC0_LTHTA BIT(0)#define FWPC0_IP4UE BIT(3)#define FWPC0_IP4TE BIT(4)#define FWPC0_IP4OE BIT(5)#define FWPC0_L2SE BIT(9)#define FWPC0_IP4EA BIT(10)#define FWPC0_IPDSA BIT(12)#define FWPC0_IPHLA BIT(18)#define FWPC0_MACSDA BIT(20)#define FWPC0_MACHLA BIT(26)#define FWPC0_MACHMA BIT(27)#define FWPC0_VLANSA BIT(28)#define FWPC1(i) (FWPC10 + (i) * 0x10)#define FWCP1_LTHFW GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)#define FWPC1_DDE BIT(0)#define FWPC2(i) (FWPC20 + (i) * 0x10)#define FWCP2_LTWFW GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)#define FWPBFC(i) (FWPBFC0 + (i) * 0x10)#define FWPBFC_PBDV GENMASK(RSWITCH_NUM_AGENTS - 1, 0)#define FWPBFCSDC(j, i) (FWPBFCSDC00 + (i) * 0x10 + (j) * 0x04)/* TOP */ #define TPEMIMC7(queue) (TPEMIMC70 + (queue) * 4)/* Descriptors */ enum RX_DS_CC_BIT {/* Data size */ /* Truncation indication */ /* Error indication */ /* Padding selection */ enum TX_DS_TAGL_BIT {/* Data size */ /* Frame tag LSBs */ enum DIE_DT {/* Frame data */ /* Chain control */ /* HW/SW arbitration */ /* Descriptor Interrupt Enable */ /* Both transmission and reception */ #define INFO1_FMT BIT(2)#define INFO1_TXC BIT(3)/* For transmission */ #define INFO1_TSUN(val) ((u64)(val) << 8ULL)#define INFO1_IPV(prio) ((u64)(prio) << 28ULL)#define INFO1_CSD0(index) ((u64)(index) << 32ULL)#define INFO1_CSD1(index) ((u64)(index) << 40ULL)#define INFO1_DV(port_vector) ((u64)(port_vector) << 48ULL)/* For reception */ #define INFO1_SPN(port) ((u64)(port) << 36ULL)/* For timestamp descriptor in dptrl (Byte 4 to 7) */ #define TS_DESC_TSUN(dptrl) ((dptrl) & GENMASK(7, 0))#define TS_DESC_SPN(dptrl) (((dptrl) & GENMASK(10, 8)) >> 8)#define TS_DESC_DPN(dptrl) (((dptrl) & GENMASK(17, 16)) >> 16)#define TS_DESC_TN(dptrl) ((dptrl) & BIT(24))struct rswitch_desc {/* Descriptor size */ /* Descriptor interrupt enable and type */ /* Descriptor pointer MSB */ /* Descriptor pointer LSW */ struct rswitch_ts_desc {struct rswitch_desc desc;struct rswitch_ext_desc {struct rswitch_desc desc;struct rswitch_ext_ts_desc {struct rswitch_desc desc;struct rswitch_etha {unsigned int index;void __iomem *addr;void __iomem *coma_addr;bool external_phy;struct mii_bus *mii;int link;int speed;/* This hardware could not be initialized twice so that marked * this flag to avoid multiple initialization. bool operated;/* The datasheet said descriptor "chain" and/or "queue". For consistency of * name, this driver calls "queue". struct rswitch_gwca_queue {union {struct rswitch_ext_desc *tx_ring;struct rswitch_ext_ts_desc *rx_ring;struct rswitch_ts_desc *ts_ring;/* Common */ unsigned int ring_size;unsigned int cur;unsigned int dirty;/* For [rt]x_ring */ unsigned int index;bool dir_tx;struct net_device *ndev; /* queue to ndev for irq */ union {/* For TX */ struct {struct sk_buff **skbs;/* For RX */ struct {void **rx_bufs;struct sk_buff *skb_fstart;#define RSWITCH_NUM_IRQ_REGS (RSWITCH_MAX_NUM_QUEUES / BITS_PER_TYPE(u32))struct rswitch_gwca {unsigned int index;struct rswitch_desc *linkfix_table;struct rswitch_gwca_queue *queues;int num_queues;struct rswitch_gwca_queue ts_queue;#define NUM_QUEUES_PER_NDEV 2#define TS_TAGS_PER_PORT 256struct rswitch_device {struct rswitch_private *priv;struct net_device *ndev;struct napi_struct napi;void __iomem *addr;struct rswitch_gwca_queue *tx_queue;struct rswitch_gwca_queue *rx_queue;struct sk_buff *ts_skb[TS_TAGS_PER_PORT];bool disabled;int port;struct rswitch_etha *etha;struct device_node *np_port;struct phy *serdes;struct rswitch_mfwd_mac_table_entry {int queue_index;unsigned char addr[MAX_ADDR_LEN];struct rswitch_mfwd {struct rswitch_mac_table_entry *mac_table_entries;int num_mac_table_entries;struct rswitch_private {struct platform_device *pdev;void __iomem *addr;struct rcar_gen4_ptp_private *ptp_priv;struct rswitch_device *rdev[RSWITCH_NUM_PORTS];struct rswitch_gwca gwca;struct rswitch_etha etha[RSWITCH_NUM_PORTS];struct rswitch_mfwd mfwd;/* lock interrupt registers' control */ struct clk *clk;bool etha_no_runtime_change;bool gwca_halt;#endif /* #ifndef __RSWITCH_H__ */
Messung V0.5 C=96 H=91 G=93
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