/* SPDX-License-Identifier: GPL-2.0 */ /* Renesas Ethernet-TSN device driver * * Copyright (C) 2022 Renesas Electronics Corporation * Copyright (C) 2023 Niklas Söderlund <niklas.soderlund@ragnatech.se> #ifndef __RTSN_H__#define __RTSN_H__#include <linux/types.h>#define AXIBMI 0x0000#define TSNMHD 0x1000#define RMSO 0x2000#define RMRO 0x3800enum rtsn_reg {/* AXIBMI */ #define RR_RATRR BIT(0)#define RR_TATRR BIT(1)#define RR_RST (RR_RATRR | RR_TATRR)#define RR_RST_COMPLETE 0x03#define AXIWC_DEFAULT 0xffff#define AXIRC_DEFAULT 0xffff#define TATLS0_TEDE BIT(1)#define TATLS0_TATEN_SHIFT 24#define TATLS0_TATEN(n) ((n) << TATLS0_TATEN_SHIFT)#define TATLR_TATL BIT(31)#define RATLS0_RETS BIT(2)#define RATLS0_REDE BIT(3)#define RATLS0_RATEN_SHIFT 24#define RATLS0_RATEN(n) ((n) << RATLS0_RATEN_SHIFT)#define RATLR_RATL BIT(31)#define DIE_DID_TDICX(n) BIT((n))#define DIE_DID_RDICX(n) BIT((n) + 8)#define TDIE_TDID_TDX(n) BIT(n)#define RDIE_RDID_RDX(n) BIT(n)#define TDIS_TDS(n) BIT(n)#define RDIS_RDS(n) BIT(n)/* MHD */ #define OSR_OPS 0x07#define SWR_SWR BIT(0)#define TGC1_TQTM_SFM 0xff00#define TGC1_STTV_DEFAULT 0x03#define TMS_MFS_MAX 0x2800/* RMAC System */ #define CFCR_SDID(n) ((n) << 16)#define FMSCR_FMSIE(n) ((n) << 0)/* RMAC */ #define MPIC_PIS_MASK GENMASK(1, 0)#define MPIC_PIS_MII 0#define MPIC_PIS_RMII 0x01#define MPIC_PIS_GMII 0x02#define MPIC_PIS_RGMII 0x03#define MPIC_LSC_SHIFT 2#define MPIC_LSC_MASK GENMASK(3, MPIC_LSC_SHIFT)#define MPIC_LSC_10M (0 << MPIC_LSC_SHIFT)#define MPIC_LSC_100M (0x01 << MPIC_LSC_SHIFT)#define MPIC_LSC_1G (0x02 << MPIC_LSC_SHIFT)#define MPIC_PSMCS_SHIFT 16#define MPIC_PSMCS_MASK GENMASK(21, MPIC_PSMCS_SHIFT)#define MPIC_PSMCS_DEFAULT (0x0a << MPIC_PSMCS_SHIFT)#define MPIC_PSMHT_SHIFT 24#define MPIC_PSMHT_MASK GENMASK(26, MPIC_PSMHT_SHIFT)#define MPIC_PSMHT_DEFAULT (0x07 << MPIC_PSMHT_SHIFT)#define MLVC_PASE BIT(8)#define MLVC_PSE BIT(16)#define MLVC_PLV BIT(17)#define MPSM_PSME BIT(0)#define MPSM_PSMAD BIT(1)#define MPSM_PDA_SHIFT 3#define MPSM_PDA_MASK GENMASK(7, 3)#define MPSM_PDA(n) (((n) << MPSM_PDA_SHIFT) & MPSM_PDA_MASK)#define MPSM_PRA_SHIFT 8#define MPSM_PRA_MASK GENMASK(12, 8)#define MPSM_PRA(n) (((n) << MPSM_PRA_SHIFT) & MPSM_PRA_MASK)#define MPSM_PRD_SHIFT 16#define MPSM_PRD_SET(n) ((n) << MPSM_PRD_SHIFT)#define MPSM_PRD_GET(n) ((n) >> MPSM_PRD_SHIFT)#define GPOUT_RDM BIT(13)#define GPOUT_TDM BIT(14)/* RTSN */ #define RTSN_INTERVAL_US 1000#define RTSN_TIMEOUT_US 1000000#define TX_NUM_CHAINS 1#define RX_NUM_CHAINS 1#define TX_CHAIN_SIZE 1024#define RX_CHAIN_SIZE 1024#define TX_CHAIN_IDX 0#define RX_CHAIN_IDX 0#define TX_CHAIN_ADDR_OFFSET (sizeof (struct rtsn_desc) * TX_CHAIN_IDX)#define RX_CHAIN_ADDR_OFFSET (sizeof (struct rtsn_desc) * RX_CHAIN_IDX)#define PKT_BUF_SZ 1584#define RTSN_ALIGN 128enum rtsn_mode {/* Descriptors */ enum RX_DS_CC_BIT {/* Data size */ /* Truncation indication */ /* Error indication */ /* Padding selection */ enum TX_FS_TAGL_BIT {/* Data size */ /* Frame tag LSBs */ enum DIE_DT {/* HW/SW arbitration */ /* Frame data */ /* Chain control */ struct rtsn_desc {struct rtsn_ts_desc {struct rtsn_ext_desc {struct rtsn_ext_ts_desc {enum EXT_INFO_DS_BIT {#endif
Messung V0.5 C=99 H=99 G=98
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