// SPDX-License-Identifier: GPL-2.0 // Copyright (C) 2018 Microchip Technology #include <linux/kernel.h>#include <linux/module.h>#include <linux/delay.h>#include <linux/mii.h>#include <linux/phy.h>#include <linux/sort.h>#include <linux/ethtool.h>#include <linux/ethtool_netlink.h>#include <linux/bitfield.h>#include "microchip_rds_ptp.h" #define PHY_ID_LAN87XX 0x0007c150#define PHY_ID_LAN937X 0x0007c180#define PHY_ID_LAN887X 0x0007c1f0#define MCHP_RDS_PTP_LTC_BASE_ADDR 0xe000#define MCHP_RDS_PTP_PORT_BASE_ADDR (MCHP_RDS_PTP_LTC_BASE_ADDR + 0x800)/* External Register Control Register */ #define LAN87XX_EXT_REG_CTL (0x14)#define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)#define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)#define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8)#define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)/* External Register Read Data Register */ #define LAN87XX_EXT_REG_RD_DATA (0x15)/* External Register Write Data Register */ #define LAN87XX_EXT_REG_WR_DATA (0x16)/* Interrupt Source Register */ #define LAN87XX_INTERRUPT_SOURCE (0x18)#define LAN87XX_INTERRUPT_SOURCE_2 (0x08)/* Interrupt Mask Register */ #define LAN87XX_INTERRUPT_MASK (0x19)#define LAN87XX_MASK_LINK_UP (0x0004)#define LAN87XX_MASK_LINK_DOWN (0x0002)#define LAN87XX_INTERRUPT_MASK_2 (0x09)#define LAN87XX_MASK_COMM_RDY BIT(10)/* MISC Control 1 Register */ #define LAN87XX_CTRL_1 (0x11)#define LAN87XX_MASK_RGMII_TXC_DLY_EN (0x4000)#define LAN87XX_MASK_RGMII_RXC_DLY_EN (0x2000)/* phyaccess nested types */ #define PHYACC_ATTR_MODE_READ 0#define PHYACC_ATTR_MODE_WRITE 1#define PHYACC_ATTR_MODE_MODIFY 2#define PHYACC_ATTR_MODE_POLL 3#define PHYACC_ATTR_BANK_SMI 0#define PHYACC_ATTR_BANK_MISC 1#define PHYACC_ATTR_BANK_PCS 2#define PHYACC_ATTR_BANK_AFE 3#define PHYACC_ATTR_BANK_DSP 4#define PHYACC_ATTR_BANK_MAX 7/* measurement defines */ #define LAN87XX_CABLE_TEST_OK 0#define LAN87XX_CABLE_TEST_OPEN 1#define LAN87XX_CABLE_TEST_SAME_SHORT 2/* T1 Registers */ #define T1_AFE_PORT_CFG1_REG 0x0B#define T1_POWER_DOWN_CONTROL_REG 0x1A#define T1_SLV_FD_MULT_CFG_REG 0x18#define T1_CDR_CFG_PRE_LOCK_REG 0x05#define T1_CDR_CFG_POST_LOCK_REG 0x06#define T1_LCK_STG2_MUFACT_CFG_REG 0x1A#define T1_LCK_STG3_MUFACT_CFG_REG 0x1B#define T1_POST_LCK_MUFACT_CFG_REG 0x1C#define T1_TX_RX_FIFO_CFG_REG 0x02#define T1_TX_LPF_FIR_CFG_REG 0x55#define T1_COEF_CLK_PWR_DN_CFG 0x04#define T1_COEF_RW_CTL_CFG 0x0D#define T1_SQI_CONFIG_REG 0x2E#define T1_SQI_CONFIG2_REG 0x4A#define T1_DCQ_SQI_REG 0xC3#define T1_DCQ_SQI_MSK GENMASK(3, 1)#define T1_MDIO_CONTROL2_REG 0x10#define T1_INTERRUPT_SOURCE_REG 0x18#define T1_INTERRUPT2_SOURCE_REG 0x08#define T1_EQ_FD_STG1_FRZ_CFG 0x69#define T1_EQ_FD_STG2_FRZ_CFG 0x6A#define T1_EQ_FD_STG3_FRZ_CFG 0x6B#define T1_EQ_FD_STG4_FRZ_CFG 0x6C#define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D#define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E#define T1_MODE_STAT_REG 0x11#define T1_LINK_UP_MSK BIT(0)/* SQI defines */ #define LAN87XX_MAX_SQI 0x07/* Chiptop registers */ #define LAN887X_PMA_EXT_ABILITY_2 0x12#define LAN887X_PMA_EXT_ABILITY_2_1000T1 BIT(1)#define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0)/* DSP 100M registers */ #define LAN887x_CDR_CONFIG1_100 0x0405#define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411#define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417#define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c#define LAN887x_PROT_DISABLE_100 0x0425#define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454/* DSP 1000M registers */ #define LAN887X_LOCK1_EQLSR_CONFIG 0x0811#define LAN887X_LOCK3_EQLSR_CONFIG 0x0813#define LAN887X_PROT_DISABLE 0x0825#define LAN887X_FFE_GAIN6 0x0843#define LAN887X_FFE_GAIN7 0x0844#define LAN887X_FFE_GAIN8 0x0845#define LAN887X_FFE_GAIN9 0x0846#define LAN887X_ECHO_DELAY_CONFIG 0x08ec#define LAN887X_FFE_MAX_CONFIG 0x08ee/* PCS 1000M registers */ #define LAN887X_SCR_CONFIG_3 0x8043#define LAN887X_INFO_FLD_CONFIG_5 0x8048/* T1 afe registers */ #define LAN887X_ZQCAL_CONTROL_1 0x8080#define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089#define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b#define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d#define LAN887X_TX_AMPLT_1000T1_REG 0x80b0#define LAN887X_INIT_COEFF_DFE1_100 0x0422/* PMA registers */ #define LAN887X_DSP_PMA_CONTROL 0x810e#define LAN887X_DSP_PMA_CONTROL_LNK_SYNC BIT(4)/* PCS 100M registers */ #define LAN887X_IDLE_ERR_TIMER_WIN 0x8204#define LAN887X_IDLE_ERR_CNT_THRESH 0x8213/* Misc registers */ #define LAN887X_REG_REG26 0x001a#define LAN887X_REG_REG26_HW_INIT_SEQ_EN BIT(8)/* Mis registers */ #define LAN887X_MIS_CFG_REG0 0xa00#define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS BIT(5)#define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0)#define LAN887X_MAC_MODE_RGMII 0x01#define LAN887X_MAC_MODE_SGMII 0x03#define LAN887X_MIS_DLL_CFG_REG0 0xa01#define LAN887X_MIS_DLL_CFG_REG1 0xa02#define LAN887X_MIS_DLL_DELAY_EN BIT(15)#define LAN887X_MIS_DLL_EN BIT(0)#define LAN887X_MIS_DLL_CONF (LAN887X_MIS_DLL_DELAY_EN |\#define LAN887X_MIS_CFG_REG2 0xa03#define LAN887X_MIS_CFG_REG2_FE_LPBK_EN BIT(2)#define LAN887X_MIS_PKT_STAT_REG0 0xa06#define LAN887X_MIS_PKT_STAT_REG1 0xa07#define LAN887X_MIS_PKT_STAT_REG3 0xa09#define LAN887X_MIS_PKT_STAT_REG4 0xa0a#define LAN887X_MIS_PKT_STAT_REG5 0xa0b#define LAN887X_MIS_PKT_STAT_REG6 0xa0c/* Chiptop common registers */ #define LAN887X_COMMON_LED3_LED2 0xc05#define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0)#define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0/* MX chip top registers */ #define LAN887X_CHIP_HARD_RST 0xf03e#define LAN887X_CHIP_HARD_RST_RESET BIT(0)#define LAN887X_CHIP_SOFT_RST 0xf03f#define LAN887X_CHIP_SOFT_RST_RESET BIT(0)#define LAN887X_SGMII_CTL 0xf01a#define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0)#define LAN887X_SGMII_PCS_CFG 0xf034#define LAN887X_SGMII_PCS_CFG_PCS_ENA BIT(9)#define LAN887X_EFUSE_READ_DAT9 0xf209#define LAN887X_EFUSE_READ_DAT9_SGMII_DIS BIT(9)#define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0)#define LAN887X_CALIB_CONFIG_100 0x437#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL BIT(5)#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE BIT(4)#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE BIT(3)#define LAN887X_CALIB_CONFIG_100_VAL \#define LAN887X_MAX_PGA_GAIN_100 0x44f#define LAN887X_MIN_PGA_GAIN_100 0x450#define LAN887X_START_CBL_DIAG_100 0x45a#define LAN887X_CBL_DIAG_DONE BIT(1)#define LAN887X_CBL_DIAG_START BIT(0)#define LAN887X_CBL_DIAG_STOP 0x0#define LAN887X_CBL_DIAG_TDR_THRESH_100 0x45b#define LAN887X_CBL_DIAG_AGC_THRESH_100 0x45c#define LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100 0x45d#define LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100 0x45e#define LAN887X_CBL_DIAG_CYC_CONFIG_100 0x45f#define LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100 0x460#define LAN887X_CBL_DIAG_MIN_PGA_GAIN_100 0x462#define LAN887X_CBL_DIAG_AGC_GAIN_100 0x497#define LAN887X_CBL_DIAG_POS_PEAK_VALUE_100 0x499#define LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100 0x49a#define LAN887X_CBL_DIAG_POS_PEAK_TIME_100 0x49c#define LAN887X_CBL_DIAG_NEG_PEAK_TIME_100 0x49d#define MICROCHIP_CABLE_NOISE_MARGIN 20#define MICROCHIP_CABLE_TIME_MARGIN 89#define MICROCHIP_CABLE_MIN_TIME_DIFF 96#define MICROCHIP_CABLE_MAX_TIME_DIFF \#define LAN887X_INT_STS 0xf000#define LAN887X_INT_MSK 0xf001#define LAN887X_INT_MSK_P1588_MOD_INT_MSK BIT(3)#define LAN887X_INT_MSK_T1_PHY_INT_MSK BIT(2)#define LAN887X_INT_MSK_LINK_UP_MSK BIT(1)#define LAN887X_INT_MSK_LINK_DOWN_MSK BIT(0)#define LAN887X_MX_CHIP_TOP_REG_CONTROL1 0xF002#define LAN887X_MX_CHIP_TOP_REG_CONTROL1_EVT_EN BIT(8)#define LAN887X_MX_CHIP_TOP_LINK_MSK (LAN887X_INT_MSK_LINK_UP_MSK |\#define LAN887X_MX_CHIP_TOP_ALL_MSK (LAN887X_INT_MSK_T1_PHY_INT_MSK |\#define LAN887X_COEFF_PWR_DN_CONFIG_100 0x0404#define LAN887X_COEFF_PWR_DN_CONFIG_100_V 0x16d6#define LAN887X_SQI_CONFIG_100 0x042e#define LAN887X_SQI_CONFIG_100_V 0x9572#define LAN887X_SQI_MSE_100 0x483#define LAN887X_POKE_PEEK_100 0x040d#define LAN887X_POKE_PEEK_100_EN BIT(0)#define LAN887X_COEFF_MOD_CONFIG 0x080d#define LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN BIT(8)#define LAN887X_DCQ_SQI_STATUS 0x08b2/* SQI raw samples count */ #define SQI_SAMPLES 200/* Samples percentage considered for SQI calculation */ #define SQI_INLINERS_PERCENT 60/* Samples count considered for SQI calculation */ #define SQI_INLIERS_NUM (SQI_SAMPLES * SQI_INLINERS_PERCENT / 100)/* Start offset of samples */ #define SQI_INLIERS_START ((SQI_SAMPLES - SQI_INLIERS_NUM) / 2)/* End offset of samples */ #define SQI_INLIERS_END (SQI_INLIERS_START + SQI_INLIERS_NUM)#define DRIVER_AUTHOR "Nisar Sayed " #define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver" /* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok) * TEST_MODE_HYBRID: Hybrid results to calculate distance to fault enum cable_diag_mode {/* CD_TEST_INIT: Cable test is initated * CD_TEST_DONE: Cable test is done enum cable_diag_state {struct access_ereg_val {struct lan887x_hw_stat {const char *string;static const struct lan887x_hw_stat lan887x_hw_stats[] = {"TX Good Count" , MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},"RX Good Count" , MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},"RX ERR Count detected by PCS" , MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},"TX CRC ERR Count" , MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},"RX CRC ERR Count" , MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},"RX ERR Count for SGMII MII2GMII" , MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},struct lan887x_regwr_map {struct lan887x_priv {struct mchp_rds_ptp_clock *clock;bool init_done;static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank)int rc = 0;/* Read previous selected bank */ if (rc < 0)goto out_unlock;/* store the prev_bank */ if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {/* access twice for DSP bank change,dummy access */ return rc;static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,int rc = 0;if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX)return -EINVAL;if (bank == PHYACC_ATTR_BANK_SMI) {if (mode == PHYACC_ATTR_MODE_WRITE)else return rc;if (mode == PHYACC_ATTR_MODE_WRITE) {if (rc < 0)return rc;else {/* DSP bank access workaround for lan937x */ if (phydev->phy_id == PHY_ID_LAN937X) {if (rc < 0)return rc;if (rc < 0)return rc;if (mode == PHYACC_ATTR_MODE_READ)return rc;static int access_ereg_modify_changed(struct phy_device *phydev,int new = 0, rc = 0;if (bank > PHYACC_ATTR_BANK_MAX)return -EINVAL;if (rc < 0)return rc;new = val | (rc & (mask ^ 0xFFFF));new );return rc;static int access_smi_poll_timeout(struct phy_device *phydev,int val;return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr,true );static int lan87xx_config_rgmii_delay(struct phy_device *phydev)int rc;if (!phy_interface_is_rgmii(phydev))return 0;if (rc < 0)return rc;switch (phydev->interface) {case PHY_INTERFACE_MODE_RGMII:break ;case PHY_INTERFACE_MODE_RGMII_ID:break ;case PHY_INTERFACE_MODE_RGMII_RXID:break ;case PHY_INTERFACE_MODE_RGMII_TXID:break ;default :return 0;return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,static int lan87xx_phy_init_cmd(struct phy_device *phydev,const struct access_ereg_val *cmd_seq, int cnt)int ret, i;for (i = 0; i < cnt; i++) {if (cmd_seq[i].mode == PHYACC_ATTR_MODE_POLL &&else {if (ret < 0)return ret;return ret;static int lan87xx_phy_init(struct phy_device *phydev)static const struct access_ereg_val hw_init[] = {/* TXPD/TXAMP6 Configs */ /* HW_Init Hi and Force_ED */ static const struct access_ereg_val slave_init[] = {/* Equalizer Full Duplex Freeze - T1 Slave */ static const struct access_ereg_val phy_init[] = {/* Slave Full Duplex Multi Configs */ /* CDR Pre and Post Lock Configs */ /* Lock Stage 2-3 Multi Factor Config */ /* Pointer delay */ /* Tx iir edits */ /* Setup SQI measurement */ /* SQI enable */ /* SQI select mode 5 */ /* Throws the first SQI reading */ /* Flag LPS and WUR as idle errors */ /* HW_Init toggle, undo force ED, TXPD off */ /* Reset PCS to trigger hardware initialization */ /* Poll till Hardware is initialized */ /* Tx AMP - 0x06 */ /* Read INTERRUPT_SOURCE Register */ /* Read INTERRUPT_SOURCE Register */ /* HW_Init Hi */ int rc;/* phy Soft reset */ if (rc < 0)return rc;/* PHY Initialization */ if (rc < 0)return rc;if (rc)return rc;/* The following squence needs to run only if phydev is in * slave mode. if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE) {if (rc < 0)return rc;if (rc < 0)return rc;return lan87xx_config_rgmii_delay(phydev);static int lan87xx_phy_config_intr(struct phy_device *phydev)int rc, val = 0;if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {/* clear all interrupt */ if (rc < 0)return rc;if (rc < 0)return rc;if (rc < 0)return rc;if (rc < 0)return rc;/* enable link down and comm ready interrupt */ if (rc < 0)return rc;else {if (rc < 0)return rc;if (rc < 0)return rc;if (rc < 0)return rc;return rc < 0 ? rc : 0;static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev)int irq_status;if (irq_status < 0) {return IRQ_NONE;if (irq_status < 0) {return IRQ_NONE;if (irq_status == 0)return IRQ_NONE;return IRQ_HANDLED;static int lan87xx_config_init(struct phy_device *phydev)int rc = lan87xx_phy_init(phydev);return rc < 0 ? rc : 0;static int microchip_cable_test_start_common(struct phy_device *phydev)int bmcr, bmsr, ret;/* If auto-negotiation is enabled, but not complete, the cable * test never completes. So disable auto-neg. if (bmcr < 0)return bmcr;if (bmsr < 0)return bmsr;if (bmcr & BMCR_ANENABLE) {if (ret < 0)return ret;if (ret < 0)return ret;/* If the link is up, allow it some time to go down */ if (bmsr & BMSR_LSTATUS)return 0;static int lan87xx_cable_test_start(struct phy_device *phydev)static const struct access_ereg_val cable_test[] = {/* min wait */ /* max wait */ /* pulse cycle */ /* cable diag thresh */ /* max gain */ /* clock align for each iteration */ /* max cycle wait config */ /* start cable diag*/ int rc, i;if (rc < 0)return rc;/* start cable diag */ /* check if part is alive - if not, return diagnostic error */ if (rc < 0)return rc;/* master/slave specific configs */ if (rc < 0)return rc;if ((rc & 0x4000) != 0x4000) {/* DUT is Slave */ if (rc < 0)return rc;if (rc < 0)return rc;else {/* DUT is Master */ if (rc < 0)return rc;for (i = 0; i < ARRAY_SIZE(cable_test); i++) {if (cable_test[i].mode == PHYACC_ATTR_MODE_MODIFY) {/* wait 50ms */ else {if (rc < 0)return rc;/* cable diag started */ return 0;static int lan87xx_cable_test_report_trans(u32 result)switch (result) {case LAN87XX_CABLE_TEST_OK:return ETHTOOL_A_CABLE_RESULT_CODE_OK;case LAN87XX_CABLE_TEST_OPEN:return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;case LAN87XX_CABLE_TEST_SAME_SHORT:return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;default :/* DIAGNOSTIC_ERROR */ return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;static int lan87xx_cable_test_report(struct phy_device *phydev)int pos_peak_cycle = 0, pos_peak_in_phases = 0, pos_peak_phase = 0;int neg_peak_cycle = 0, neg_peak_in_phases = 0, neg_peak_phase = 0;int noise_margin = 20, time_margin = 89, jitter_var = 30;int min_time_diff = 96, max_time_diff = 96 + time_margin;bool fault = false , check_a = false , check_b = false ;int gain_idx = 0, pos_peak = 0, neg_peak = 0;int pos_peak_time = 0, neg_peak_time = 0;int pos_peak_in_phases_hybrid = 0;int detect = -1;/* read non-hybrid results */ /* calculate non-hybrid values */ /* process values */ if (pos_peak_in_phases > neg_peak_in_phases && check_a)else if ((neg_peak_in_phases > pos_peak_in_phases) && check_b)if (pos_peak > noise_margin && neg_peak > noise_margin &&if (detect == 1 || detect == 2)true ;if (!fault)return phy_init_hw(phydev);static int lan87xx_cable_test_get_status(struct phy_device *phydev,bool *finished)int rc = 0;false ;/* check if cable diag was finished */ if (rc < 0)return rc;if ((rc & 2) == 2) {/* stop cable diag*/ if (rc < 0)return rc;true ;return lan87xx_cable_test_report(phydev);return 0;static int lan87xx_read_status(struct phy_device *phydev)int rc = 0;if (rc < 0)return rc;if (rc & T1_LINK_UP_MSK)else if (rc < 0)return rc;if (rc < 0)return rc;return rc;static int lan87xx_config_aneg(struct phy_device *phydev)int ret;switch (phydev->master_slave_set) {case MASTER_SLAVE_CFG_MASTER_FORCE:break ;case MASTER_SLAVE_CFG_SLAVE_FORCE:break ;case MASTER_SLAVE_CFG_UNKNOWN:case MASTER_SLAVE_CFG_UNSUPPORTED:return 0;default :"Unsupported Master/Slave mode\n" );return -EOPNOTSUPP;if (ret == 1)return phy_init_hw(phydev);return ret;static int lan87xx_get_sqi(struct phy_device *phydev)int rc;if (rc < 0)return rc;if (rc < 0)return rc;return sqi_value;static int lan87xx_get_sqi_max(struct phy_device *phydev)return LAN87XX_MAX_SQI;static int lan887x_rgmii_init(struct phy_device *phydev)int ret;/* SGMII mux disable */ if (ret < 0)return ret;/* Select MAC_MODE as RGMII */ if (ret < 0)return ret;/* Disable PCS */ if (ret < 0)return ret;/* LAN887x Errata: RGMII rx clock active in SGMII mode * Disabled it for SGMII mode * Re-enabling it for RGMII mode return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,static int lan887x_sgmii_init(struct phy_device *phydev)int ret;/* SGMII mux enable */ if (ret < 0)return ret;/* Select MAC_MODE as SGMII */ if (ret < 0)return ret;/* LAN887x Errata: RGMII rx clock active in SGMII mode. * So disabling it for SGMII mode if (ret < 0)return ret;/* Enable PCS */ return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,static int lan887x_config_rgmii_en(struct phy_device *phydev)int txc;int rxc;int ret;if (ret < 0)return ret;/* Control bit to enable/disable TX DLL delay line in signal path */ if (txc < 0)return txc;/* Control bit to enable/disable RX DLL delay line in signal path */ if (rxc < 0)return rxc;/* Configures the phy to enable RX/TX delay * RGMII - TX & RX delays are either added by MAC or not needed, * phy should not add * RGMII_ID - Configures phy to enable TX & RX delays, MAC shouldn't add * RGMII_RX_ID - Configures the PHY to enable the RX delay. * The MAC shouldn't add the RX delay * RGMII_TX_ID - Configures the PHY to enable the TX delay. * The MAC shouldn't add the TX delay in this case switch (phydev->interface) {case PHY_INTERFACE_MODE_RGMII:break ;case PHY_INTERFACE_MODE_RGMII_ID:break ;case PHY_INTERFACE_MODE_RGMII_RXID:break ;case PHY_INTERFACE_MODE_RGMII_TXID:break ;default :"Invalid phydev interface %d\n" , phydev->interface);return 0;/* Configures the PHY to enable/disable RX delay in signal path */ if (ret < 0)return ret;/* Configures the PHY to enable/disable the TX delay in signal path */ return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0,static int lan887x_config_phy_interface(struct phy_device *phydev)int interface_mode;int sgmii_dis;int ret;/* Read sku efuse data for interfaces supported by sku */ if (ret < 0)return ret;/* If interface_mode is 1 then efuse sets RGMII operations. * If interface mode is 3 then efuse sets SGMII operations. /* SGMII disable is set for RGMII operations */ switch (phydev->interface) {case PHY_INTERFACE_MODE_RGMII:case PHY_INTERFACE_MODE_RGMII_ID:case PHY_INTERFACE_MODE_RGMII_RXID:case PHY_INTERFACE_MODE_RGMII_TXID:/* Reject RGMII settings for SGMII only sku */ if (!((interface_mode & LAN887X_MAC_MODE_SGMII) ==break ;case PHY_INTERFACE_MODE_SGMII:/* Reject SGMII setting for RGMII only sku */ if (!sgmii_dis)break ;default :/* Reject setting for unsupported interfaces */ return ret;static int lan887x_get_features(struct phy_device *phydev)int ret;if (ret < 0)return ret;/* Enable twisted pair */ /* First patch only supports 100Mbps and 1000Mbps force-mode. * T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later. return 0;static int lan887x_phy_init(struct phy_device *phydev)struct lan887x_priv *priv = phydev->priv;int ret;if (!priv->init_done && phy_interrupt_is_valid(phydev)) {if (IS_ERR(priv->clock))return PTR_ERR(priv->clock);/* Enable pin mux for EVT */ /* Initialize pin numbers specific to PEROUT */ true ;/* Clear loopback */ if (ret < 0)return ret;/* Configure default behavior of led to link and activity for any * speed if (ret < 0)return ret;/* PHY interface setup */ return lan887x_config_phy_interface(phydev);static int lan887x_phy_config(struct phy_device *phydev,const struct lan887x_regwr_map *reg_map, int cnt)int ret;for (int i = 0; i < cnt; i++) {if (ret < 0)return ret;return 0;static int lan887x_phy_setup(struct phy_device *phydev)static const struct lan887x_regwr_map phy_cfg[] = {/* PORT_AFE writes */ /* 100T1_PCS_VENDOR writes */ /* 100T1 DSP writes */ /* 1000T1 DSP writes */ /* 1000T1 PCS writes */ return lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));static int lan887x_100M_setup(struct phy_device *phydev)int ret;/* (Re)configure the speed/mode dependent T1 settings */ if (phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_FORCE ||static const struct lan887x_regwr_map phy_cfg[] = {else {static const struct lan887x_regwr_map phy_cfg[] = {if (ret < 0)return ret;return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,static int lan887x_1000M_setup(struct phy_device *phydev)static const struct lan887x_regwr_map phy_cfg[] = {int ret;/* (Re)configure the speed/mode dependent T1 settings */ if (ret < 0)return ret;return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,static int lan887x_link_setup(struct phy_device *phydev)int ret = -EINVAL;if (phydev->speed == SPEED_1000)else if (phydev->speed == SPEED_100)return ret;/* LAN887x Errata: speed configuration changes require soft reset * and chip soft reset static int lan887x_phy_reset(struct phy_device *phydev)int ret, val;/* Clear 1000M link sync */ if (ret < 0)return ret;/* Clear 100M link sync */ if (ret < 0)return ret;/* Chiptop soft-reset to allow the speed/mode change */ if (ret < 0)return ret;/* CL22 soft-reset to let the link re-train */ if (ret < 0)return ret;/* Wait for reset complete or timeout if > 10ms */ return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),true );static int lan887x_phy_reconfig(struct phy_device *phydev)int ret;if (ret < 0)return ret;return lan887x_link_setup(phydev);static int lan887x_config_aneg(struct phy_device *phydev)int ret;/* LAN887x Errata: speed configuration changes require soft reset * and chip soft reset if (ret < 0)return ret;return lan887x_phy_reconfig(phydev);static int lan887x_probe(struct phy_device *phydev)struct lan887x_priv *priv;sizeof (*priv), GFP_KERNEL);if (!priv)return -ENOMEM;false ;return lan887x_phy_setup(phydev);static u64 lan887x_get_stat(struct phy_device *phydev, int i)struct lan887x_hw_stat stat = lan887x_hw_stats[i];struct lan887x_priv *priv = phydev->priv;int val;if (stat.mmd)else if (val < 0) {else {return ret;static void lan887x_get_stats(struct phy_device *phydev,struct ethtool_stats *stats, u64 *data)for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)static int lan887x_get_sset_count(struct phy_device *phydev)return ARRAY_SIZE(lan887x_hw_stats);static void lan887x_get_strings(struct phy_device *phydev, u8 *data)for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)static int lan887x_config_intr(struct phy_device *phydev)struct lan887x_priv *priv = phydev->priv;int rc;if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {/* Clear the interrupt status before enabling interrupts */ if (rc < 0)return rc;/* Unmask for enabling interrupt */ else {if (rc < 0)return rc;if (rc < 0)return rc;if (phy_is_default_hwtstamp(phydev)) {return mchp_rds_ptp_top_config_intr(priv->clock,return 0;static irqreturn_t lan887x_handle_interrupt(struct phy_device *phydev)struct lan887x_priv *priv = phydev->priv;int rc = IRQ_NONE;int irq_status;if (irq_status < 0) {return IRQ_NONE;if (irq_status & LAN887X_MX_CHIP_TOP_LINK_MSK) {if (irq_status & LAN887X_INT_MSK_P1588_MOD_INT_MSK)return rc;static int lan887x_cd_reset(struct phy_device *phydev,enum cable_diag_state cd_done)int rc;/* Chip hard-reset */ if (rc < 0)return rc;/* Wait for reset to complete */ true );if (rc < 0)return rc;if (cd_done == CD_TEST_DONE) {/* Cable diagnostics complete. Restore PHY. */ if (rc < 0)return rc;if (rc < 0)return rc;if (rc < 0)return rc;if (rc < 0)return rc;return 0;static int lan887x_cable_test_prep(struct phy_device *phydev,enum cable_diag_mode mode)static const struct lan887x_regwr_map values[] = {int rc;if (rc < 0)return rc;/* Forcing DUT to master mode, as we don't care about * mode during diagnostics if (rc < 0)return rc;if (rc < 0)return rc;if (rc < 0)return rc;for (int i = 0; i < ARRAY_SIZE(values); i++) {if (rc < 0)return rc;if (mode &&if (rc < 0)return rc;if (mode == TEST_MODE_HYBRID) {if (rc < 0)return rc;/* HW_INIT 100T1, Get DUT running in 100T1 mode */ if (rc < 0)return rc;/* Cable diag requires hard reset and is sensitive regarding the delays. * Hard reset is expected into and out of cable diag. * Wait for 50ms /* Start cable diag */ return phy_write_mmd(phydev, MDIO_MMD_VEND1,static int lan887x_cable_test_chk(struct phy_device *phydev,enum cable_diag_mode mode)int val;int rc;if (mode == TEST_MODE_HYBRID) {/* Cable diag requires hard reset and is sensitive regarding the delays. * Hard reset is expected into and out of cable diag. * Wait for cable diag to complete. * Minimum wait time is 50ms if the condition is not a match. false );if (rc < 0)return rc;else {if (rc < 0)return rc;if ((rc & LAN887X_CBL_DIAG_DONE) != LAN887X_CBL_DIAG_DONE)return -EAGAIN;/* Stop cable diag */ return phy_write_mmd(phydev, MDIO_MMD_VEND1,static int lan887x_cable_test_start(struct phy_device *phydev)int rc, ret;if (rc < 0) {if (ret < 0)return ret;return rc;return 0;static int lan887x_cable_test_report(struct phy_device *phydev)int pos_peak_cycle, pos_peak_cycle_hybrid, pos_peak_in_phases;int pos_peak_time, pos_peak_time_hybrid, neg_peak_time;int neg_peak_cycle, neg_peak_in_phases;int pos_peak_in_phases_hybrid;int gain_idx, gain_idx_hybrid;int pos_peak_phase_hybrid;int pos_peak, neg_peak;int distance;int detect;int length;int ret;int rc;/* Read non-hybrid results */ if (gain_idx < 0) {goto error;if (pos_peak < 0) {goto error;if (neg_peak < 0) {goto error;if (pos_peak_time < 0) {goto error;if (neg_peak_time < 0) {goto error;/* Calculate non-hybrid values */ /* Deriving the status of cable */ if (pos_peak > MICROCHIP_CABLE_NOISE_MARGIN &&if (pos_peak_in_phases > neg_peak_in_phases &&else if (neg_peak_in_phases > pos_peak_in_phases &&else {else {if (detect == LAN87XX_CABLE_TEST_OK) {goto get_len;/* Re-initialize PHY and start cable diag test */ if (rc < 0)goto cd_stop;/* Wait for cable diag test completion */ if (rc < 0)goto cd_stop;/* Read hybrid results */ if (gain_idx_hybrid < 0) {goto error;if (pos_peak_time_hybrid < 0) {goto error;/* Calculate hybrid values to derive cable length to fault */ /* Distance to fault calculation. * distance = (peak_in_phases - peak_in_phases_hybrid) * * propagationconstant. * constant to convert number of phases to meters * propagationconstant = 0.015953 * (0.6811 * 2.9979 * 156.2499 * 0.0001 * 0.5) * Applying constant 1.5953 as ethtool further devides by 100 to * convert to meters. if (detect == LAN87XX_CABLE_TEST_OPEN) {else if (detect == LAN87XX_CABLE_TEST_SAME_SHORT) {else {if (rc < 0)return rc;return 0;/* Stop cable diag */ if (ret < 0)return ret;/* Cable diag test failed */ if (ret < 0)return ret;/* Return error in failure case */ return rc;static int lan887x_cable_test_get_status(struct phy_device *phydev,bool *finished)int rc;if (rc < 0) {/* Let PHY statemachine poll again */ if (rc == -EAGAIN)return 0;return rc;/* Cable diag test complete */ true ;/* Retrieve test status and cable length to fault */ return lan887x_cable_test_report(phydev);/* Compare block to sort in ascending order */ static int sqi_compare(const void *a, const void *b)return *(u16 *)a - *(u16 *)b;static int lan887x_get_sqi_100M(struct phy_device *phydev)int rc, i;/* Configuration of SQI 100M */ if (rc < 0)return rc;if (rc < 0)return rc;if (rc != LAN887X_SQI_CONFIG_100_V)return -EINVAL;if (rc < 0)return rc;/* Required before reading register * otherwise it will return high value /* Link check before raw readings */ if (rc < 0)return rc;if (!phydev->link)return -ENETDOWN;/* Get 200 SQI raw readings */ for (i = 0; i < SQI_SAMPLES; i++) {if (rc < 0)return rc;if (rc < 0)return rc;/* Link check after raw readings */ if (rc < 0)return rc;if (!phydev->link)return -ENETDOWN;/* Sort SQI raw readings in ascending order */ sizeof (u16), sqi_compare, NULL);/* Keep inliers and discard outliers */ for (i = SQI_INLIERS_START; i < SQI_INLIERS_END; i++)/* Handle invalid samples */ if (sqiavg != 0) {/* Get SQI average */ if (sqiavg < 75)else if (sqiavg < 94)else if (sqiavg < 119)else if (sqiavg < 150)else if (sqiavg < 189)else if (sqiavg < 237)else if (sqiavg < 299)else return sqinum;static int lan887x_get_sqi(struct phy_device *phydev)int rc, val;if (phydev->speed != SPEED_1000 &&return -ENETDOWN;if (phydev->speed == SPEED_100)return lan887x_get_sqi_100M(phydev);/* Writing DCQ_COEFF_EN to trigger a SQI read */ if (rc < 0)return rc;/* Wait for DCQ done */ true );if (rc < 0)return rc;if (rc < 0)return rc;return FIELD_GET(T1_DCQ_SQI_MSK, rc);static struct phy_driver microchip_t1_phy_driver[] = {"Microchip LAN87xx T1" ,"Microchip LAN937x T1" ,"Microchip LAN887x T1 PHY" ,static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {"GPL" );
Messung V0.5 C=97 H=94 G=95
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¤ *© Formatika GbR, Deutschland
