/* SPDX-License-Identifier: ISC */ /* * Copyright (c) 2005-2011 Atheros Communications Inc. * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. * Copyright (c) 2018, The Linux Foundation. All rights reserved. * Copyright (c) 2021, 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/* This command is used for sending management frames in HTT < 3.0. * HTT >= 3.0 uses TX_FRM for everything.
*/
HTT_H2T_MSG_TYPE_MGMT_TX = 7,
HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11,
/* * HTT tx MSDU descriptor * * The HTT tx MSDU descriptor is created by the host HTT SW for each * tx MSDU. The HTT tx MSDU descriptor contains the information that * the target firmware needs for the FW's tx processing, particularly * for creating the HW msdu descriptor. * The same HTT tx descriptor is used for HL and LL systems, though * a few fields within the tx descriptor are used only by LL or * only by HL. * The HTT tx descriptor is defined in two manners: by a struct with * bitfields, and by a series of [dword offset, bit mask, bit shift] * definitions. * The target should use the struct def, for simplicity and clarity, * but the host shall use the bit-mast + bit-shift defs, to be endian- * neutral. Specifically, the host shall use the get/set macros built * around the mask + shift defs.
*/ struct htt_data_tx_desc_frag { union { struct double_word_addr {
__le32 paddr;
__le32 len;
} __packed dword_addr; struct triple_word_addr {
__le32 paddr_lo;
__le16 paddr_hi;
__le16 len_16;
} __packed tword_addr;
} __packed;
} __packed;
/* * htt_data_tx_desc - used for data tx path * * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1. * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_ * for special kinds of tids * postponed: only for HL hosts. indicates if this is a resend * (HL hosts manage queues on the host ) * more_in_batch: only for HL hosts. indicates if more packets are * pending. this allows target to wait and aggregate * freq: 0 means home channel of given vdev. intended for offchannel
*/ struct htt_data_tx_desc {
u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
__le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
__le16 len;
__le16 id;
__le32 frags_paddr; union {
__le32 peerid; struct {
__le16 peerid;
__le16 freq;
} __packed offchan_tx;
} __packed;
u8 prefetch[0]; /* start of frame, for FW classification engine */
} __packed;
/* * htt_stats_req - request target to send specified statistics * * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually * so make sure its little-endian. * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually * so make sure its little-endian. * @cfg_val: stat_type specific configuration * @stat_type: see %htt_dbg_stats_type * @cookie_lsb: used for confirmation message from target->host * @cookie_msb: ditto as %cookie
*/ struct htt_stats_req {
u8 upload_types[3];
u8 rsvd0;
u8 reset_types[3]; struct {
u8 mpdu_bytes;
u8 mpdu_num_msdus;
u8 msdu_bytes;
} __packed;
u8 stat_type;
__le32 cookie_lsb;
__le32 cookie_msb;
} __packed;
/* * htt_oob_sync_req - request out-of-band sync * * The HTT SYNC tells the target to suspend processing of subsequent * HTT host-to-target messages until some other target agent locally * informs the target HTT FW that the current sync counter is equal to * or greater than (in a modulo sense) the sync counter specified in * the SYNC message. * * This allows other host-target components to synchronize their operation * with HTT, e.g. to ensure that tx frames don't get transmitted until a * security key has been downloaded to and activated by the target. * In the absence of any explicit synchronization counter value * specification, the target HTT FW will use zero as the default current * sync value. * * The HTT target FW will suspend its host->target message processing as long * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128.
*/ struct htt_oob_sync_req {
u8 sync_count;
__le16 rsvd0;
} __packed;
struct htt_aggr_conf {
u8 max_num_ampdu_subframes; /* amsdu_subframes is limited by 0x1F mask */
u8 max_num_amsdu_subframes;
} __packed;
struct htt_aggr_conf_v2 {
u8 max_num_ampdu_subframes; /* amsdu_subframes is limited by 0x1F mask */
u8 max_num_amsdu_subframes;
u8 reserved;
} __packed;
/* * htt_rx_flush - discard or reorder given range of mpdus * * Note: host must check if all sequence numbers between * [seq_num_start, seq_num_end-1] are valid.
*/ struct htt_rx_flush {
__le16 peer_id;
u8 tid;
u8 rsvd0;
u8 mpdu_status; /* %htt_rx_flush_mpdu_status */
u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */
u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */
};
/* * @brief target -> host TX completion indication message definition * * @details * The following diagram shows the format of the TX completion indication sent * from the target to the host * * |31 28|27|26|25|24|23 16| 15 |14 11|10 8|7 0| * |-------------------------------------------------------------| * header: |rsvd |A2|TP|A1|A0| num | t_i| tid |status| msg_type | * |-------------------------------------------------------------| * payload: | MSDU1 ID | MSDU0 ID | * |-------------------------------------------------------------| * : MSDU3 ID : MSDU2 ID : * |-------------------------------------------------------------| * | struct htt_tx_compl_ind_append_retries | * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| * | struct htt_tx_compl_ind_append_tx_tstamp | * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| * | MSDU1 ACK RSSI | MSDU0 ACK RSSI | * |-------------------------------------------------------------| * : MSDU3 ACK RSSI : MSDU2 ACK RSSI : * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -| * -msg_type * Bits 7:0 * Purpose: identifies this as HTT TX completion indication * -status * Bits 10:8 * Purpose: the TX completion status of payload fragmentations descriptors * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD * -tid * Bits 14:11 * Purpose: the tid associated with those fragmentation descriptors. It is * valid or not, depending on the tid_invalid bit. * Value: 0 to 15 * -tid_invalid * Bits 15:15 * Purpose: this bit indicates whether the tid field is valid or not * Value: 0 indicates valid, 1 indicates invalid * -num * Bits 23:16 * Purpose: the number of payload in this indication * Value: 1 to 255 * -A0 = append * Bits 24:24 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains * the number of tx retries for one MSDU at the end of this message * Value: 0 indicates no appending, 1 indicates appending * -A1 = append1 * Bits 25:25 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which * contains the timestamp info for each TX msdu id in payload. * Value: 0 indicates no appending, 1 indicates appending * -TP = MSDU tx power presence * Bits 26:26 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report * for each MSDU referenced by the TX_COMPL_IND message. * The order of the per-MSDU tx power reports matches the order * of the MSDU IDs. * Value: 0 indicates not appending, 1 indicates appending * -A2 = append2 * Bits 27:27 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report * matches the order of the MSDU IDs. * The ACK RSSI values are valid when status is COMPLETE_OK (and * this append2 bit is set). * Value: 0 indicates not appending, 1 indicates appending
*/
/* * target -> host test message definition * * The following field definitions describe the format of the test * message sent from the target to the host. * The message consists of a 4-octet header, followed by a variable * number of 32-bit integer values, followed by a variable number * of 8-bit character values. * * |31 16|15 8|7 0| * |-----------------------------------------------------------| * | num chars | num ints | msg type | * |-----------------------------------------------------------| * | int 0 | * |-----------------------------------------------------------| * | int 1 | * |-----------------------------------------------------------| * | ... | * |-----------------------------------------------------------| * | char 3 | char 2 | char 1 | char 0 | * |-----------------------------------------------------------| * | | | ... | char 4 | * |-----------------------------------------------------------| * - MSG_TYPE * Bits 7:0 * Purpose: identifies this as a test message * Value: HTT_MSG_TYPE_TEST * - NUM_INTS * Bits 15:8 * Purpose: indicate how many 32-bit integers follow the message header * - NUM_CHARS * Bits 31:16 * Purpose: indicate how many 8-bit characters follow the series of integers
*/ struct htt_rx_test {
u8 num_ints;
__le16 num_chars;
/* payload consists of 2 lists: * a) num_ints * sizeof(__le32) * b) num_chars * sizeof(u8) aligned to 4bytes
*/
u8 payload[];
} __packed;
/* * target -> host packet log message * * The following field definitions describe the format of the packet log * message sent from the target to the host. * The message consists of a 4-octet header,followed by a variable number * of 32-bit character values. * * |31 24|23 16|15 8|7 0| * |-----------------------------------------------------------| * | | | | msg type | * |-----------------------------------------------------------| * | payload | * |-----------------------------------------------------------| * - MSG_TYPE * Bits 7:0 * Purpose: identifies this as a test message * Value: HTT_MSG_TYPE_PACKETLOG
*/ struct htt_pktlog_msg {
u8 pad[3];
u8 payload[];
} __packed;
struct htt_dbg_stats_rx_reorder_stats { /* Non QoS MPDUs received */
__le32 deliver_non_qos;
/* MPDUs received in-order */
__le32 deliver_in_order;
/* Flush due to reorder timer expired */
__le32 deliver_flush_timeout;
/* Flush due to move out of window */
__le32 deliver_flush_oow;
/* Flush due to DELBA */
__le32 deliver_flush_delba;
/* MPDUs dropped due to FCS error */
__le32 fcs_error;
/* MPDUs dropped due to monitor mode non-data packet */
__le32 mgmt_ctrl;
/* MPDUs dropped due to invalid peer */
__le32 invalid_peer;
/* MPDUs dropped due to duplication (non aggregation) */
__le32 dup_non_aggr;
/* MPDUs dropped due to processed before */
__le32 dup_past;
/* MPDUs dropped due to duplicate in reorder queue */
__le32 dup_in_reorder;
/* * htt_dbg_stats_status - * present - The requested stats have been delivered in full. * This indicates that either the stats information was contained * in its entirety within this message, or else this message * completes the delivery of the requested stats info that was * partially delivered through earlier STATS_CONF messages. * partial - The requested stats have been delivered in part. * One or more subsequent STATS_CONF messages with the same * cookie value will be sent to deliver the remainder of the * information. * error - The requested stats could not be delivered, for example due * to a shortage of memory to construct a message holding the * requested stats. * invalid - The requested stat type is either not recognized, or the * target is configured to not gather the stats type in question. * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * series_done - This special value indicates that no further stats info * elements are present within a series of stats info elems * (within a stats upload confirmation message).
*/ enum htt_dbg_stats_status {
HTT_DBG_STATS_STATUS_PRESENT = 0,
HTT_DBG_STATS_STATUS_PARTIAL = 1,
HTT_DBG_STATS_STATUS_ERROR = 2,
HTT_DBG_STATS_STATUS_INVALID = 3,
HTT_DBG_STATS_STATUS_SERIES_DONE = 7
};
/* * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank * * The following field definitions describe the format of the HTT host * to target frag_desc/msdu_ext bank configuration message. * The message contains the based address and the min and max id of the * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and * MSDU_EXT/FRAG_DESC. * HTT will use id in HTT descriptor instead sending the frag_desc_ptr. * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0 * the hardware does the mapping/translation. * * Total banks that can be configured is configured to 16. * * This should be called before any TX has be initiated by the HTT * * |31 16|15 8|7 5|4 0| * |------------------------------------------------------------| * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type | * |------------------------------------------------------------| * | BANK0_BASE_ADDRESS | * |------------------------------------------------------------| * | ... | * |------------------------------------------------------------| * | BANK15_BASE_ADDRESS | * |------------------------------------------------------------| * | BANK0_MAX_ID | BANK0_MIN_ID | * |------------------------------------------------------------| * | ... | * |------------------------------------------------------------| * | BANK15_MAX_ID | BANK15_MIN_ID | * |------------------------------------------------------------| * Header fields: * - MSG_TYPE * Bits 7:0 * Value: 0x6 * - BANKx_BASE_ADDRESS * Bits 31:0 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT * bank physical/bus address. * - BANKx_MIN_ID * Bits 15:0 * Purpose: Provide a mechanism to specify the min index that needs to * mapped. * - BANKx_MAX_ID * Bits 31:16 * Purpose: Provide a mechanism to specify the max index that needs to *
*/ struct htt_frag_desc_bank_id {
__le16 bank_min_id;
__le16 bank_max_id;
} __packed;
/* real is 16 but it wouldn't fit in the max htt message size * so we use a conservatively safe value for now
*/ #define HTT_FRAG_DESC_BANK_MAX 4
/** * struct htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config * * Defines host q state format and behavior. See htt_q_state. * * @paddr: Queue physical address * @num_peers: Number of supported peers * @num_tids: Number of supported TIDs * @record_size: Defines the size of each host q entry in bytes. In practice * however firmware (at least 10.4.3-00191) ignores this host * configuration value and uses hardcoded value of 1. * @record_multiplier: This is valid only when q depth type is MSDUs. It * defines the exponent for the power of 2 multiplication. * @pad: struct padding for 32-bit alignment
*/ struct htt_q_state_conf {
__le32 paddr;
__le16 num_peers;
__le16 num_tids;
u8 record_size;
u8 record_multiplier;
u8 pad[2];
} __packed;
/** * struct htt_q_state - shared between host and firmware via DMA * * This structure is used for the host to expose it's software queue state to * firmware so that its rate control can schedule fetch requests for optimized * performance. This is most notably used for MU-MIMO aggregation when multiple * MU clients are connected. * * @count: Each element defines the host queue depth. When q depth type was * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as: * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 ** * record_multiplier (see htt_q_state_conf). * @map: Used by firmware to quickly check which host queues are not empty. It * is a bitmap simply saying. * @seq: Used by firmware to quickly check if the host queues were updated * since it last checked. * * FIXME: Is the q_state map[] size calculation really correct?
*/ struct htt_q_state {
u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS];
u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32];
__le32 seq;
} __packed;
struct { /* * Ring of network buffer objects - This ring is * used exclusively by the host SW. This ring * mirrors the dev_addrs_ring that is shared * between the host SW and the MAC HW. The host SW * uses this netbufs ring to locate the network * buffer objects whose data buffers the HW has * filled.
*/ struct sk_buff **netbufs_ring;
/* This is used only with firmware supporting IN_ORD_IND. * * With Full Rx Reorder the HTT Rx Ring is more of a temporary * buffer ring from which buffer addresses are copied by the * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND * pointing to specific (re-ordered) buffers. * * FIXME: With kernel generic hashing functions there's a lot * of hash collisions for sk_buffs.
*/ bool in_ord_rx;
DECLARE_HASHTABLE(skb_table, 4);
/* * Ring of buffer addresses - * This ring holds the "physical" device address of the * rx buffers the host SW provides for the MAC HW to * fill.
*/ union {
__le64 *paddrs_ring_64;
__le32 *paddrs_ring_32;
};
/* * Base address of ring, as a "physical" device address * rather than a CPU address.
*/
dma_addr_t base_paddr;
/* how many elems in the ring (power of 2) */ int size;
/* size - 1 */ unsignedint size_mask;
/* how many rx buffers to keep in the ring */ int fill_level;
/* how many rx buffers (full+empty) are in the ring */ int fill_cnt;
/* * alloc_idx - where HTT SW has deposited empty buffers * This is allocated in consistent mem, so that the FW can * read this variable, and program the HW's FW_IDX reg with * the value of this shadow register.
*/ struct {
__le32 *vaddr;
dma_addr_t paddr;
} alloc_idx;
/* where HTT SW has processed bufs filled by rx MAC DMA */ struct { unsignedint msdu_payld;
} sw_rd_idx;
/* * refill_retry_timer - timer triggered when the ring is * not refilled to the level expected
*/ struct timer_list refill_retry_timer;
/* Protects access to all rx ring buffer state variables */
spinlock_t lock;
} rx_ring;
unsignedint prefetch_len;
/* Protects access to pending_tx, num_pending_tx */
spinlock_t tx_lock; int max_num_pending_tx; int num_pending_tx; int num_pending_mgmt_tx; struct idr pending_tx;
wait_queue_head_t empty_tx_wq;
/* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */
DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done);
/* set if host-fw communication goes haywire * used to avoid further failures
*/ bool rx_confused;
atomic_t num_mpdus_ready;
/* This is used to group tx/rx completions separately and process them * in batches to reduce cache stalls
*/ struct sk_buff_head rx_msdus_q; struct sk_buff_head rx_in_ord_compl_q; struct sk_buff_head tx_fetch_ind_q;
/* the driver strongly assumes that the rx header status be 64 bytes long, * so all possible rx_desc structures must respect this assumption.
*/ #define RX_HTT_HDR_STATUS_LEN 64
/* The rx descriptor structure layout is programmed via rx ring setup * so that FW knows how to transfer the rx descriptor to the host. * Unfortunately, though, QCA6174's firmware doesn't currently behave correctly * when modifying the structure layout of the rx descriptor beyond what it expects * (even if it correctly programmed during the rx ring setup). * Therefore we must keep two different memory layouts, abstract the rx descriptor * representation and use ath10k_rx_desc_ops * for correctly accessing rx descriptor data.
*/
/* base struct used for abstracting the rx descriptor representation */ struct htt_rx_desc { union { /* This field is filled on the host using the msdu buffer * from htt_rx_indication
*/ struct fw_rx_desc_base fw_desc;
u32 pad;
} __packed;
} __packed;
/* rx descriptor for wcn3990 and possibly extensible for newer cards * Buffers like this are placed on the rx ring.
*/ struct htt_rx_desc_v2 { struct htt_rx_desc base; struct { struct rx_attention attention; struct rx_frag_info frag_info; struct rx_mpdu_start mpdu_start; struct rx_msdu_start msdu_start; struct rx_msdu_end msdu_end; struct rx_mpdu_end mpdu_end; struct rx_ppdu_start ppdu_start; struct rx_ppdu_end ppdu_end;
} __packed;
u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN];
u8 msdu_payload[];
};
/* QCA6174, QCA988x, QCA99x0 dedicated rx descriptor to make sure their firmware * works correctly. We keep a single rx descriptor for all these three * families of cards because from tests it seems to be the most stable solution, * e.g. having a rx descriptor only for QCA6174 seldom caused firmware crashes * during some tests. * Buffers like this are placed on the rx ring.
*/ struct htt_rx_desc_v1 { struct htt_rx_desc base; struct { struct rx_attention attention; struct rx_frag_info_v1 frag_info; struct rx_mpdu_start mpdu_start; struct rx_msdu_start_v1 msdu_start; struct rx_msdu_end_v1 msdu_end; struct rx_mpdu_end mpdu_end; struct rx_ppdu_start ppdu_start; struct rx_ppdu_end_v1 ppdu_end;
} __packed;
u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN];
u8 msdu_payload[];
};
/* rx_desc abstraction */ struct ath10k_htt_rx_desc_ops { /* These fields are mandatory, they must be specified in any instance */
/* sizeof() of the rx_desc structure used by this hw */
size_t rx_desc_size;
/* offset of msdu_payload inside the rx_desc structure used by this hw */
size_t rx_desc_msdu_payload_offset;
/* These fields are options. * When a field is not provided the default implementation gets used * (see the ath10k_rx_desc_* operations below for more info about the defaults)
*/ bool (*rx_desc_get_msdu_limit_error)(struct htt_rx_desc *rxd); int (*rx_desc_get_l3_pad_bytes)(struct htt_rx_desc *rxd);
/* Safely cast from a void* buffer containing an rx descriptor * to the proper rx_desc structure
*/ struct htt_rx_desc *(*rx_desc_from_raw_buffer)(void *buff);
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