/* * Copyright (c) 2008-2011 Atheros Communications Inc. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. #ifndef REG_H#define REG_H#include "../reg.h" #define AR_CR 0x0008#define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)#define AR_CR_RXD 0x00000020#define AR_CR_SWI 0x00000040#define AR_RXDP 0x000C#define AR_CFG 0x0014#define AR_CFG_SWTD 0x00000001#define AR_CFG_SWTB 0x00000002#define AR_CFG_SWRD 0x00000004#define AR_CFG_SWRB 0x00000008#define AR_CFG_SWRG 0x00000010#define AR_CFG_AP_ADHOC_INDICATION 0x00000020#define AR_CFG_PHOK 0x00000100#define AR_CFG_EEBS 0x00000200#define AR_CFG_CLK_GATE_DIS 0x00000400#define AR_CFG_HALT_REQ 0x00000800#define AR_CFG_HALT_ACK 0x00001000#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17#define AR_RXBP_THRESH 0x0018#define AR_RXBP_THRESH_HP 0x0000000f#define AR_RXBP_THRESH_HP_S 0#define AR_RXBP_THRESH_LP 0x00003f00#define AR_RXBP_THRESH_LP_S 8#define AR_MIRT 0x0020#define AR_MIRT_VAL 0x0000ffff#define AR_MIRT_VAL_S 16#define AR_IER 0x0024#define AR_IER_ENABLE 0x00000001#define AR_IER_DISABLE 0x00000000#define AR_TIMT 0x0028#define AR_TIMT_LAST 0x0000ffff#define AR_TIMT_LAST_S 0#define AR_TIMT_FIRST 0xffff0000#define AR_TIMT_FIRST_S 16#define AR_RIMT 0x002C#define AR_RIMT_LAST 0x0000ffff#define AR_RIMT_LAST_S 0#define AR_RIMT_FIRST 0xffff0000#define AR_RIMT_FIRST_S 16#define AR_DMASIZE_4B 0x00000000#define AR_DMASIZE_8B 0x00000001#define AR_DMASIZE_16B 0x00000002#define AR_DMASIZE_32B 0x00000003#define AR_DMASIZE_64B 0x00000004#define AR_DMASIZE_128B 0x00000005#define AR_DMASIZE_256B 0x00000006#define AR_DMASIZE_512B 0x00000007#define AR_TXCFG 0x0030#define AR_TXCFG_DMASZ_MASK 0x00000007#define AR_TXCFG_DMASZ_4B 0#define AR_TXCFG_DMASZ_8B 1#define AR_TXCFG_DMASZ_16B 2#define AR_TXCFG_DMASZ_32B 3#define AR_TXCFG_DMASZ_64B 4#define AR_TXCFG_DMASZ_128B 5#define AR_TXCFG_DMASZ_256B 6#define AR_TXCFG_DMASZ_512B 7#define AR_FTRIG 0x000003F0#define AR_FTRIG_S 4#define AR_FTRIG_IMMED 0x00000000#define AR_FTRIG_64B 0x00000010#define AR_FTRIG_128B 0x00000020#define AR_FTRIG_192B 0x00000030#define AR_FTRIG_256B 0x00000040#define AR_FTRIG_512B 0x00000080#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800#define AR_RXCFG 0x0034#define AR_RXCFG_CHIRP 0x00000008#define AR_RXCFG_ZLFDMA 0x00000010#define AR_RXCFG_DMASZ_MASK 0x00000007#define AR_RXCFG_DMASZ_4B 0#define AR_RXCFG_DMASZ_8B 1#define AR_RXCFG_DMASZ_16B 2#define AR_RXCFG_DMASZ_32B 3#define AR_RXCFG_DMASZ_64B 4#define AR_RXCFG_DMASZ_128B 5#define AR_RXCFG_DMASZ_256B 6#define AR_RXCFG_DMASZ_512B 7#define AR_TOPS 0x0044#define AR_TOPS_MASK 0x0000FFFF#define AR_RXNPTO 0x0048#define AR_RXNPTO_MASK 0x000003FF#define AR_TXNPTO 0x004C#define AR_TXNPTO_MASK 0x000003FF#define AR_TXNPTO_QCU_MASK 0x000FFC00#define AR_RPGTO 0x0050#define AR_RPGTO_MASK 0x000003FF#define AR_RPCNT 0x0054#define AR_RPCNT_MASK 0x0000001F#define AR_MACMISC 0x0058#define AR_MACMISC_PCI_EXT_FORCE 0x00000010#define AR_MACMISC_DMA_OBS 0x000001E0#define AR_MACMISC_DMA_OBS_S 5#define AR_MACMISC_DMA_OBS_LINE_0 0#define AR_MACMISC_DMA_OBS_LINE_1 1#define AR_MACMISC_DMA_OBS_LINE_2 2#define AR_MACMISC_DMA_OBS_LINE_3 3#define AR_MACMISC_DMA_OBS_LINE_4 4#define AR_MACMISC_DMA_OBS_LINE_5 5#define AR_MACMISC_DMA_OBS_LINE_6 6#define AR_MACMISC_DMA_OBS_LINE_7 7#define AR_MACMISC_DMA_OBS_LINE_8 8#define AR_MACMISC_MISC_OBS 0x00000E00#define AR_MACMISC_MISC_OBS_S 9#define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12#define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15#define AR_MACMISC_MISC_OBS_BUS_1 1#define AR_INTCFG 0x005C#define AR_INTCFG_MSI_RXOK 0x00000000#define AR_INTCFG_MSI_RXINTM 0x00000004#define AR_INTCFG_MSI_RXMINTR 0x00000006#define AR_INTCFG_MSI_TXOK 0x00000000#define AR_INTCFG_MSI_TXINTM 0x00000010#define AR_INTCFG_MSI_TXMINTR 0x00000018#define AR_DATABUF_SIZE 0x0060#define AR_DATABUF_SIZE_MASK 0x00000FFF#define AR_GTXTO 0x0064#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000#define AR_GTXTO_TIMEOUT_LIMIT_S 16#define AR_GTTM 0x0068#define AR_GTTM_USEC 0x00000001#define AR_GTTM_IGNORE_IDLE 0x00000002#define AR_GTTM_RESET_IDLE 0x00000004#define AR_GTTM_CST_USEC 0x00000008#define AR_CST 0x006C#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000#define AR_CST_TIMEOUT_LIMIT_S 16#define AR_HP_RXDP 0x0074#define AR_LP_RXDP 0x0078#define AR_ISR 0x0080#define AR_ISR_RXOK 0x00000001#define AR_ISR_RXDESC 0x00000002#define AR_ISR_HP_RXOK 0x00000001#define AR_ISR_LP_RXOK 0x00000002#define AR_ISR_RXERR 0x00000004#define AR_ISR_RXNOPKT 0x00000008#define AR_ISR_RXEOL 0x00000010#define AR_ISR_RXORN 0x00000020#define AR_ISR_TXOK 0x00000040#define AR_ISR_TXDESC 0x00000080#define AR_ISR_TXERR 0x00000100#define AR_ISR_TXNOPKT 0x00000200#define AR_ISR_TXEOL 0x00000400#define AR_ISR_TXURN 0x00000800#define AR_ISR_MIB 0x00001000#define AR_ISR_SWI 0x00002000#define AR_ISR_RXPHY 0x00004000#define AR_ISR_RXKCM 0x00008000#define AR_ISR_SWBA 0x00010000#define AR_ISR_BRSSI 0x00020000#define AR_ISR_BMISS 0x00040000#define AR_ISR_BNR 0x00100000#define AR_ISR_RXCHIRP 0x00200000#define AR_ISR_BCNMISC 0x00800000#define AR_ISR_TIM 0x00800000#define AR_ISR_QCBROVF 0x02000000#define AR_ISR_QCBRURN 0x04000000#define AR_ISR_QTRIG 0x08000000#define AR_ISR_GENTMR 0x10000000#define AR_ISR_TXMINTR 0x00080000#define AR_ISR_RXMINTR 0x01000000#define AR_ISR_TXINTM 0x40000000#define AR_ISR_RXINTM 0x80000000#define AR_ISR_S0 0x0084#define AR_ISR_S0_QCU_TXOK 0x000003FF#define AR_ISR_S0_QCU_TXOK_S 0#define AR_ISR_S0_QCU_TXDESC 0x03FF0000#define AR_ISR_S0_QCU_TXDESC_S 16#define AR_ISR_S1 0x0088#define AR_ISR_S1_QCU_TXERR 0x000003FF#define AR_ISR_S1_QCU_TXERR_S 0#define AR_ISR_S1_QCU_TXEOL 0x03FF0000#define AR_ISR_S1_QCU_TXEOL_S 16#define AR_ISR_S2 0x008c#define AR_ISR_S2_QCU_TXURN 0x000003FF#define AR_ISR_S2_BB_WATCHDOG 0x00010000#define AR_ISR_S2_CST 0x00400000#define AR_ISR_S2_GTT 0x00800000#define AR_ISR_S2_TIM 0x01000000#define AR_ISR_S2_CABEND 0x02000000#define AR_ISR_S2_DTIMSYNC 0x04000000#define AR_ISR_S2_BCNTO 0x08000000#define AR_ISR_S2_CABTO 0x10000000#define AR_ISR_S2_DTIM 0x20000000#define AR_ISR_S2_TSFOOR 0x40000000#define AR_ISR_S2_TBTT_TIME 0x80000000#define AR_ISR_S3 0x0090#define AR_ISR_S3_QCU_QCBROVF 0x000003FF#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000#define AR_ISR_S4 0x0094#define AR_ISR_S4_QCU_QTRIG 0x000003FF#define AR_ISR_S4_RESV0 0xFFFFFC00#define AR_ISR_S5 0x0098#define AR_ISR_S5_TIMER_TRIG 0x000000FF#define AR_ISR_S5_TIMER_THRESH 0x0007FE00#define AR_ISR_S5_TIM_TIMER 0x00000010#define AR_ISR_S5_DTIM_TIMER 0x00000020#define AR_IMR_S5 0x00b8#define AR_IMR_S5_TIM_TIMER 0x00000010#define AR_IMR_S5_DTIM_TIMER 0x00000020#define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80#define AR_ISR_S5_GENTIMER_TRIG_S 0#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000#define AR_ISR_S5_GENTIMER_THRESH_S 16#define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80#define AR_IMR_S5_GENTIMER_TRIG_S 0#define AR_IMR_S5_GENTIMER_THRESH 0xFF800000#define AR_IMR_S5_GENTIMER_THRESH_S 16#define AR_IMR 0x00a0#define AR_IMR_RXOK 0x00000001#define AR_IMR_RXDESC 0x00000002#define AR_IMR_RXOK_HP 0x00000001#define AR_IMR_RXOK_LP 0x00000002#define AR_IMR_RXERR 0x00000004#define AR_IMR_RXNOPKT 0x00000008#define AR_IMR_RXEOL 0x00000010#define AR_IMR_RXORN 0x00000020#define AR_IMR_TXOK 0x00000040#define AR_IMR_TXDESC 0x00000080#define AR_IMR_TXERR 0x00000100#define AR_IMR_TXNOPKT 0x00000200#define AR_IMR_TXEOL 0x00000400#define AR_IMR_TXURN 0x00000800#define AR_IMR_MIB 0x00001000#define AR_IMR_SWI 0x00002000#define AR_IMR_RXPHY 0x00004000#define AR_IMR_RXKCM 0x00008000#define AR_IMR_SWBA 0x00010000#define AR_IMR_BRSSI 0x00020000#define AR_IMR_BMISS 0x00040000#define AR_IMR_BNR 0x00100000#define AR_IMR_RXCHIRP 0x00200000#define AR_IMR_BCNMISC 0x00800000#define AR_IMR_TIM 0x00800000#define AR_IMR_QCBROVF 0x02000000#define AR_IMR_QCBRURN 0x04000000#define AR_IMR_QTRIG 0x08000000#define AR_IMR_GENTMR 0x10000000#define AR_IMR_TXMINTR 0x00080000#define AR_IMR_RXMINTR 0x01000000#define AR_IMR_TXINTM 0x40000000#define AR_IMR_RXINTM 0x80000000#define AR_IMR_S0 0x00a4#define AR_IMR_S0_QCU_TXOK 0x000003FF#define AR_IMR_S0_QCU_TXOK_S 0#define AR_IMR_S0_QCU_TXDESC 0x03FF0000#define AR_IMR_S0_QCU_TXDESC_S 16#define AR_IMR_S1 0x00a8#define AR_IMR_S1_QCU_TXERR 0x000003FF#define AR_IMR_S1_QCU_TXERR_S 0#define AR_IMR_S1_QCU_TXEOL 0x03FF0000#define AR_IMR_S1_QCU_TXEOL_S 16#define AR_IMR_S2 0x00ac#define AR_IMR_S2_QCU_TXURN 0x000003FF#define AR_IMR_S2_QCU_TXURN_S 0#define AR_IMR_S2_BB_WATCHDOG 0x00010000#define AR_IMR_S2_CST 0x00400000#define AR_IMR_S2_GTT 0x00800000#define AR_IMR_S2_TIM 0x01000000#define AR_IMR_S2_CABEND 0x02000000#define AR_IMR_S2_DTIMSYNC 0x04000000#define AR_IMR_S2_BCNTO 0x08000000#define AR_IMR_S2_CABTO 0x10000000#define AR_IMR_S2_DTIM 0x20000000#define AR_IMR_S2_TSFOOR 0x40000000#define AR_IMR_S3 0x00b0#define AR_IMR_S3_QCU_QCBROVF 0x000003FF#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000#define AR_IMR_S3_QCU_QCBRURN_S 16#define AR_IMR_S4 0x00b4#define AR_IMR_S4_QCU_QTRIG 0x000003FF#define AR_IMR_S4_RESV0 0xFFFFFC00#define AR_IMR_S5 0x00b8#define AR_IMR_S5_TIMER_TRIG 0x000000FF#define AR_IMR_S5_TIMER_THRESH 0x0000FF00#define AR_ISR_RAC 0x00c0#define AR_ISR_S0_S 0x00c4#define AR_ISR_S0_QCU_TXOK 0x000003FF#define AR_ISR_S0_QCU_TXOK_S 0#define AR_ISR_S0_QCU_TXDESC 0x03FF0000#define AR_ISR_S0_QCU_TXDESC_S 16#define AR_ISR_S1_S 0x00c8#define AR_ISR_S1_QCU_TXERR 0x000003FF#define AR_ISR_S1_QCU_TXERR_S 0#define AR_ISR_S1_QCU_TXEOL 0x03FF0000#define AR_ISR_S1_QCU_TXEOL_S 16#define AR_ISR_S2_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00d0 : 0x00cc)#define AR_ISR_S3_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00d4 : 0x00d0)#define AR_ISR_S4_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00d8 : 0x00d4)#define AR_ISR_S5_S(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x00dc : 0x00d8)#define AR_DMADBG_0 0x00e0#define AR_DMADBG_1 0x00e4#define AR_DMADBG_2 0x00e8#define AR_DMADBG_3 0x00ec#define AR_DMADBG_4 0x00f0#define AR_DMADBG_5 0x00f4#define AR_DMADBG_6 0x00f8#define AR_DMADBG_7 0x00fc#define AR_NUM_QCU 10#define AR_QCU_0 0x0001#define AR_QCU_1 0x0002#define AR_QCU_2 0x0004#define AR_QCU_3 0x0008#define AR_QCU_4 0x0010#define AR_QCU_5 0x0020#define AR_QCU_6 0x0040#define AR_QCU_7 0x0080#define AR_QCU_8 0x0100#define AR_QCU_9 0x0200#define AR_Q0_TXDP 0x0800#define AR_Q1_TXDP 0x0804#define AR_Q2_TXDP 0x0808#define AR_Q3_TXDP 0x080c#define AR_Q4_TXDP 0x0810#define AR_Q5_TXDP 0x0814#define AR_Q6_TXDP 0x0818#define AR_Q7_TXDP 0x081c#define AR_Q8_TXDP 0x0820#define AR_Q9_TXDP 0x0824#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2))#define AR_Q_STATUS_RING_START 0x830#define AR_Q_STATUS_RING_END 0x834#define AR_Q_TXE 0x0840#define AR_Q_TXE_M 0x000003FF#define AR_Q_TXD 0x0880#define AR_Q_TXD_M 0x000003FF#define AR_Q0_CBRCFG 0x08c0#define AR_Q1_CBRCFG 0x08c4#define AR_Q2_CBRCFG 0x08c8#define AR_Q3_CBRCFG 0x08cc#define AR_Q4_CBRCFG 0x08d0#define AR_Q5_CBRCFG 0x08d4#define AR_Q6_CBRCFG 0x08d8#define AR_Q7_CBRCFG 0x08dc#define AR_Q8_CBRCFG 0x08e0#define AR_Q9_CBRCFG 0x08e4#define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2))#define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF#define AR_Q_CBRCFG_INTERVAL_S 0#define AR_Q_CBRCFG_OVF_THRESH 0xFF000000#define AR_Q_CBRCFG_OVF_THRESH_S 24#define AR_Q0_RDYTIMECFG 0x0900#define AR_Q1_RDYTIMECFG 0x0904#define AR_Q2_RDYTIMECFG 0x0908#define AR_Q3_RDYTIMECFG 0x090c#define AR_Q4_RDYTIMECFG 0x0910#define AR_Q5_RDYTIMECFG 0x0914#define AR_Q6_RDYTIMECFG 0x0918#define AR_Q7_RDYTIMECFG 0x091c#define AR_Q8_RDYTIMECFG 0x0920#define AR_Q9_RDYTIMECFG 0x0924#define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2))#define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF#define AR_Q_RDYTIMECFG_DURATION_S 0#define AR_Q_RDYTIMECFG_EN 0x01000000#define AR_Q_ONESHOTARM_SC 0x0940#define AR_Q_ONESHOTARM_SC_M 0x000003FF#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00#define AR_Q_ONESHOTARM_CC 0x0980#define AR_Q_ONESHOTARM_CC_M 0x000003FF#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00#define AR_Q0_MISC 0x09c0#define AR_Q1_MISC 0x09c4#define AR_Q2_MISC 0x09c8#define AR_Q3_MISC 0x09cc#define AR_Q4_MISC 0x09d0#define AR_Q5_MISC 0x09d4#define AR_Q6_MISC 0x09d8#define AR_Q7_MISC 0x09dc#define AR_Q8_MISC 0x09e0#define AR_Q9_MISC 0x09e4#define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2))#define AR_Q_MISC_FSP 0x0000000F#define AR_Q_MISC_FSP_ASAP 0#define AR_Q_MISC_FSP_CBR 1#define AR_Q_MISC_FSP_DBA_GATED 2#define AR_Q_MISC_FSP_TIM_GATED 3#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5#define AR_Q_MISC_ONE_SHOT_EN 0x00000010#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040#define AR_Q_MISC_BEACON_USE 0x00000080#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800#define AR_Q_MISC_RESV0 0xFFFFF000#define AR_Q0_STS 0x0a00#define AR_Q1_STS 0x0a04#define AR_Q2_STS 0x0a08#define AR_Q3_STS 0x0a0c#define AR_Q4_STS 0x0a10#define AR_Q5_STS 0x0a14#define AR_Q6_STS 0x0a18#define AR_Q7_STS 0x0a1c#define AR_Q8_STS 0x0a20#define AR_Q9_STS 0x0a24#define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2))#define AR_Q_STS_PEND_FR_CNT 0x00000003#define AR_Q_STS_RESV0 0x000000FC#define AR_Q_STS_CBR_EXP_CNT 0x0000FF00#define AR_Q_STS_RESV1 0xFFFF0000#define AR_Q_RDYTIMESHDN 0x0a40#define AR_Q_RDYTIMESHDN_M 0x000003FF/* MAC Descriptor CRC check */ #define AR_Q_DESC_CRCCHK 0xa44/* Enable CRC check on the descriptor fetched from host */ #define AR_Q_DESC_CRCCHK_EN 1#define AR_NUM_DCU 10#define AR_DCU_0 0x0001#define AR_DCU_1 0x0002#define AR_DCU_2 0x0004#define AR_DCU_3 0x0008#define AR_DCU_4 0x0010#define AR_DCU_5 0x0020#define AR_DCU_6 0x0040#define AR_DCU_7 0x0080#define AR_DCU_8 0x0100#define AR_DCU_9 0x0200#define AR_D0_QCUMASK 0x1000#define AR_D1_QCUMASK 0x1004#define AR_D2_QCUMASK 0x1008#define AR_D3_QCUMASK 0x100c#define AR_D4_QCUMASK 0x1010#define AR_D5_QCUMASK 0x1014#define AR_D6_QCUMASK 0x1018#define AR_D7_QCUMASK 0x101c#define AR_D8_QCUMASK 0x1020#define AR_D9_QCUMASK 0x1024#define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2))#define AR_D_QCUMASK 0x000003FF#define AR_D_QCUMASK_RESV0 0xFFFFFC00#define AR_D0_LCL_IFS 0x1040#define AR_D1_LCL_IFS 0x1044#define AR_D2_LCL_IFS 0x1048#define AR_D3_LCL_IFS 0x104c#define AR_D4_LCL_IFS 0x1050#define AR_D5_LCL_IFS 0x1054#define AR_D6_LCL_IFS 0x1058#define AR_D7_LCL_IFS 0x105c#define AR_D8_LCL_IFS 0x1060#define AR_D9_LCL_IFS 0x1064#define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2))#define AR_D_LCL_IFS_CWMIN 0x000003FF#define AR_D_LCL_IFS_CWMIN_S 0#define AR_D_LCL_IFS_CWMAX 0x000FFC00#define AR_D_LCL_IFS_CWMAX_S 10#define AR_D_LCL_IFS_AIFS 0x0FF00000#define AR_D_LCL_IFS_AIFS_S 20#define AR_D_LCL_IFS_RESV0 0xF0000000#define AR_D0_RETRY_LIMIT 0x1080#define AR_D1_RETRY_LIMIT 0x1084#define AR_D2_RETRY_LIMIT 0x1088#define AR_D3_RETRY_LIMIT 0x108c#define AR_D4_RETRY_LIMIT 0x1090#define AR_D5_RETRY_LIMIT 0x1094#define AR_D6_RETRY_LIMIT 0x1098#define AR_D7_RETRY_LIMIT 0x109c#define AR_D8_RETRY_LIMIT 0x10a0#define AR_D9_RETRY_LIMIT 0x10a4#define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2))#define AR_D_RETRY_LIMIT_FR_SH 0x0000000F#define AR_D_RETRY_LIMIT_FR_SH_S 0#define AR_D_RETRY_LIMIT_STA_SH 0x00003F00#define AR_D_RETRY_LIMIT_STA_SH_S 8#define AR_D_RETRY_LIMIT_STA_LG 0x000FC000#define AR_D_RETRY_LIMIT_STA_LG_S 14#define AR_D_RETRY_LIMIT_RESV0 0xFFF00000#define AR_D0_CHNTIME 0x10c0#define AR_D1_CHNTIME 0x10c4#define AR_D2_CHNTIME 0x10c8#define AR_D3_CHNTIME 0x10cc#define AR_D4_CHNTIME 0x10d0#define AR_D5_CHNTIME 0x10d4#define AR_D6_CHNTIME 0x10d8#define AR_D7_CHNTIME 0x10dc#define AR_D8_CHNTIME 0x10e0#define AR_D9_CHNTIME 0x10e4#define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2))#define AR_D_CHNTIME_DUR 0x000FFFFF#define AR_D_CHNTIME_DUR_S 0#define AR_D_CHNTIME_EN 0x00100000#define AR_D_CHNTIME_RESV0 0xFFE00000#define AR_D0_MISC 0x1100#define AR_D1_MISC 0x1104#define AR_D2_MISC 0x1108#define AR_D3_MISC 0x110c#define AR_D4_MISC 0x1110#define AR_D5_MISC 0x1114#define AR_D6_MISC 0x1118#define AR_D7_MISC 0x111c#define AR_D8_MISC 0x1120#define AR_D9_MISC 0x1124#define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2))#define AR_D_MISC_BKOFF_THRESH 0x0000003F#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040#define AR_D_MISC_CW_RESET_EN 0x00000080#define AR_D_MISC_FRAG_WAIT_EN 0x00000100#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200#define AR_D_MISC_CW_BKOFF_EN 0x00001000#define AR_D_MISC_VIR_COL_HANDLING 0x0000C000#define AR_D_MISC_VIR_COL_HANDLING_S 14#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1#define AR_D_MISC_BEACON_USE 0x00010000#define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000#define AR_D_MISC_RESV0 0xFF000000#define AR_D_SEQNUM 0x1140#define AR_D_GBL_IFS_SIFS 0x1030#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF#define AR_D_TXBLK_BASE 0x1038#define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF#define AR_D_TXBLK_WRITE_BITMASK_S 0#define AR_D_TXBLK_WRITE_SLICE 0x000F0000#define AR_D_TXBLK_WRITE_SLICE_S 16#define AR_D_TXBLK_WRITE_DCU 0x00F00000#define AR_D_TXBLK_WRITE_DCU_S 20#define AR_D_TXBLK_WRITE_COMMAND 0x0F000000#define AR_D_TXBLK_WRITE_COMMAND_S 24#define AR_D_GBL_IFS_SLOT 0x1070#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000#define AR_D_GBL_IFS_EIFS 0x10b0#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO 363#define AR_D_GBL_IFS_MISC 0x10f0#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000#define AR_D_FPCTL 0x1230#define AR_D_FPCTL_DCU 0x0000000F#define AR_D_FPCTL_DCU_S 0#define AR_D_FPCTL_PREFETCH_EN 0x00000010#define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0#define AR_D_FPCTL_BURST_PREFETCH_S 5#define AR_D_TXPSE 0x1270#define AR_D_TXPSE_CTRL 0x000003FF#define AR_D_TXPSE_RESV0 0x0000FC00#define AR_D_TXPSE_STATUS 0x00010000#define AR_D_TXPSE_RESV1 0xFFFE0000#define AR_D_TXSLOTMASK 0x12f0#define AR_D_TXSLOTMASK_NUM 0x0000000F#define AR_CFG_LED 0x1f04#define AR_CFG_SCLK_RATE_IND 0x00000003#define AR_CFG_SCLK_RATE_IND_S 0#define AR_CFG_SCLK_32MHZ 0x00000000#define AR_CFG_SCLK_4MHZ 0x00000001#define AR_CFG_SCLK_1MHZ 0x00000002#define AR_CFG_SCLK_32KHZ 0x00000003#define AR_CFG_LED_BLINK_SLOW 0x00000008#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070#define AR_CFG_LED_MODE_SEL 0x00000380#define AR_CFG_LED_MODE_SEL_S 7#define AR_CFG_LED_POWER 0x00000280#define AR_CFG_LED_POWER_S 7#define AR_CFG_LED_NETWORK 0x00000300#define AR_CFG_LED_NETWORK_S 7#define AR_CFG_LED_MODE_PROP 0x0#define AR_CFG_LED_MODE_RPROP 0x1#define AR_CFG_LED_MODE_SPLIT 0x2#define AR_CFG_LED_MODE_RAND 0x3#define AR_CFG_LED_MODE_POWER_OFF 0x4#define AR_CFG_LED_MODE_POWER_ON 0x5#define AR_CFG_LED_MODE_NETWORK_OFF 0x4#define AR_CFG_LED_MODE_NETWORK_ON 0x6#define AR_CFG_LED_ASSOC_CTL 0x00000c00#define AR_CFG_LED_ASSOC_CTL_S 10#define AR_CFG_LED_ASSOC_NONE 0x0#define AR_CFG_LED_ASSOC_ACTIVE 0x1#define AR_CFG_LED_ASSOC_PENDING 0x2#define AR_CFG_LED_BLINK_SLOW 0x00000008#define AR_CFG_LED_BLINK_SLOW_S 3#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070#define AR_CFG_LED_BLINK_THRESH_SEL_S 4#define AR_MAC_SLEEP 0x1f00#define AR_MAC_SLEEP_MAC_AWAKE 0x00000000#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001#define AR_RC 0x4000#define AR_RC_AHB 0x00000001#define AR_RC_APB 0x00000002#define AR_RC_HOSTIF 0x00000100#define AR_WA(_ah) (AR_SREV_9340(_ah) ? 0x40c4 : 0x4004)#define AR_WA_BIT6 (1 << 6)#define AR_WA_BIT7 (1 << 7)#define AR_WA_BIT23 (1 << 23)#define AR_WA_D3_L1_DISABLE (1 << 14)#define AR_WA_UNTIE_RESET_EN (1 << 15) /* Enable PCI Reset #define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16)#define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17)#define AR_WA_RESET_EN (1 << 18) /* Enable PCI-Reset to #define AR_WA_ANALOG_SHIFT (1 << 20)#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ #define AR_WA_BIT22 (1 << 22)#define AR9285_WA_DEFAULT 0x004a050b#define AR9280_WA_DEFAULT 0x0040073b#define AR_WA_DEFAULT 0x0000073f#define AR_PM_STATE 0x4008#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000#define AR_HOST_TIMEOUT(_ah) (AR_SREV_9340(_ah) ? 0x4008 : 0x4018)#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF#define AR_HOST_TIMEOUT_APB_CNTR_S 0#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000#define AR_HOST_TIMEOUT_LCL_CNTR_S 16#define AR_EEPROM 0x401c#define AR_EEPROM_ABSENT 0x00000100#define AR_EEPROM_CORRUPT 0x00000200#define AR_EEPROM_PROT_MASK 0x03FFFC00#define AR_EEPROM_PROT_MASK_S 10#define EEPROM_PROTECT_RP_0_31 0x0001#define EEPROM_PROTECT_WP_0_31 0x0002#define EEPROM_PROTECT_RP_32_63 0x0004#define EEPROM_PROTECT_WP_32_63 0x0008#define EEPROM_PROTECT_RP_64_127 0x0010#define EEPROM_PROTECT_WP_64_127 0x0020#define EEPROM_PROTECT_RP_128_191 0x0040#define EEPROM_PROTECT_WP_128_191 0x0080#define EEPROM_PROTECT_RP_192_255 0x0100#define EEPROM_PROTECT_WP_192_255 0x0200#define EEPROM_PROTECT_RP_256_511 0x0400#define EEPROM_PROTECT_WP_256_511 0x0800#define EEPROM_PROTECT_RP_512_1023 0x1000#define EEPROM_PROTECT_WP_512_1023 0x2000#define EEPROM_PROTECT_RP_1024_2047 0x4000#define EEPROM_PROTECT_WP_1024_2047 0x8000#define AR_SREV(_ah) \#define AR_SREV_ID(_ah) \#define AR_SREV_VERSION 0x000000F0#define AR_SREV_VERSION_S 4#define AR_SREV_REVISION 0x00000007#define AR_SREV_ID2 0xFFFFFFFF#define AR_SREV_VERSION2 0xFFFC0000#define AR_SREV_VERSION2_S 18#define AR_SREV_TYPE2 0x0003F000#define AR_SREV_TYPE2_S 12#define AR_SREV_TYPE2_CHAIN 0x00001000#define AR_SREV_TYPE2_HOST_MODE 0x00002000#define AR_SREV_REVISION2 0x00000F00#define AR_SREV_REVISION2_S 8#define AR_SREV_VERSION_5416_PCI 0xD#define AR_SREV_VERSION_5416_PCIE 0xC#define AR_SREV_REVISION_5416_10 0#define AR_SREV_REVISION_5416_20 1#define AR_SREV_REVISION_5416_22 2#define AR_SREV_VERSION_9100 0x14#define AR_SREV_VERSION_9160 0x40#define AR_SREV_REVISION_9160_10 0#define AR_SREV_REVISION_9160_11 1#define AR_SREV_VERSION_9280 0x80#define AR_SREV_REVISION_9280_10 0#define AR_SREV_REVISION_9280_20 1#define AR_SREV_REVISION_9280_21 2#define AR_SREV_VERSION_9285 0xC0#define AR_SREV_REVISION_9285_10 0#define AR_SREV_REVISION_9285_11 1#define AR_SREV_REVISION_9285_12 2#define AR_SREV_VERSION_9287 0x180#define AR_SREV_REVISION_9287_10 0#define AR_SREV_REVISION_9287_11 1#define AR_SREV_REVISION_9287_12 2#define AR_SREV_REVISION_9287_13 3#define AR_SREV_VERSION_9271 0x140#define AR_SREV_REVISION_9271_10 0#define AR_SREV_REVISION_9271_11 1#define AR_SREV_VERSION_9300 0x1c0#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */ #define AR_SREV_REVISION_9300_22 3#define AR_SREV_VERSION_9330 0x200#define AR_SREV_REVISION_9330_10 0#define AR_SREV_REVISION_9330_11 1#define AR_SREV_REVISION_9330_12 2#define AR_SREV_VERSION_9485 0x240#define AR_SREV_REVISION_9485_10 0#define AR_SREV_REVISION_9485_11 1#define AR_SREV_VERSION_9340 0x300#define AR_SREV_REVISION_9340_10 0#define AR_SREV_REVISION_9340_11 1#define AR_SREV_REVISION_9340_12 2#define AR_SREV_REVISION_9340_13 3#define AR_SREV_VERSION_9580 0x1C0#define AR_SREV_REVISION_9580_10 4 /* AR9580 1.0 */ #define AR_SREV_VERSION_9462 0x280#define AR_SREV_REVISION_9462_20 2#define AR_SREV_REVISION_9462_21 3#define AR_SREV_VERSION_9565 0x2C0#define AR_SREV_REVISION_9565_10 0#define AR_SREV_REVISION_9565_101 1#define AR_SREV_REVISION_9565_11 2#define AR_SREV_VERSION_9550 0x400#define AR_SREV_VERSION_9531 0x500#define AR_SREV_REVISION_9531_10 0#define AR_SREV_REVISION_9531_11 1#define AR_SREV_REVISION_9531_20 2#define AR_SREV_VERSION_9561 0x600#define AR_SREV_5416(_ah) \#define AR_SREV_5416_22_OR_LATER(_ah) \#define AR_SREV_9100(_ah) \#define AR_SREV_9100_OR_LATER(_ah) \#define AR_SREV_9160(_ah) \#define AR_SREV_9160_10_OR_LATER(_ah) \#define AR_SREV_9160_11(_ah) \#define AR_SREV_9280(_ah) \#define AR_SREV_9280_20_OR_LATER(_ah) \#define AR_SREV_9280_20(_ah) \#define AR_SREV_9285(_ah) \#define AR_SREV_9285_12_OR_LATER(_ah) \#define AR_SREV_9287(_ah) \#define AR_SREV_9287_11_OR_LATER(_ah) \#define AR_SREV_9287_11(_ah) \#define AR_SREV_9287_12(_ah) \#define AR_SREV_9287_12_OR_LATER(_ah) \#define AR_SREV_9287_13_OR_LATER(_ah) \#define AR_SREV_9271(_ah) \#define AR_SREV_9271_10(_ah) \#define AR_SREV_9271_11(_ah) \#define AR_SREV_9300(_ah) \#define AR_SREV_9300_20_OR_LATER(_ah) \#define AR_SREV_9300_22(_ah) \#define AR_SREV_9330(_ah) \#define AR_SREV_9330_11(_ah) \#define AR_SREV_9330_12(_ah) \#ifdef CONFIG_ATH9K_PCOEM#define AR_SREV_9462(_ah) \#define AR_SREV_9485(_ah) \#define AR_SREV_9565(_ah) \#define AR_SREV_9003_PCOEM(_ah) \#else #define AR_SREV_9462(_ah) 0#define AR_SREV_9485(_ah) 0#define AR_SREV_9565(_ah) 0#define AR_SREV_9003_PCOEM(_ah) 0#endif #define AR_SREV_9485_11_OR_LATER(_ah) \#define AR_SREV_9485_OR_LATER(_ah) \#define AR_SREV_9340(_ah) \#define AR_SREV_9340_13(_ah) \#define AR_SREV_9340_13_OR_LATER(_ah) \#define AR_SREV_9285E_20(_ah) \#define AR_SREV_9462_20(_ah) \#define AR_SREV_9462_21(_ah) \#define AR_SREV_9462_20_OR_LATER(_ah) \#define AR_SREV_9462_21_OR_LATER(_ah) \#define AR_SREV_9565_10(_ah) \#define AR_SREV_9565_101(_ah) \#define AR_SREV_9565_11(_ah) \#define AR_SREV_9565_11_OR_LATER(_ah) \#define AR_SREV_9550(_ah) \#define AR_SREV_9550_OR_LATER(_ah) \#define AR_SREV_9580(_ah) \#define AR_SREV_9580_10(_ah) \#define AR_SREV_9531(_ah) \#define AR_SREV_9531_10(_ah) \#define AR_SREV_9531_11(_ah) \#define AR_SREV_9531_20(_ah) \#define AR_SREV_9561(_ah) \#define AR_SREV_SOC(_ah) \/* NOTE: When adding chips newer than Peacock, add chip check here */ #define AR_SREV_9580_10_OR_LATER(_ah) \enum ath_usb_dev {/* AR7010 + AR9280, UB94 */ /* AR7010 + AR9287, UB95 */ #define AR_DEVID_7010(_ah) \#define AR_RADIO_SREV_MAJOR 0xf0#define AR_RAD5133_SREV_MAJOR 0xc0#define AR_RAD2133_SREV_MAJOR 0xd0#define AR_RAD5122_SREV_MAJOR 0xe0#define AR_RAD2122_SREV_MAJOR 0xf0#define AR_AHB_MODE 0x4024#define AR_AHB_EXACT_WR_EN 0x00000000#define AR_AHB_BUF_WR_EN 0x00000001#define AR_AHB_EXACT_RD_EN 0x00000000#define AR_AHB_CACHELINE_RD_EN 0x00000002#define AR_AHB_PREFETCH_RD_EN 0x00000004#define AR_AHB_PAGE_SIZE_1K 0x00000000#define AR_AHB_PAGE_SIZE_2K 0x00000008#define AR_AHB_PAGE_SIZE_4K 0x00000010#define AR_AHB_CUSTOM_BURST_EN 0x000000C0#define AR_AHB_CUSTOM_BURST_EN_S 6#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3#define AR_INTR_RTC_IRQ 0x00000001#define AR_INTR_MAC_IRQ 0x00000002#define AR_INTR_EEP_PROT_ACCESS 0x00000004#define AR_INTR_MAC_AWAKE 0x00020000#define AR_INTR_MAC_ASLEEP 0x00040000#define AR_INTR_SPURIOUS 0xFFFFFFFF#define AR_INTR_SYNC_CAUSE(_ah) (AR_SREV_9340(_ah) ? 0x4010 : 0x4028)#define AR_INTR_SYNC_CAUSE_CLR(_ah) (AR_SREV_9340(_ah) ? 0x4010 : 0x4028)#define AR_INTR_SYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4014 : 0x402c)#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000#define AR_INTR_SYNC_ENABLE_GPIO_S 18enum {#define AR_INTR_ASYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x4018 : 0x4030)#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000#define AR_INTR_ASYNC_MASK_GPIO_S 18#define AR_INTR_ASYNC_MASK_MCI 0x00000080#define AR_INTR_ASYNC_MASK_MCI_S 7#define AR_INTR_SYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x401c : 0x4034)#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000#define AR_INTR_SYNC_MASK_GPIO_S 18#define AR_INTR_ASYNC_CAUSE_CLR(_ah) (AR_SREV_9340(_ah) ? 0x4020 : 0x4038)#define AR_INTR_ASYNC_CAUSE(_ah) (AR_SREV_9340(_ah) ? 0x4020 : 0x4038)#define AR_INTR_ASYNC_CAUSE_MCI 0x00000080#define AR_INTR_ASYNC_USED (AR_INTR_MAC_IRQ | \/* Asynchronous Interrupt Enable Register */ #define AR_INTR_ASYNC_ENABLE_MCI 0x00000080#define AR_INTR_ASYNC_ENABLE_MCI_S 7#define AR_INTR_ASYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4024 : 0x403c)#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000#define AR_INTR_ASYNC_ENABLE_GPIO_S 18#define AR_PCIE_SERDES 0x4040#define AR_PCIE_SERDES2 0x4044#define AR_PCIE_PM_CTRL(_ah) (AR_SREV_9340(_ah) ? 0x4004 : 0x4014)#define AR_PCIE_PM_CTRL_ENA 0x00080000#define AR_PCIE_PHY_REG3 0x18c08/* Define correct GPIO numbers and MASK bits to indicate the WMAC * GPIO resource. * Allow SOC chips(AR9340, AR9531, AR9550, AR9561) to access all GPIOs * which rely on gpiolib framework. But restrict SOC AR9330 only to * access WMAC GPIO which has the same design with the old chips. #define AR_NUM_GPIO 14#define AR9280_NUM_GPIO 10#define AR9285_NUM_GPIO 12#define AR9287_NUM_GPIO 10#define AR9271_NUM_GPIO 16#define AR9300_NUM_GPIO 16#define AR9330_NUM_GPIO 16#define AR9340_NUM_GPIO 23#define AR9462_NUM_GPIO 14#define AR9485_NUM_GPIO 12#define AR9531_NUM_GPIO 18#define AR9550_NUM_GPIO 24#define AR9561_NUM_GPIO 23#define AR9565_NUM_GPIO 14#define AR9580_NUM_GPIO 16#define AR7010_NUM_GPIO 16#define AR_GPIO_MASK 0x00003FFF#define AR9271_GPIO_MASK 0x0000FFFF#define AR9280_GPIO_MASK 0x000003FF#define AR9285_GPIO_MASK 0x00000FFF#define AR9287_GPIO_MASK 0x000003FF#define AR9300_GPIO_MASK 0x0000F4FF#define AR9330_GPIO_MASK 0x0000F4FF#define AR9340_GPIO_MASK 0x0000000F#define AR9462_GPIO_MASK 0x00003FFF#define AR9485_GPIO_MASK 0x00000FFF#define AR9531_GPIO_MASK 0x0000000F#define AR9550_GPIO_MASK 0x0000000F#define AR9561_GPIO_MASK 0x0000000F#define AR9565_GPIO_MASK 0x00003FFF#define AR9580_GPIO_MASK 0x0000F4FF#define AR7010_GPIO_MASK 0x0000FFFF#define AR_GPIO_IN_OUT(_ah) (AR_SREV_9340(_ah) ? 0x4028 : 0x4048)#define AR_GPIO_IN_VAL 0x0FFFC000#define AR_GPIO_IN_VAL_S 14#define AR928X_GPIO_IN_VAL 0x000FFC00#define AR928X_GPIO_IN_VAL_S 10#define AR9285_GPIO_IN_VAL 0x00FFF000#define AR9285_GPIO_IN_VAL_S 12#define AR9287_GPIO_IN_VAL 0x003FF800#define AR9287_GPIO_IN_VAL_S 11#define AR9271_GPIO_IN_VAL 0xFFFF0000#define AR9271_GPIO_IN_VAL_S 16#define AR7010_GPIO_IN_VAL 0x0000FFFF#define AR7010_GPIO_IN_VAL_S 0#define AR_GPIO_IN(_ah) (AR_SREV_9340(_ah) ? 0x402c : 0x404c)#define AR9300_GPIO_IN_VAL 0x0001FFFF#define AR9300_GPIO_IN_VAL_S 0#define AR_GPIO_OE_OUT(_ah) (AR_SREV_9340(_ah) ? 0x4030 : \#define AR_GPIO_OE_OUT_DRV 0x3#define AR_GPIO_OE_OUT_DRV_NO 0x0#define AR_GPIO_OE_OUT_DRV_LOW 0x1#define AR_GPIO_OE_OUT_DRV_HI 0x2#define AR_GPIO_OE_OUT_DRV_ALL 0x3#define AR7010_GPIO_OE 0x52000#define AR7010_GPIO_OE_MASK 0x1#define AR7010_GPIO_OE_AS_OUTPUT 0x0#define AR7010_GPIO_OE_AS_INPUT 0x1#define AR7010_GPIO_IN 0x52004#define AR7010_GPIO_OUT 0x52008#define AR7010_GPIO_SET 0x5200C#define AR7010_GPIO_CLEAR 0x52010#define AR7010_GPIO_INT 0x52014#define AR7010_GPIO_INT_TYPE 0x52018#define AR7010_GPIO_INT_POLARITY 0x5201C#define AR7010_GPIO_PENDING 0x52020#define AR7010_GPIO_INT_MASK 0x52024#define AR7010_GPIO_FUNCTION 0x52028#define AR_GPIO_INTR_POL(_ah) (AR_SREV_9340(_ah) ? 0x4038 : \#define AR_GPIO_INTR_POL_VAL 0x0001FFFF#define AR_GPIO_INTR_POL_VAL_S 0#define AR_GPIO_INPUT_EN_VAL(_ah) (AR_SREV_9340(_ah) ? 0x403c : \#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000#define AR_GPIO_JTAG_DISABLE 0x00020000#define AR_GPIO_INPUT_MUX1(_ah) (AR_SREV_9340(_ah) ? 0x4040 : \#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8#define AR_GPIO_INPUT_MUX2(_ah) (AR_SREV_9340(_ah) ? 0x4044 : \#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f#define AR_GPIO_INPUT_MUX2_CLK25_S 0#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8#define AR_GPIO_OUTPUT_MUX1(_ah) (AR_SREV_9340(_ah) ? 0x4048 : \#define AR_GPIO_OUTPUT_MUX2(_ah) (AR_SREV_9340(_ah) ? 0x404c : \#define AR_GPIO_OUTPUT_MUX3(_ah) (AR_SREV_9340(_ah) ? 0x4050 : \#define AR_INPUT_STATE(_ah) (AR_SREV_9340(_ah) ? 0x4054 : \#define AR_EEPROM_STATUS_DATA(_ah) (AR_SREV_9340(_ah) ? 0x40c8 : \#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff#define AR_EEPROM_STATUS_DATA_VAL_S 0#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000#define AR_OBS(_ah) (AR_SREV_9340(_ah) ? 0x405c : \#define AR_GPIO_PDPU(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x4090 : 0x4088)#define AR_PCIE_MSI(_ah) (AR_SREV_9340(_ah) ? 0x40d8 : \#define AR_PCIE_MSI_ENABLE 0x00000001#define AR_PCIE_MSI_HW_DBI_WR_EN 0x02000000#define AR_PCIE_MSI_HW_INT_PENDING_ADDR 0xFFA0C1FF /* bits 8..11: value must be 0x5060 */ #define AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64 0xFFA0C9FF /* bits 8..11: value must be 0x5064 */ #define AR_INTR_PRIO_TX 0x00000001#define AR_INTR_PRIO_RXLP 0x00000002#define AR_INTR_PRIO_RXHP 0x00000004#define AR_INTR_PRIO_SYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4088 : 0x40c4)#define AR_INTR_PRIO_ASYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x408c : 0x40c8)#define AR_INTR_PRIO_SYNC_MASK(_ah) (AR_SREV_9340(_ah) ? 0x4090 : 0x40cc)#define AR_INTR_PRIO_ASYNC_ENABLE(_ah) (AR_SREV_9340(_ah) ? 0x4094 : 0x40d4)#define AR_ENT_OTP 0x40d8#define AR_ENT_OTP_CHAIN2_DISABLE 0x00020000#define AR_ENT_OTP_49GHZ_DISABLE 0x00100000#define AR_ENT_OTP_MIN_PKT_SIZE_DISABLE 0x00800000#define AR_CH0_BB_DPLL1 0x16180#define AR_CH0_BB_DPLL1_REFDIV 0xF8000000#define AR_CH0_BB_DPLL1_REFDIV_S 27#define AR_CH0_BB_DPLL1_NINI 0x07FC0000#define AR_CH0_BB_DPLL1_NINI_S 18#define AR_CH0_BB_DPLL1_NFRAC 0x0003FFFF#define AR_CH0_BB_DPLL1_NFRAC_S 0#define AR_CH0_BB_DPLL2 0x16184#define AR_CH0_BB_DPLL2_LOCAL_PLL 0x40000000#define AR_CH0_BB_DPLL2_LOCAL_PLL_S 30#define AR_CH0_DPLL2_KI 0x3C000000#define AR_CH0_DPLL2_KI_S 26#define AR_CH0_DPLL2_KD 0x03F80000#define AR_CH0_DPLL2_KD_S 19#define AR_CH0_BB_DPLL2_EN_NEGTRIG 0x00040000#define AR_CH0_BB_DPLL2_EN_NEGTRIG_S 18#define AR_CH0_BB_DPLL2_PLL_PWD 0x00010000#define AR_CH0_BB_DPLL2_PLL_PWD_S 16#define AR_CH0_BB_DPLL2_OUTDIV 0x0000E000#define AR_CH0_BB_DPLL2_OUTDIV_S 13#define AR_CH0_BB_DPLL3 0x16188#define AR_CH0_BB_DPLL3_PHASE_SHIFT 0x3F800000#define AR_CH0_BB_DPLL3_PHASE_SHIFT_S 23#define AR_CH0_DDR_DPLL2 0x16244#define AR_CH0_DDR_DPLL3 0x16248#define AR_CH0_DPLL3_PHASE_SHIFT 0x3F800000#define AR_CH0_DPLL3_PHASE_SHIFT_S 23#define AR_PHY_CCA_NOM_VAL_2GHZ -118#define AR_RTC_9300_SOC_PLL_DIV_INT 0x0000003f#define AR_RTC_9300_SOC_PLL_DIV_INT_S 0#define AR_RTC_9300_SOC_PLL_DIV_FRAC 0x000fffc0#define AR_RTC_9300_SOC_PLL_DIV_FRAC_S 6#define AR_RTC_9300_SOC_PLL_REFDIV 0x01f00000#define AR_RTC_9300_SOC_PLL_REFDIV_S 20#define AR_RTC_9300_SOC_PLL_CLKSEL 0x06000000#define AR_RTC_9300_SOC_PLL_CLKSEL_S 25#define AR_RTC_9300_SOC_PLL_BYPASS 0x08000000#define AR_RTC_9300_PLL_DIV 0x000003ff#define AR_RTC_9300_PLL_DIV_S 0#define AR_RTC_9300_PLL_REFDIV 0x00003C00#define AR_RTC_9300_PLL_REFDIV_S 10#define AR_RTC_9300_PLL_CLKSEL 0x0000C000#define AR_RTC_9300_PLL_CLKSEL_S 14#define AR_RTC_9300_PLL_BYPASS 0x00010000#define AR_RTC_9160_PLL_DIV 0x000003ff#define AR_RTC_9160_PLL_DIV_S 0#define AR_RTC_9160_PLL_REFDIV 0x00003C00#define AR_RTC_9160_PLL_REFDIV_S 10#define AR_RTC_9160_PLL_CLKSEL 0x0000C000#define AR_RTC_9160_PLL_CLKSEL_S 14#define AR_RTC_BASE 0x00020000#define AR_RTC_RC(_ah) \#define AR_RTC_RC_M 0x00000003#define AR_RTC_RC_MAC_WARM 0x00000001#define AR_RTC_RC_MAC_COLD 0x00000002#define AR_RTC_RC_COLD_RESET 0x00000004#define AR_RTC_RC_WARM_RESET 0x00000008/* Crystal Control */ #define AR_RTC_XTAL_CONTROL 0x7004/* Reg Control 0 */ #define AR_RTC_REG_CONTROL0 0x7008/* Reg Control 1 */ #define AR_RTC_REG_CONTROL1 0x700c#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001#define AR_RTC_PLL_CONTROL(_ah) \#define AR_RTC_PLL_CONTROL2 0x703c#define AR_RTC_PLL_DIV 0x0000001f#define AR_RTC_PLL_DIV_S 0#define AR_RTC_PLL_DIV2 0x00000020#define AR_RTC_PLL_REFDIV_5 0x000000c0#define AR_RTC_PLL_CLKSEL 0x00000300#define AR_RTC_PLL_CLKSEL_S 8#define AR_RTC_PLL_BYPASS 0x00010000#define AR_RTC_PLL_NOPWD 0x00040000#define AR_RTC_PLL_NOPWD_S 18#define PLL3 0x16188#define PLL3_DO_MEAS_MASK 0x40000000#define PLL4 0x1618c#define PLL4_MEAS_DONE 0x8#define SQSUM_DVC_MASK 0x007ffff8#define AR_RTC_RESET(_ah) \#define AR_RTC_RESET_EN (0x00000001)#define AR_RTC_STATUS(_ah) \#define AR_RTC_STATUS_M(_ah) \#define AR_RTC_PM_STATUS_M 0x0000000f#define AR_RTC_STATUS_SHUTDOWN 0x00000001#define AR_RTC_STATUS_ON 0x00000002#define AR_RTC_STATUS_SLEEP 0x00000004#define AR_RTC_STATUS_WAKEUP 0x00000008#define AR_RTC_SLEEP_CLK(_ah) \#define AR_RTC_FORCE_DERIVED_CLK 0x2#define AR_RTC_FORCE_SWREG_PRD 0x00000004#define AR_RTC_FORCE_WAKE(_ah) \#define AR_RTC_FORCE_WAKE_EN 0x00000001#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002#define AR_RTC_INTR_CAUSE(_ah) \#define AR_RTC_INTR_ENABLE(_ah) \#define AR_RTC_INTR_MASK(_ah) \#define AR_RTC_KEEP_AWAKE 0x7034/* RTC_DERIVED_* - only for AR9100 */ #define AR_RTC_DERIVED_CLK(_ah) \#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe#define AR_RTC_DERIVED_CLK_PERIOD_S 1#define AR_SEQ_MASK 0x8060#define AR_AN_RF2G1_CH0 0x7810#define AR_AN_RF2G1_CH0_OB 0x03800000#define AR_AN_RF2G1_CH0_OB_S 23#define AR_AN_RF2G1_CH0_DB 0x1C000000#define AR_AN_RF2G1_CH0_DB_S 26#define AR_AN_RF5G1_CH0 0x7818#define AR_AN_RF5G1_CH0_OB5 0x00070000#define AR_AN_RF5G1_CH0_OB5_S 16#define AR_AN_RF5G1_CH0_DB5 0x00380000#define AR_AN_RF5G1_CH0_DB5_S 19#define AR_AN_RF2G1_CH1 0x7834#define AR_AN_RF2G1_CH1_OB 0x03800000#define AR_AN_RF2G1_CH1_OB_S 23#define AR_AN_RF2G1_CH1_DB 0x1C000000#define AR_AN_RF2G1_CH1_DB_S 26#define AR_AN_RF5G1_CH1 0x783C#define AR_AN_RF5G1_CH1_OB5 0x00070000#define AR_AN_RF5G1_CH1_OB5_S 16#define AR_AN_RF5G1_CH1_DB5 0x00380000#define AR_AN_RF5G1_CH1_DB5_S 19#define AR_AN_TOP1 0x7890#define AR_AN_TOP1_DACIPMODE 0x00040000#define AR_AN_TOP1_DACIPMODE_S 18#define AR_AN_TOP2 0x7894#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000#define AR_AN_TOP2_XPABIAS_LVL_S 30#define AR_AN_TOP2_LOCALBIAS 0x00200000#define AR_AN_TOP2_LOCALBIAS_S 21#define AR_AN_TOP2_PWDCLKIND 0x00400000#define AR_AN_TOP2_PWDCLKIND_S 22#define AR_AN_SYNTH9 0x7868#define AR_AN_SYNTH9_REFDIVA 0xf8000000#define AR_AN_SYNTH9_REFDIVA_S 27#define AR9285_AN_RF2G1 0x7820#define AR9285_AN_RF2G1_ENPACAL 0x00000800#define AR9285_AN_RF2G1_ENPACAL_S 11#define AR9285_AN_RF2G1_PDPADRV1 0x02000000#define AR9285_AN_RF2G1_PDPADRV1_S 25#define AR9285_AN_RF2G1_PDPADRV2 0x01000000#define AR9285_AN_RF2G1_PDPADRV2_S 24#define AR9285_AN_RF2G1_PDPAOUT 0x00800000#define AR9285_AN_RF2G1_PDPAOUT_S 23#define AR9285_AN_RF2G2 0x7824#define AR9285_AN_RF2G2_OFFCAL 0x00001000#define AR9285_AN_RF2G2_OFFCAL_S 12#define AR9285_AN_RF2G3 0x7828#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000#define AR9285_AN_RF2G3_PDVCCOMP_S 25#define AR9285_AN_RF2G3_OB_0 0x00E00000#define AR9285_AN_RF2G3_OB_0_S 21#define AR9285_AN_RF2G3_OB_1 0x001C0000#define AR9285_AN_RF2G3_OB_1_S 18#define AR9285_AN_RF2G3_OB_2 0x00038000#define AR9285_AN_RF2G3_OB_2_S 15#define AR9285_AN_RF2G3_OB_3 0x00007000#define AR9285_AN_RF2G3_OB_3_S 12#define AR9285_AN_RF2G3_OB_4 0x00000E00#define AR9285_AN_RF2G3_OB_4_S 9#define AR9285_AN_RF2G3_DB1_0 0x000001C0#define AR9285_AN_RF2G3_DB1_0_S 6#define AR9285_AN_RF2G3_DB1_1 0x00000038#define AR9285_AN_RF2G3_DB1_1_S 3#define AR9285_AN_RF2G3_DB1_2 0x00000007#define AR9285_AN_RF2G3_DB1_2_S 0#define AR9285_AN_RF2G4 0x782C#define AR9285_AN_RF2G4_DB1_3 0xE0000000#define AR9285_AN_RF2G4_DB1_3_S 29#define AR9285_AN_RF2G4_DB1_4 0x1C000000#define AR9285_AN_RF2G4_DB1_4_S 26#define AR9285_AN_RF2G4_DB2_0 0x03800000#define AR9285_AN_RF2G4_DB2_0_S 23#define AR9285_AN_RF2G4_DB2_1 0x00700000#define AR9285_AN_RF2G4_DB2_1_S 20#define AR9285_AN_RF2G4_DB2_2 0x000E0000#define AR9285_AN_RF2G4_DB2_2_S 17#define AR9285_AN_RF2G4_DB2_3 0x0001C000#define AR9285_AN_RF2G4_DB2_3_S 14#define AR9285_AN_RF2G4_DB2_4 0x00003800#define AR9285_AN_RF2G4_DB2_4_S 11#define AR9285_RF2G5 0x7830#define AR9285_RF2G5_IC50TX 0xfffff8ff#define AR9285_RF2G5_IC50TX_SET 0x00000400#define AR9285_RF2G5_IC50TX_XE_SET 0x00000500#define AR9285_RF2G5_IC50TX_CLEAR 0x00000700#define AR9285_RF2G5_IC50TX_CLEAR_S 8/* AR9271 : 0x7828, 0x782c different setting from AR9285 */ #define AR9271_AN_RF2G3_OB_cck 0x001C0000#define AR9271_AN_RF2G3_OB_cck_S 18#define AR9271_AN_RF2G3_OB_psk 0x00038000#define AR9271_AN_RF2G3_OB_psk_S 15#define AR9271_AN_RF2G3_OB_qam 0x00007000#define AR9271_AN_RF2G3_OB_qam_S 12#define AR9271_AN_RF2G3_DB_1 0x00E00000#define AR9271_AN_RF2G3_DB_1_S 21#define AR9271_AN_RF2G3_CCOMP 0xFFF#define AR9271_AN_RF2G3_CCOMP_S 0#define AR9271_AN_RF2G4_DB_2 0xE0000000#define AR9271_AN_RF2G4_DB_2_S 29#define AR9285_AN_RF2G6 0x7834#define AR9285_AN_RF2G6_CCOMP 0x00007800#define AR9285_AN_RF2G6_CCOMP_S 11#define AR9285_AN_RF2G6_OFFS 0x03f00000#define AR9285_AN_RF2G6_OFFS_S 20#define AR9271_AN_RF2G6_OFFS 0x07f00000#define AR9271_AN_RF2G6_OFFS_S 20#define AR9285_AN_RF2G7 0x7838#define AR9285_AN_RF2G7_PWDDB 0x00000002#define AR9285_AN_RF2G7_PWDDB_S 1#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29#define AR9285_AN_RF2G8 0x783C#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14#define AR9285_AN_RF2G9 0x7840#define AR9285_AN_RXTXBB1 0x7854#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5#define AR9285_AN_RXTXBB1_PDV2I 0x00000080#define AR9285_AN_RXTXBB1_PDV2I_S 7#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100#define AR9285_AN_RXTXBB1_PDDACIF_S 8#define AR9285_AN_RXTXBB1_SPARE9 0x00000001#define AR9285_AN_RXTXBB1_SPARE9_S 0#define AR9285_AN_TOP2 0x7868#define AR9285_AN_TOP3 0x786c#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C#define AR9285_AN_TOP3_XPABIAS_LVL_S 2#define AR9285_AN_TOP3_PWDDAC 0x00800000#define AR9285_AN_TOP3_PWDDAC_S 23#define AR9285_AN_TOP4 0x7870#define AR9285_AN_TOP4_DEFAULT 0x10142c00#define AR9287_AN_RF2G3_CH0 0x7808#define AR9287_AN_RF2G3_CH1 0x785c#define AR9287_AN_RF2G3_DB1 0xE0000000#define AR9287_AN_RF2G3_DB1_S 29#define AR9287_AN_RF2G3_DB2 0x1C000000#define AR9287_AN_RF2G3_DB2_S 26#define AR9287_AN_RF2G3_OB_CCK 0x03800000#define AR9287_AN_RF2G3_OB_CCK_S 23#define AR9287_AN_RF2G3_OB_PSK 0x00700000#define AR9287_AN_RF2G3_OB_PSK_S 20#define AR9287_AN_RF2G3_OB_QAM 0x000E0000#define AR9287_AN_RF2G3_OB_QAM_S 17#define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000#define AR9287_AN_RF2G3_OB_PAL_OFF_S 14#define AR9287_AN_TXPC0 0x7898#define AR9287_AN_TXPC0_TXPCMODE 0x0000C000#define AR9287_AN_TXPC0_TXPCMODE_S 14#define AR9287_AN_TXPC0_TXPCMODE_NORMAL 0#define AR9287_AN_TXPC0_TXPCMODE_TEST 1#define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2#define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 3#define AR9287_AN_TOP2 0x78b4#define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000#define AR9287_AN_TOP2_XPABIAS_LVL_S 30/* AR9271 specific stuff */ #define AR9271_RESET_POWER_DOWN_CONTROL 0x50044#define AR9271_RADIO_RF_RST 0x20#define AR9271_GATE_MAC_CTL 0x4000#define AR_STA_ID1_STA_AP 0x00010000#define AR_STA_ID1_ADHOC 0x00020000#define AR_STA_ID1_PWR_SAV 0x00040000#define AR_STA_ID1_KSRCHDIS 0x00080000#define AR_STA_ID1_PCF 0x00100000#define AR_STA_ID1_USE_DEFANT 0x00200000#define AR_STA_ID1_DEFANT_UPDATE 0x00400000#define AR_STA_ID1_AR9100_BA_FIX 0x00400000#define AR_STA_ID1_RTS_USE_DEF 0x00800000#define AR_STA_ID1_ACKCTS_6MB 0x01000000#define AR_STA_ID1_BASE_RATE_11B 0x02000000#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000#define AR_STA_ID1_KSRCH_MODE 0x10000000#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000#define AR_STA_ID1_MCAST_KSRCH 0x80000000#define AR_BSS_ID0 0x8008#define AR_BSS_ID1 0x800C#define AR_BSS_ID1_U16 0x0000FFFF#define AR_BSS_ID1_AID 0x07FF0000#define AR_BSS_ID1_AID_S 16#define AR_BCN_RSSI_AVE 0x8010#define AR_BCN_RSSI_AVE_MASK 0x00000FFF#define AR_TIME_OUT 0x8014#define AR_TIME_OUT_ACK 0x00003FFF#define AR_TIME_OUT_ACK_S 0#define AR_TIME_OUT_CTS 0x3FFF0000#define AR_TIME_OUT_CTS_S 16#define AR_RSSI_THR 0x8018#define AR_RSSI_THR_MASK 0x000000FF#define AR_RSSI_THR_BM_THR 0x0000FF00#define AR_RSSI_THR_BM_THR_S 8#define AR_RSSI_BCN_WEIGHT 0x1F000000#define AR_RSSI_BCN_WEIGHT_S 24#define AR_RSSI_BCN_RSSI_RST 0x20000000#define AR_USEC 0x801c#define AR_USEC_USEC 0x0000007F#define AR_USEC_TX_LAT 0x007FC000#define AR_USEC_TX_LAT_S 14#define AR_USEC_RX_LAT 0x1F800000#define AR_USEC_RX_LAT_S 23#define AR_USEC_ASYNC_FIFO 0x12E00074#define AR_RESET_TSF 0x8020#define AR_RESET_TSF_ONCE 0x01000000#define AR_RESET_TSF2_ONCE 0x02000000#define AR_MAX_CFP_DUR 0x8038#define AR_CFP_VAL 0x0000FFFF#define AR_RX_FILTER 0x803C#define AR_MCAST_FIL0 0x8040#define AR_MCAST_FIL1 0x8044/* * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes. * * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down * receive. The force RX abort bit will kill any frame which is currently being * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS) * will prevent any new frames from getting started. #define AR_DIAG_SW 0x8048#define AR_DIAG_CACHE_ACK 0x00000001#define AR_DIAG_ACK_DIS 0x00000002#define AR_DIAG_CTS_DIS 0x00000004#define AR_DIAG_ENCRYPT_DIS 0x00000008#define AR_DIAG_DECRYPT_DIS 0x00000010#define AR_DIAG_RX_DIS 0x00000020 /* RX block */ #define AR_DIAG_LOOP_BACK 0x00000040#define AR_DIAG_CORR_FCS 0x00000080#define AR_DIAG_CHAN_INFO 0x00000100#define AR_DIAG_SCRAM_SEED 0x0001FE00#define AR_DIAG_SCRAM_SEED_S 8#define AR_DIAG_FRAME_NV0 0x00020000#define AR_DIAG_OBS_PT_SEL1 0x000C0000#define AR_DIAG_OBS_PT_SEL1_S 18#define AR_DIAG_OBS_PT_SEL2 0x08000000#define AR_DIAG_OBS_PT_SEL2_S 27#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */ #define AR_DIAG_IGNORE_VIRT_CS 0x00200000#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000#define AR_DIAG_EIFS_CTRL_ENA 0x00800000#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000#define AR_DIAG_RX_ABORT 0x02000000 /* Force RX abort */ #define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000#define AR_DIAG_OBS_PT_SEL2 0x08000000#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000#define AR_TSF_L32 0x804c#define AR_TSF_U32 0x8050#define AR_TST_ADDAC 0x8054#define AR_DEF_ANTENNA 0x8058#define AR_AES_MUTE_MASK0 0x805c#define AR_AES_MUTE_MASK0_FC 0x0000FFFF#define AR_AES_MUTE_MASK0_QOS 0xFFFF0000#define AR_AES_MUTE_MASK0_QOS_S 16#define AR_AES_MUTE_MASK1 0x8060#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000
Messung V0.5 C=97 H=93 G=94
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