/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* Copyright(c) 2019-2020 Realtek Corporation #ifndef __RTW89_FW_H__#define __RTW89_FW_H__#include "core.h" enum rtw89_fw_dl_status {struct rtw89_c2hreg_hdr {#define RTW89_C2HREG_HDR_FUNC_MASK GENMASK(6, 0)#define RTW89_C2HREG_HDR_ACK BIT(7)#define RTW89_C2HREG_HDR_LEN_MASK GENMASK(11, 8)#define RTW89_C2HREG_HDR_SEQ_MASK GENMASK(15, 12)struct rtw89_c2hreg_phycap {#define RTW89_C2HREG_PHYCAP_W0_FUNC GENMASK(6, 0)#define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)#define RTW89_C2HREG_PHYCAP_W0_LEN GENMASK(11, 8)#define RTW89_C2HREG_PHYCAP_W0_SEQ GENMASK(15, 12)#define RTW89_C2HREG_PHYCAP_W0_RX_NSS GENMASK(23, 16)#define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)#define RTW89_C2HREG_PHYCAP_W1_TX_NSS GENMASK(7, 0)#define RTW89_C2HREG_PHYCAP_W1_PROT GENMASK(15, 8)#define RTW89_C2HREG_PHYCAP_W1_NIC GENMASK(23, 16)#define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)#define RTW89_C2HREG_PHYCAP_W2_HW_TYPE GENMASK(7, 0)#define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM GENMASK(15, 8)#define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM GENMASK(23, 16)#define RTW89_C2HREG_PHYCAP_W3_BAND_SEL GENMASK(31, 24)#define RTW89_C2HREG_PHYCAP_P1_W0_B1_RX_NSS GENMASK(23, 16)#define RTW89_C2HREG_PHYCAP_P1_W0_B1_BW GENMASK(31, 24)#define RTW89_C2HREG_PHYCAP_P1_W1_B1_TX_NSS GENMASK(7, 0)#define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_TX_NUM GENMASK(15, 8)#define RTW89_C2HREG_PHYCAP_P1_W1_B1_ANT_RX_NUM GENMASK(23, 16)#define RTW89_C2HREG_PHYCAP_P1_W1_B1_BAND_SEL GENMASK(31, 24)#define RTW89_C2HREG_PHYCAP_P1_W2_QAM GENMASK(7, 0)#define RTW89_C2HREG_PHYCAP_P1_W2_QAM_256 0x1#define RTW89_C2HREG_PHYCAP_P1_W2_QAM_1024 0x2#define RTW89_C2HREG_PHYCAP_P1_W2_QAM_4096 0x3#define RTW89_C2HREG_PHYCAP_P1_W2_B1_QAM GENMASK(15, 8)#define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX GENMASK(23, 16)#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 GENMASK(7, 0)#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 GENMASK(15, 8)#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 GENMASK(23, 16)#define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 GENMASK(31, 24)#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 GENMASK(7, 0)#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 GENMASK(15, 8)#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 GENMASK(23, 16)#define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 GENMASK(31, 24)#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 GENMASK(7, 0)#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 GENMASK(15, 8)#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 GENMASK(23, 16)#define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 GENMASK(31, 24)#define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 GENMASK(23, 16)#define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 GENMASK(31, 24)#define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 GENMASK(7, 0)#define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 GENMASK(15, 8)#define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 GENMASK(23, 16)#define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 GENMASK(31, 24)#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 GENMASK(7, 0)#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 GENMASK(15, 8)#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 GENMASK(23, 16)#define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 GENMASK(31, 24)#define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 GENMASK(7, 0)#define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 GENMASK(15, 8)#define RTW89_C2HREG_PS_LEAVE_ACK_RET GENMASK(7, 0)#define RTW89_C2HREG_PS_LEAVE_ACK_MACID GENMASK(31, 16)struct rtw89_h2creg_hdr {#define RTW89_H2CREG_HDR_FUNC_MASK GENMASK(6, 0)#define RTW89_H2CREG_HDR_LEN_MASK GENMASK(11, 8)struct rtw89_h2creg_sch_tx_en {#define RTW89_H2CREG_SCH_TX_EN_W0_EN GENMASK(31, 16)#define RTW89_H2CREG_SCH_TX_EN_W1_MASK GENMASK(15, 0)#define RTW89_H2CREG_SCH_TX_EN_W1_BAND BIT(16)#define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN GENMASK(23, 16)#define RTW89_H2CREG_GET_FEATURE_PART_NUM GENMASK(23, 16)#define RTW89_H2CREG_MAX 4#define RTW89_C2HREG_MAX 4#define RTW89_C2HREG_HDR_LEN 2#define RTW89_H2CREG_HDR_LEN 2#define RTW89_C2H_TIMEOUT 1000000#define RTW89_C2H_TIMEOUT_USB 4000struct rtw89_mac_c2h_info {union {struct rtw89_c2hreg_hdr hdr;struct rtw89_c2hreg_phycap phycap;struct rtw89_mac_h2c_info {union {struct rtw89_h2creg_hdr hdr;struct rtw89_h2creg_sch_tx_en sch_tx_en;enum rtw89_mac_h2c_type {enum rtw89_mac_c2h_type {enum rtw89_fw_c2h_category {enum rtw89_fw_log_level {enum rtw89_fw_log_path {enum rtw89_fw_log_comp {enum rtw89_pkt_offload_op {#define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) \enum rtw89_scanofld_notify_reason {enum rtw89_scanofld_status {enum rtw89_chan_type {enum rtw89_p2pps_action {#define RTW89_DEFAULT_CQM_HYST 4#define RTW89_DEFAULT_CQM_THOLD -70enum rtw89_bcn_fltr_offload_mode {enum rtw89_bcn_fltr_type {enum rtw89_bcn_fltr_rssi_event {#define FWDL_SECTION_MAX_NUM 10#define FWDL_SECTION_CHKSUM_LEN 8#define FWDL_SECTION_PER_PKT_LEN 2020struct rtw89_fw_hdr_section_info {const u8 *addr;bool ignore;const u8 *key_addr;struct rtw89_fw_bin_info {bool dynamic_hdr_en;bool dsp_checksum;bool secure_section_exist;struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM];struct rtw89_fw_macid_pause_grp {struct rtw89_fw_macid_pause_sleep_grp {struct {#define RTW89_H2C_MAX_SIZE 2048#define RTW89_CHANNEL_TIME 45#define RTW89_CHANNEL_TIME_6G 20#define RTW89_CHANNEL_TIME_EXTRA_OP 30#define RTW89_DFS_CHAN_TIME 105#define RTW89_OFF_CHAN_TIME 100#define RTW89_P2P_CHAN_TIME 105#define RTW89_DWELL_TIME 20#define RTW89_DWELL_TIME_6G 10#define RTW89_SCAN_WIDTH 0#define RTW89_SCANOFLD_MAX_SSID 8#define RTW89_SCANOFLD_MAX_IE_LEN 512#define RTW89_SCANOFLD_PKT_NONE 0xFF#define RTW89_SCANOFLD_DEBUG_MASK 0x1F#define RTW89_CHAN_INVALID 0xFF#define RTW89_MAC_CHINFO_SIZE 28#define RTW89_MAC_CHINFO_SIZE_BE 32#define RTW89_SCAN_LIST_GUARD 4#define RTW89_SCAN_LIST_LIMIT(size) \#define RTW89_SCAN_LIST_LIMIT_AX RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE)#define RTW89_SCAN_LIST_LIMIT_BE RTW89_SCAN_LIST_LIMIT(RTW89_MAC_CHINFO_SIZE_BE)#define RTW89_BCN_LOSS_CNT 60struct rtw89_mac_chinfo_ax {struct list_head list;bool is_psc;struct rtw89_mac_chinfo_be {struct list_head list;bool is_psc;struct rtw89_pktofld_info {struct list_head list;bool wildcard_6ghz;/* Below fields are for WiFi 6 chips 6 GHz RNR use only */ bool cancel;struct rtw89_h2c_ra {#define RTW89_H2C_RA_W0_IS_DIS BIT(0)#define RTW89_H2C_RA_W0_MODE GENMASK(5, 1)#define RTW89_H2C_RA_W0_BW_CAP GENMASK(7, 6)#define RTW89_H2C_RA_W0_MACID GENMASK(15, 8)#define RTW89_H2C_RA_W0_DCM BIT(16)#define RTW89_H2C_RA_W0_ER BIT(17)#define RTW89_H2C_RA_W0_INIT_RATE_LV GENMASK(19, 18)#define RTW89_H2C_RA_W0_UPD_ALL BIT(20)#define RTW89_H2C_RA_W0_SGI BIT(21)#define RTW89_H2C_RA_W0_LDPC BIT(22)#define RTW89_H2C_RA_W0_STBC BIT(23)#define RTW89_H2C_RA_W0_SS_NUM GENMASK(26, 24)#define RTW89_H2C_RA_W0_GILTF GENMASK(29, 27)#define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK BIT(30)#define RTW89_H2C_RA_W0_UPD_MASK BIT(31)#define RTW89_H2C_RA_W1_RAMASK_LO32 GENMASK(31, 0)#define RTW89_H2C_RA_W2_RAMASK_HI32 GENMASK(30, 0)#define RTW89_H2C_RA_W2_BFEE_CSI_CTL BIT(31)#define RTW89_H2C_RA_W3_BAND_NUM GENMASK(7, 0)#define RTW89_H2C_RA_W3_RA_CSI_RATE_EN BIT(8)#define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN BIT(9)#define RTW89_H2C_RA_W3_CR_TBL_SEL BIT(10)#define RTW89_H2C_RA_W3_FIX_GILTF_EN BIT(11)#define RTW89_H2C_RA_W3_FIX_GILTF GENMASK(14, 12)#define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX GENMASK(23, 16)#define RTW89_H2C_RA_W3_FIXED_CSI_MODE GENMASK(25, 24)#define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF GENMASK(28, 26)#define RTW89_H2C_RA_W3_FIXED_CSI_BW GENMASK(31, 29)struct rtw89_h2c_ra_v1 {struct rtw89_h2c_ra v0;#define RTW89_H2C_RA_V1_W4_MODE_EHT GENMASK(6, 0)#define RTW89_H2C_RA_V1_W4_BW_EHT GENMASK(10, 8)#define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 GENMASK(31, 16)#define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 GENMASK(15, 0)static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val)static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val)static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val)static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val)static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val)static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val)#define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16)#define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12)#define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8)#define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0)#define FWDL_SECURITY_SECTION_TYPE 9#define FWDL_SECURITY_SIGLEN 512#define FWDL_SECURITY_CHKSUM_LEN 8struct rtw89_fw_dynhdr_sec {struct rtw89_fw_dynhdr_hdr {/* struct rtw89_fw_dynhdr_sec (nested flexible structures) */ struct rtw89_fw_hdr_section {#define FWSECTION_HDR_W0_DL_ADDR GENMASK(31, 0)#define FWSECTION_HDR_W1_METADATA GENMASK(31, 24)#define FWSECTION_HDR_W1_SECTIONTYPE GENMASK(27, 24)#define FWSECTION_HDR_W1_SEC_SIZE GENMASK(23, 0)#define FWSECTION_HDR_W1_CHECKSUM BIT(28)#define FWSECTION_HDR_W1_REDL BIT(29)#define FWSECTION_HDR_W2_MSSC GENMASK(31, 0)struct rtw89_fw_hdr {struct rtw89_fw_hdr_section sections[];/* struct rtw89_fw_dynhdr_hdr (optional) */ #define FW_HDR_W1_MAJOR_VERSION GENMASK(7, 0)#define FW_HDR_W1_MINOR_VERSION GENMASK(15, 8)#define FW_HDR_W1_SUBVERSION GENMASK(23, 16)#define FW_HDR_W1_SUBINDEX GENMASK(31, 24)#define FW_HDR_W2_COMMITID GENMASK(31, 0)#define FW_HDR_W3_LEN GENMASK(23, 16)#define FW_HDR_W3_HDR_VER GENMASK(31, 24)#define FW_HDR_W4_MONTH GENMASK(7, 0)#define FW_HDR_W4_DATE GENMASK(15, 8)#define FW_HDR_W4_HOUR GENMASK(23, 16)#define FW_HDR_W4_MIN GENMASK(31, 24)#define FW_HDR_W5_YEAR GENMASK(31, 0)#define FW_HDR_W6_SEC_NUM GENMASK(15, 8)#define FW_HDR_W7_PART_SIZE GENMASK(15, 0)#define FW_HDR_W7_DYN_HDR BIT(16)#define FW_HDR_W7_IDMEM_SHARE_MODE GENMASK(21, 18)#define FW_HDR_W7_CMD_VERSERION GENMASK(31, 24)struct rtw89_fw_hdr_section_v1 {#define FWSECTION_HDR_V1_W0_DL_ADDR GENMASK(31, 0)#define FWSECTION_HDR_V1_W1_METADATA GENMASK(31, 24)#define FWSECTION_HDR_V1_W1_SECTIONTYPE GENMASK(27, 24)#define FWSECTION_HDR_V1_W1_SEC_SIZE GENMASK(23, 0)#define FWSECTION_HDR_V1_W1_CHECKSUM BIT(28)#define FWSECTION_HDR_V1_W1_REDL BIT(29)#define FWSECTION_HDR_V1_W2_MSSC GENMASK(7, 0)#define FORMATTED_MSSC 0xFF#define FORMATTED_MSSC_MASK GENMASK(7, 0)#define FWSECTION_HDR_V1_W2_BBMCU_IDX GENMASK(27, 24)struct rtw89_fw_hdr_v1 {struct rtw89_fw_hdr_section_v1 sections[];#define FW_HDR_V1_W1_MAJOR_VERSION GENMASK(7, 0)#define FW_HDR_V1_W1_MINOR_VERSION GENMASK(15, 8)#define FW_HDR_V1_W1_SUBVERSION GENMASK(23, 16)#define FW_HDR_V1_W1_SUBINDEX GENMASK(31, 24)#define FW_HDR_V1_W2_COMMITID GENMASK(31, 0)#define FW_HDR_V1_W3_CMD_VERSERION GENMASK(23, 16)#define FW_HDR_V1_W3_HDR_VER GENMASK(31, 24)#define FW_HDR_V1_W4_MONTH GENMASK(7, 0)#define FW_HDR_V1_W4_DATE GENMASK(15, 8)#define FW_HDR_V1_W4_HOUR GENMASK(23, 16)#define FW_HDR_V1_W4_MIN GENMASK(31, 24)#define FW_HDR_V1_W5_YEAR GENMASK(15, 0)#define FW_HDR_V1_W5_HDR_SIZE GENMASK(31, 16)#define FW_HDR_V1_W6_SEC_NUM GENMASK(15, 8)#define FW_HDR_V1_W6_DSP_CHKSUM BIT(24)#define FW_HDR_V1_W7_PART_SIZE GENMASK(15, 0)#define FW_HDR_V1_W7_DYN_HDR BIT(16)#define FW_HDR_V1_W7_IDMEM_SHARE_MODE GENMASK(21, 18)enum rtw89_fw_mss_pool_rmp_tbl_type {#define FWDL_MSS_POOL_DEFKEYSETS_SIZE 8struct rtw89_fw_mss_pool_hdr {/* equal to mss_signature[] */ /* enum rtw89_fw_mss_pool_rmp_tbl_type */ union rtw89_fw_section_mssc_content {struct {struct {struct {struct rtw89_fw_blacklist {extern const struct rtw89_fw_blacklist rtw89_fw_blacklist_default;static inline void SET_CTRL_INFO_MACID(void *table, u32 val)static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val)#define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0)static inline void SET_CMC_TBL_DATARATE(void *table, u32 val)#define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0)static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0)static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0)static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val)#define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0)static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val)#define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0)static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val)#define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0)static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0)static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0)static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0)static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_DISRTSFB BIT(0)static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val)#define SET_CMC_TBL_MASK_DISDATAFB BIT(0)static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val)#define SET_CMC_TBL_MASK_TRYRATE BIT(0)static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val)#define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0)static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0)static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val)#define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0)static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val)#define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0)static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val)#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0)static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val)#define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0)static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val)#define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0)static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val)#define SET_CMC_TBL_MASK_VCS_STBC BIT(0)static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val)#define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0)static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0)static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0)static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val)#define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0)static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val)#define SET_CMC_TBL_MASK_RTS_EN BIT(0)static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0)static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0)static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val)#define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0)static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0)static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val)#define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0)static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val)#define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0)static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val)#define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0)static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val)#define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0)static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val)#define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0)static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val)#define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0)static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val)#define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0)static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val)#define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0)static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val)#define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0)static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val)#define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0)static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val)#define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0)static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val)#define SET_CMC_TBL_MASK_BMC BIT(0)static inline void SET_CMC_TBL_BMC(void *table, u32 val)#define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0)static inline void SET_CMC_TBL_MBSSID(void *table, u32 val)#define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0)static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val)#define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0)static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_DCM BIT(0)static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_ER BIT(0)static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_LDPC BIT(0)static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_STBC BIT(0)static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val)#define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0)static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val)#define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0)static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val)#define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0)static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val)#define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0)static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val)#define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0)static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val)#define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0)static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0)static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val)#define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0)static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val)#define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0)static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val)#define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0)static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val)#define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0)static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val)#define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0)static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0)static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val)#define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0)static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val)#define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0)static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val)#define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0)static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val)#define SET_CMC_TBL_MASK_ANTSEL_A BIT(0)static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val)#define SET_CMC_TBL_MASK_ANTSEL_B BIT(0)static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val)#define SET_CMC_TBL_MASK_ANTSEL_C BIT(0)static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val)#define SET_CMC_TBL_MASK_ANTSEL_D BIT(0)static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val)#define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0)static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val)static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val)static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val)static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val)#define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0)static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val)#define SET_CMC_TBL_MASK_PAID GENMASK(8, 0)static inline void SET_CMC_TBL_PAID(void *table, u32 val)#define SET_CMC_TBL_MASK_ULDL BIT(0)static inline void SET_CMC_TBL_ULDL(void *table, u32 val)#define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0)static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val)static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val)static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val)#define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0)static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val)static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val)#define SET_CMC_TBL_MASK_NC GENMASK(2, 0)static inline void SET_CMC_TBL_NC(void *table, u32 val)#define SET_CMC_TBL_MASK_NR GENMASK(2, 0)static inline void SET_CMC_TBL_NR(void *table, u32 val)#define SET_CMC_TBL_MASK_NG GENMASK(1, 0)static inline void SET_CMC_TBL_NG(void *table, u32 val)#define SET_CMC_TBL_MASK_CB GENMASK(1, 0)static inline void SET_CMC_TBL_CB(void *table, u32 val)#define SET_CMC_TBL_MASK_CS GENMASK(1, 0)static inline void SET_CMC_TBL_CS(void *table, u32 val)#define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0)static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0)static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0)static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0)static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val)#define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0)static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val)#define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0)static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val)static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val)#define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0)static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val)struct rtw89_h2c_cctlinfo_ud_g7 {#define CCTLINFO_G7_C0_MACID GENMASK(6, 0)#define CCTLINFO_G7_C0_OP BIT(7)#define CCTLINFO_G7_W0_DATARATE GENMASK(11, 0)#define CCTLINFO_G7_W0_DATA_GI_LTF GENMASK(14, 12)#define CCTLINFO_G7_W0_TRYRATE BIT(15)#define CCTLINFO_G7_W0_ARFR_CTRL GENMASK(17, 16)#define CCTLINFO_G7_W0_DIS_HE1SS_STBC BIT(18)#define CCTLINFO_G7_W0_ACQ_RPT_EN BIT(20)#define CCTLINFO_G7_W0_MGQ_RPT_EN BIT(21)#define CCTLINFO_G7_W0_ULQ_RPT_EN BIT(22)#define CCTLINFO_G7_W0_TWTQ_RPT_EN BIT(23)#define CCTLINFO_G7_W0_FORCE_TXOP BIT(24)#define CCTLINFO_G7_W0_DISRTSFB BIT(25)#define CCTLINFO_G7_W0_DISDATAFB BIT(26)#define CCTLINFO_G7_W0_NSTR_EN BIT(27)#define CCTLINFO_G7_W0_AMPDU_DENSITY GENMASK(31, 28)#define CCTLINFO_G7_W0_ALL (GENMASK(31, 20) | GENMASK(18, 0))#define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE GENMASK(11, 0)#define CCTLINFO_G7_W1_RTS_TXCNT_LMT GENMASK(15, 12)#define CCTLINFO_G7_W1_RTSRATE GENMASK(27, 16)#define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE GENMASK(31, 28)#define CCTLINFO_G7_W1_ALL GENMASK(31, 0)#define CCTLINFO_G7_W2_DATA_TX_CNT_LMT GENMASK(5, 0)#define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL BIT(6)#define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL BIT(7)#define CCTLINFO_G7_W2_RTS_EN BIT(8)#define CCTLINFO_G7_W2_CTS2SELF_EN BIT(9)#define CCTLINFO_G7_W2_CCA_RTS GENMASK(11, 10)#define CCTLINFO_G7_W2_HW_RTS_EN BIT(12)#define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE GENMASK(14, 13)#define CCTLINFO_G7_W2_PRELD_EN BIT(15)#define CCTLINFO_G7_W2_AMPDU_MAX_LEN GENMASK(26, 16)#define CCTLINFO_G7_W2_UL_MU_DIS BIT(27)#define CCTLINFO_G7_W2_AMPDU_MAX_TIME GENMASK(31, 28)#define CCTLINFO_G7_W2_ALL GENMASK(31, 0)#define CCTLINFO_G7_W3_MAX_AGG_NUM GENMASK(7, 0)#define CCTLINFO_G7_W3_DATA_BW GENMASK(10, 8)#define CCTLINFO_G7_W3_DATA_BW_ER BIT(11)#define CCTLINFO_G7_W3_BA_BMAP GENMASK(14, 12)#define CCTLINFO_G7_W3_VCS_STBC BIT(15)#define CCTLINFO_G7_W3_VO_LFTIME_SEL GENMASK(18, 16)#define CCTLINFO_G7_W3_VI_LFTIME_SEL GENMASK(21, 19)#define CCTLINFO_G7_W3_BE_LFTIME_SEL GENMASK(24, 22)#define CCTLINFO_G7_W3_BK_LFTIME_SEL GENMASK(27, 25)#define CCTLINFO_G7_W3_AMPDU_TIME_SEL BIT(28)#define CCTLINFO_G7_W3_AMPDU_LEN_SEL BIT(29)#define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL BIT(30)#define CCTLINFO_G7_W3_LSIG_TXOP_EN BIT(31)#define CCTLINFO_G7_W3_ALL GENMASK(31, 0)#define CCTLINFO_G7_W4_MULTI_PORT_ID GENMASK(2, 0)#define CCTLINFO_G7_W4_BYPASS_PUNC BIT(3)#define CCTLINFO_G7_W4_MBSSID GENMASK(7, 4)#define CCTLINFO_G7_W4_DATA_DCM BIT(8)#define CCTLINFO_G7_W4_DATA_ER BIT(9)#define CCTLINFO_G7_W4_DATA_LDPC BIT(10)#define CCTLINFO_G7_W4_DATA_STBC BIT(11)#define CCTLINFO_G7_W4_A_CTRL_BQR BIT(12)#define CCTLINFO_G7_W4_A_CTRL_BSR BIT(14)#define CCTLINFO_G7_W4_A_CTRL_CAS BIT(15)#define CCTLINFO_G7_W4_ACT_SUBCH_CBW GENMASK(31, 16)#define CCTLINFO_G7_W4_ALL (GENMASK(31, 14) | GENMASK(12, 0))#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 GENMASK(1, 0)#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 GENMASK(3, 2)#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 GENMASK(5, 4)#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 GENMASK(7, 6)#define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 GENMASK(9, 8)#define CCTLINFO_G7_W5_SR_RATE GENMASK(14, 10)#define CCTLINFO_G7_W5_TID_DISABLE GENMASK(23, 16)#define CCTLINFO_G7_W5_ADDR_CAM_INDEX GENMASK(31, 24)#define CCTLINFO_G7_W5_ALL (GENMASK(31, 16) | GENMASK(14, 0))#define CCTLINFO_G7_W6_AID12_PAID GENMASK(11, 0)#define CCTLINFO_G7_W6_RESP_REF_RATE GENMASK(23, 12)#define CCTLINFO_G7_W6_ULDL BIT(31)#define CCTLINFO_G7_W6_ALL (BIT(31) | GENMASK(23, 0))#define CCTLINFO_G7_W7_NC GENMASK(2, 0)#define CCTLINFO_G7_W7_NR GENMASK(5, 3)#define CCTLINFO_G7_W7_NG GENMASK(7, 6)#define CCTLINFO_G7_W7_CB GENMASK(9, 8)#define CCTLINFO_G7_W7_CS GENMASK(11, 10)#define CCTLINFO_G7_W7_CSI_STBC_EN BIT(13)#define CCTLINFO_G7_W7_CSI_LDPC_EN BIT(14)#define CCTLINFO_G7_W7_CSI_PARA_EN BIT(15)#define CCTLINFO_G7_W7_CSI_FIX_RATE GENMASK(27, 16)#define CCTLINFO_G7_W7_CSI_BW GENMASK(31, 29)#define CCTLINFO_G7_W7_ALL (GENMASK(31, 29) | GENMASK(27, 13) | GENMASK(11, 0))#define CCTLINFO_G7_W8_ALL_ACK_SUPPORT BIT(0)#define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT BIT(1)#define CCTLINFO_G7_W8_BSR_OM_UPD_EN BIT(2)#define CCTLINFO_G7_W8_MACID_FWD_IDC BIT(3)#define CCTLINFO_G7_W8_AZ_SEC_EN BIT(4)#define CCTLINFO_G7_W8_CSI_SEC_EN BIT(5)#define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX BIT(6)#define CCTLINFO_G7_W8_CTRL_CNT_VLD BIT(7)#define CCTLINFO_G7_W8_CTRL_CNT GENMASK(11, 8)#define CCTLINFO_G7_W8_RESP_SEC_TYPE GENMASK(15, 12)#define CCTLINFO_G7_W8_ALL GENMASK(15, 0)/* W9~13 are reserved */ #define CCTLINFO_G7_W14_VO_CURR_RATE GENMASK(11, 0)#define CCTLINFO_G7_W14_VI_CURR_RATE GENMASK(23, 12)#define CCTLINFO_G7_W14_BE_CURR_RATE_L GENMASK(31, 24)#define CCTLINFO_G7_W14_ALL GENMASK(31, 0)#define CCTLINFO_G7_W15_BE_CURR_RATE_H GENMASK(3, 0)#define CCTLINFO_G7_W15_BK_CURR_RATE GENMASK(15, 4)#define CCTLINFO_G7_W15_MGNT_CURR_RATE GENMASK(27, 16)#define CCTLINFO_G7_W15_ALL GENMASK(27, 0)struct rtw89_h2c_bcn_upd {#define RTW89_H2C_BCN_UPD_W0_PORT GENMASK(7, 0)#define RTW89_H2C_BCN_UPD_W0_MBSSID GENMASK(15, 8)#define RTW89_H2C_BCN_UPD_W0_BAND GENMASK(23, 16)#define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST GENMASK(31, 24)#define RTW89_H2C_BCN_UPD_W1_MACID GENMASK(7, 0)#define RTW89_H2C_BCN_UPD_W1_SSN_SEL GENMASK(9, 8)#define RTW89_H2C_BCN_UPD_W1_SSN_MODE GENMASK(11, 10)#define RTW89_H2C_BCN_UPD_W1_RATE GENMASK(20, 12)#define RTW89_H2C_BCN_UPD_W1_TXPWR GENMASK(23, 21)#define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN BIT(0)#define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN GENMASK(4, 1)#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A GENMASK(6, 5)#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B GENMASK(8, 7)#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C GENMASK(10, 9)#define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D GENMASK(12, 11)#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A BIT(13)#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B BIT(14)#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C BIT(15)#define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D BIT(16)#define RTW89_H2C_BCN_UPD_W2_CSA_OFST GENMASK(31, 17)struct rtw89_h2c_bcn_upd_be {#define RTW89_H2C_BCN_UPD_BE_W0_PORT GENMASK(7, 0)#define RTW89_H2C_BCN_UPD_BE_W0_MBSSID GENMASK(15, 8)#define RTW89_H2C_BCN_UPD_BE_W0_BAND GENMASK(23, 16)#define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST GENMASK(31, 24)#define RTW89_H2C_BCN_UPD_BE_W1_MACID GENMASK(7, 0)#define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL GENMASK(9, 8)#define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE GENMASK(11, 10)#define RTW89_H2C_BCN_UPD_BE_W1_RATE GENMASK(20, 12)#define RTW89_H2C_BCN_UPD_BE_W1_TXPWR GENMASK(23, 21)#define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT GENMASK(31, 24)#define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN BIT(0)#define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN GENMASK(4, 1)#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A GENMASK(6, 5)#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B GENMASK(8, 7)#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C GENMASK(10, 9)#define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D GENMASK(12, 11)#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A BIT(13)#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B BIT(14)#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C BIT(15)#define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D BIT(16)#define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST GENMASK(31, 17)#define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST GENMASK(15, 0)#define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST GENMASK(31, 16)#define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST GENMASK(15, 0)#define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST GENMASK(31, 16)#define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST GENMASK(15, 0)#define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST GENMASK(31, 16)#define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST GENMASK(15, 0)#define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST GENMASK(31, 16)#define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST GENMASK(15, 0)#define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST GENMASK(30, 16)#define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID BIT(31)struct rtw89_h2c_role_maintain {#define RTW89_H2C_ROLE_MAINTAIN_W0_MACID GENMASK(7, 0)#define RTW89_H2C_ROLE_MAINTAIN_W0_SELF_ROLE GENMASK(9, 8)#define RTW89_H2C_ROLE_MAINTAIN_W0_UPD_MODE GENMASK(12, 10)#define RTW89_H2C_ROLE_MAINTAIN_W0_WIFI_ROLE GENMASK(16, 13)#define RTW89_H2C_ROLE_MAINTAIN_W0_BAND GENMASK(18, 17)#define RTW89_H2C_ROLE_MAINTAIN_W0_PORT GENMASK(21, 19)#define RTW89_H2C_ROLE_MAINTAIN_W0_MACID_EXT GENMASK(31, 24)enum rtw89_fw_sta_type { /* value of RTW89_H2C_JOININFO_W1_STA_TYPE */ struct rtw89_h2c_join {struct rtw89_h2c_join_v1 {#define RTW89_H2C_JOININFO_W0_MACID GENMASK(7, 0)#define RTW89_H2C_JOININFO_W0_OP BIT(8)#define RTW89_H2C_JOININFO_W0_BAND BIT(9)#define RTW89_H2C_JOININFO_W0_WMM GENMASK(11, 10)#define RTW89_H2C_JOININFO_W0_TGR BIT(12)#define RTW89_H2C_JOININFO_W0_ISHESTA BIT(13)#define RTW89_H2C_JOININFO_W0_DLBW GENMASK(15, 14)#define RTW89_H2C_JOININFO_W0_TF_MAC_PAD GENMASK(17, 16)#define RTW89_H2C_JOININFO_W0_DL_T_PE GENMASK(20, 18)#define RTW89_H2C_JOININFO_W0_PORT_ID GENMASK(23, 21)#define RTW89_H2C_JOININFO_W0_NET_TYPE GENMASK(25, 24)#define RTW89_H2C_JOININFO_W0_WIFI_ROLE GENMASK(29, 26)#define RTW89_H2C_JOININFO_W0_SELF_ROLE GENMASK(31, 30)#define RTW89_H2C_JOININFO_W1_STA_TYPE GENMASK(2, 0)#define RTW89_H2C_JOININFO_W1_IS_MLD BIT(3)#define RTW89_H2C_JOININFO_W1_MAIN_MACID GENMASK(11, 4)#define RTW89_H2C_JOININFO_W1_MLO_MODE BIT(12)#define RTW89_H2C_JOININFO_MLO_MODE_MLMR 0#define RTW89_H2C_JOININFO_MLO_MODE_MLSR 1#define RTW89_H2C_JOININFO_W1_EMLSR_CAB BIT(13)#define RTW89_H2C_JOININFO_W1_NSTR_EN BIT(14)#define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE BIT(15)#define RTW89_H2C_JOININFO_W1_EMLSR_PADDING GENMASK(18, 16)#define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY GENMASK(21, 19)#define RTW89_H2C_JOININFO_W2_MACID_EXT GENMASK(7, 0)#define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT GENMASK(15, 8)struct rtw89_h2c_notify_dbcc {#define RTW89_H2C_NOTIFY_DBCC_EN BIT(0)static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val)static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val)static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val)static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val)static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val)static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val)static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val)static inline void SET_LOG_CFG_PATH(void *h2c, u32 val)static inline void SET_LOG_CFG_COMP(void *h2c, u32 val)static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val)struct rtw89_h2c_ba_cam {#define RTW89_H2C_BA_CAM_W0_VALID BIT(0)#define RTW89_H2C_BA_CAM_W0_INIT_REQ BIT(1)#define RTW89_H2C_BA_CAM_W0_ENTRY_IDX GENMASK(3, 2)#define RTW89_H2C_BA_CAM_W0_TID GENMASK(7, 4)#define RTW89_H2C_BA_CAM_W0_MACID GENMASK(15, 8)#define RTW89_H2C_BA_CAM_W0_BMAP_SIZE GENMASK(19, 16)#define RTW89_H2C_BA_CAM_W0_SSN GENMASK(31, 20)#define RTW89_H2C_BA_CAM_W1_UID GENMASK(7, 0)#define RTW89_H2C_BA_CAM_W1_STD_EN BIT(8)#define RTW89_H2C_BA_CAM_W1_BAND BIT(9)#define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 GENMASK(31, 28)struct rtw89_h2c_ba_cam_v1 {#define RTW89_H2C_BA_CAM_V1_W0_VALID BIT(0)#define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ BIT(1)#define RTW89_H2C_BA_CAM_V1_W0_TID_MASK GENMASK(7, 4)#define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK GENMASK(15, 8)#define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK GENMASK(19, 16)#define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK GENMASK(31, 20)#define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK GENMASK(7, 0)#define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN BIT(8)#define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL BIT(9)#define RTW89_H2C_BA_CAM_V1_W1_MLD_EN BIT(10)#define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK GENMASK(31, 24)struct rtw89_h2c_ba_cam_init {#define RTW89_H2C_BA_CAM_INIT_USERS_MASK GENMASK(7, 0)#define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK GENMASK(19, 12)#define RTW89_H2C_BA_CAM_INIT_BAND_SEL BIT(24)static inline void SET_LPS_PARM_MACID(void *h2c, u32 val)static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val)static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val)static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val)static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val)static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val)static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val)static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val)static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val)static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val)struct rtw89_h2c_lps_ch_info {struct {struct rtw89_h2c_lps_ml_cmn_info {struct rtw89_h2c_trig_cpu_except {#define RTW89_H2C_CPU_EXCEPTION_TYPE GENMASK(31, 0)static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val)static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val)static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val)static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val)static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val)static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val)static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val)static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val)static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val)static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val)static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val)struct rtw89_h2c_wow_global {struct rtw89_wow_key_info key_info;#define RTW89_H2C_WOW_GLOBAL_W0_ENABLE BIT(0)#define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT BIT(1)#define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE BIT(2)#define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED BIT(3)#define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID GENMASK(15, 8)#define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO GENMASK(23, 16)#define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO GENMASK(31, 24)#define RTW89_MAX_SUPPORT_NL_NUM 16struct rtw89_h2c_cfg_nlo {#define RTW89_H2C_NLO_W0_ENABLE BIT(0)#define RTW89_H2C_NLO_W0_IGNORE_CIPHER BIT(2)#define RTW89_H2C_NLO_W0_MACID GENMASK(31, 24)static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val)static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val)static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val)static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val)static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val)static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val)static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val)
Messung V0.5 C=97 H=94 G=95
¤ Dauer der Verarbeitung: 0.40 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
