// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 MediaTek Inc. * Author: Jie Qiu <jie.qiu@mediatek.com> #include "phy-mtk-hdmi.h" #include "phy-mtk-io.h" #define HDMI_CON0 0x00#define RG_HDMITX_PLL_EN BIT(31)#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)#define RG_HDMITX_PLL_IR GENMASK(15, 12)#define RG_HDMITX_PLL_IC GENMASK(11, 8)#define RG_HDMITX_PLL_BP GENMASK(7, 4)#define RG_HDMITX_PLL_BR GENMASK(3, 2)#define RG_HDMITX_PLL_BC GENMASK(1, 0)#define HDMI_CON1 0x04#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)#define RG_HDMITX_PLL_AUTOK_EN BIT(28)#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)#define RG_HDMITX_PLL_BAND GENMASK(21, 16)#define RG_HDMITX_PLL_REF_SEL BIT(15)#define RG_HDMITX_PLL_BIAS_EN BIT(14)#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)#define RG_HDMITX_PLL_TXDIV_EN BIT(12)#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)#define RG_HDMITX_PLL_LVROD_EN BIT(9)#define RG_HDMITX_PLL_MONVC_EN BIT(8)#define RG_HDMITX_PLL_MONCK_EN BIT(7)#define RG_HDMITX_PLL_MONREF_EN BIT(6)#define RG_HDMITX_PLL_TST_EN BIT(5)#define RG_HDMITX_PLL_TST_CK_EN BIT(4)#define RG_HDMITX_PLL_TST_SEL GENMASK(3, 0)#define HDMI_CON2 0x08#define RGS_HDMITX_PLL_AUTOK_BAND GENMASK(14, 8)#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)#define RG_HDMITX_EN_TX_CKLDO BIT(0)#define HDMI_CON3 0x0c#define RG_HDMITX_SER_EN GENMASK(31, 28)#define RG_HDMITX_PRD_EN GENMASK(27, 24)#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)#define RG_HDMITX_DRV_EN GENMASK(19, 16)#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)#define RG_HDMITX_MHLCK_FORCE BIT(10)#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)#define RG_HDMITX_MHLCK_EN BIT(8)#define RG_HDMITX_SER_DIN_SEL GENMASK(7, 4)#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)#define RG_HDMITX_SER_BIST_TOG BIT(2)#define RG_HDMITX_SER_DIN_TOG BIT(1)#define RG_HDMITX_SER_CLKDIG_INV BIT(0)#define HDMI_CON4 0x10#define RG_HDMITX_PRD_IBIAS_CLK GENMASK(27, 24)#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)#define HDMI_CON5 0x14#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)#define HDMI_CON6 0x18#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)#define HDMI_CON7 0x1c#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)#define RG_HDMITX_SER_DIN GENMASK(25, 16)#define RG_HDMITX_CHLDC_TST GENMASK(15, 12)#define RG_HDMITX_CHLCK_TST GENMASK(11, 8)#define RG_HDMITX_RESERVE GENMASK(7, 0)#define HDMI_CON8 0x20#define RGS_HDMITX_2T1_LEV GENMASK(19, 16)#define RGS_HDMITX_2T1_EDG GENMASK(15, 12)#define RGS_HDMITX_5T1_LEV GENMASK(11, 8)#define RGS_HDMITX_5T1_EDG GENMASK(7, 4)#define RGS_HDMITX_PLUG_TST BIT(0)static int mtk_hdmi_pll_prepare(struct clk_hw *hw)struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);void __iomem *base = hdmi_phy->regs;return 0;static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);void __iomem *base = hdmi_phy->regs;static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,unsigned long *parent_rate)struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);if (rate <= 74250000)else return rate;static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,unsigned long parent_rate)struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);void __iomem *base = hdmi_phy->regs;unsigned int pre_div;unsigned int div;unsigned int pre_ibias;unsigned int hdmi_ibias;unsigned int imp_en;"%s: %lu Hz, parent: %lu Hz\n" , __func__,if (rate <= 27000000) {else if (rate <= 74250000) {else {if (rate < 165000000) {else {return 0;static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,unsigned long parent_rate)struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);return hdmi_phy->pll_rate;static const struct clk_ops mtk_hdmi_phy_pll_ops = {static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {"Jie Qiu " );"MediaTek MT8173 HDMI PHY Driver" );"GPL v2" );
Messung V0.5 C=97 H=98 G=97
¤ Dauer der Verarbeitung: 0.3 Sekunden
¤ *© Formatika GbR, Deutschland
