// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2017, The Linux Foundation. All rights reserved. #include <linux/clk.h>#include <linux/clk-provider.h>#include <linux/delay.h>#include <linux/err.h>#include <linux/io.h>#include <linux/iopoll.h>#include <linux/kernel.h>#include <linux/module.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/phy/phy.h>#include <linux/platform_device.h>#include <linux/regulator/consumer.h>#include <linux/reset.h>#include <linux/slab.h>#include <ufs/unipro.h>#include "phy-qcom-qmp-common.h" #include "phy-qcom-qmp.h" #include "phy-qcom-qmp-pcs-ufs-v2.h" #include "phy-qcom-qmp-pcs-ufs-v3.h" #include "phy-qcom-qmp-pcs-ufs-v4.h" #include "phy-qcom-qmp-pcs-ufs-v5.h" #include "phy-qcom-qmp-pcs-ufs-v6.h" #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" #include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h" /* QPHY_PCS_READY_STATUS bit */ #define PCS_READY BIT(0)#define PHY_INIT_COMPLETE_TIMEOUT 10000#define NUM_OVERLAY 2/* set of registers with offsets different per-PHY */ enum qphy_reg_layout {/* PCS registers */ /* Keep last to ensure regs_layout arrays are properly initialized */ static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = {static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = {static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = {static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = {static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = {static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = {static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {/* 8 us */ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = {static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = {static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = {static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = {static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = {static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = {static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = {static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = {static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = {static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = {static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = {static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = {static const struct qmp_phy_init_tbl sm8475_ufsphy_serdes[] = {static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_serdes[] = {static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_pcs[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = {static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = {static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = {static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = {static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = {static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = {static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = {static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = {static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = {static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = {static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = {struct qmp_ufs_offsets {struct qmp_phy_cfg_tbls {/* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes;int serdes_num;const struct qmp_phy_init_tbl *tx;int tx_num;const struct qmp_phy_init_tbl *rx;int rx_num;const struct qmp_phy_init_tbl *pcs;int pcs_num;/* Maximum supported Gear of this tbls */ /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg {int lanes;const struct qmp_ufs_offsets *offsets;/* Maximum supported Gear of this config */ /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_cfg_tbls tbls;/* Additional sequence for HS Series B */ const struct qmp_phy_cfg_tbls tbls_hs_b;/* Additional sequence for different HS Gears */ const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];/* regulators to be requested */ const char * const *vreg_list;int num_vregs;/* array of registers with different offsets */ const unsigned int *regs;/* true, if PCS block has no separate SW_RESET register */ bool no_pcs_sw_reset;struct qmp_ufs {struct device *dev;const struct qmp_phy_cfg *cfg;void __iomem *serdes;void __iomem *pcs;void __iomem *pcs_misc;void __iomem *tx;void __iomem *rx;void __iomem *tx2;void __iomem *rx2;struct clk_bulk_data *clks;int num_clks;struct regulator_bulk_data *vregs;struct reset_control *ufs_reset;struct phy *phy;static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)/* ensure that above write is through */ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)/* ensure that above write is through */ /* list of regulators */ static const char * const qmp_phy_vreg_l[] = {"vdda-phy" , "vdda-pll" ,static const struct qmp_ufs_offsets qmp_ufs_offsets = {static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {true ,static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {true ,static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {true ,static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {true ,static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {static const struct qmp_phy_cfg sm8475_ufsphy_cfg = {
Messung V0.5 C=98 H=100 G=98
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