// SPDX-License-Identifier: GPL-2.0+ /* * Actions Semi S500 SoC Pinctrl driver * * Copyright (c) 2014 Actions Semi Inc. * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com> #include <linux/module.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/pinctrl/pinconf-generic.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-owl.h" /* Pinctrl registers offset */ #define MFCTL0 (0x0040)#define MFCTL1 (0x0044)#define MFCTL2 (0x0048)#define MFCTL3 (0x004C)#define PAD_PULLCTL0 (0x0060)#define PAD_PULLCTL1 (0x0064)#define PAD_PULLCTL2 (0x0068)#define PAD_ST0 (0x006C)#define PAD_ST1 (0x0070)#define PAD_CTL (0x0074)#define PAD_DRV0 (0x0080)#define PAD_DRV1 (0x0084)#define PAD_DRV2 (0x0088)#define _GPIOA(offset) (offset)#define _GPIOB(offset) (32 + (offset))#define _GPIOC(offset) (64 + (offset))#define _GPIOD(offset) (96 + (offset))#define _GPIOE(offset) (128 + (offset))#define NUM_GPIOS (_GPIOE(3) + 1)#define _PIN(offset) (NUM_GPIOS + (offset))#define DNAND_DQS _GPIOA(12)#define DNAND_DQSN _GPIOA(13)#define ETH_TXD0 _GPIOA(14)#define ETH_TXD1 _GPIOA(15)#define ETH_TXEN _GPIOA(16)#define ETH_RXER _GPIOA(17)#define ETH_CRS_DV _GPIOA(18)#define ETH_RXD1 _GPIOA(19)#define ETH_RXD0 _GPIOA(20)#define ETH_REF_CLK _GPIOA(21)#define ETH_MDC _GPIOA(22)#define ETH_MDIO _GPIOA(23)#define SIRQ0 _GPIOA(24)#define SIRQ1 _GPIOA(25)#define SIRQ2 _GPIOA(26)#define I2S_D0 _GPIOA(27)#define I2S_BCLK0 _GPIOA(28)#define I2S_LRCLK0 _GPIOA(29)#define I2S_MCLK0 _GPIOA(30)#define I2S_D1 _GPIOA(31)#define I2S_BCLK1 _GPIOB(0)#define I2S_LRCLK1 _GPIOB(1)#define I2S_MCLK1 _GPIOB(2)#define KS_IN0 _GPIOB(3)#define KS_IN1 _GPIOB(4)#define KS_IN2 _GPIOB(5)#define KS_IN3 _GPIOB(6)#define KS_OUT0 _GPIOB(7)#define KS_OUT1 _GPIOB(8)#define KS_OUT2 _GPIOB(9)#define LVDS_OEP _GPIOB(10)#define LVDS_OEN _GPIOB(11)#define LVDS_ODP _GPIOB(12)#define LVDS_ODN _GPIOB(13)#define LVDS_OCP _GPIOB(14)#define LVDS_OCN _GPIOB(15)#define LVDS_OBP _GPIOB(16)#define LVDS_OBN _GPIOB(17)#define LVDS_OAP _GPIOB(18)#define LVDS_OAN _GPIOB(19)#define LVDS_EEP _GPIOB(20)#define LVDS_EEN _GPIOB(21)#define LVDS_EDP _GPIOB(22)#define LVDS_EDN _GPIOB(23)#define LVDS_ECP _GPIOB(24)#define LVDS_ECN _GPIOB(25)#define LVDS_EBP _GPIOB(26)#define LVDS_EBN _GPIOB(27)#define LVDS_EAP _GPIOB(28)#define LVDS_EAN _GPIOB(29)#define LCD0_D18 _GPIOB(30)#define LCD0_D17 _GPIOB(31)#define DSI_DP3 _GPIOC(0)#define DSI_DN3 _GPIOC(1)#define DSI_DP1 _GPIOC(2)#define DSI_DN1 _GPIOC(3)#define DSI_CP _GPIOC(4)#define DSI_CN _GPIOC(5)#define DSI_DP0 _GPIOC(6)#define DSI_DN0 _GPIOC(7)#define DSI_DP2 _GPIOC(8)#define DSI_DN2 _GPIOC(9)#define SD0_D0 _GPIOC(10)#define SD0_D1 _GPIOC(11)#define SD0_D2 _GPIOC(12)#define SD0_D3 _GPIOC(13)#define SD1_D0 _GPIOC(14) /* SD0_D4 */ #define SD1_D1 _GPIOC(15) /* SD0_D5 */ #define SD1_D2 _GPIOC(16) /* SD0_D6 */ #define SD1_D3 _GPIOC(17) /* SD0_D7 */ #define SD0_CMD _GPIOC(18)#define SD0_CLK _GPIOC(19)#define SD1_CMD _GPIOC(20)#define SD1_CLK _GPIOC(21)#define SPI0_SCLK _GPIOC(22)#define SPI0_SS _GPIOC(23)#define SPI0_MISO _GPIOC(24)#define SPI0_MOSI _GPIOC(25)#define UART0_RX _GPIOC(26)#define UART0_TX _GPIOC(27)#define I2C0_SCLK _GPIOC(28)#define I2C0_SDATA _GPIOC(29)#define SENSOR0_PCLK _GPIOC(31)#define SENSOR0_CKOUT _GPIOD(10)#define DNAND_ALE _GPIOD(12)#define DNAND_CLE _GPIOD(13)#define DNAND_CEB0 _GPIOD(14)#define DNAND_CEB1 _GPIOD(15)#define DNAND_CEB2 _GPIOD(16)#define DNAND_CEB3 _GPIOD(17)#define UART2_RX _GPIOD(18)#define UART2_TX _GPIOD(19)#define UART2_RTSB _GPIOD(20)#define UART2_CTSB _GPIOD(21)#define UART3_RX _GPIOD(22)#define UART3_TX _GPIOD(23)#define UART3_RTSB _GPIOD(24)#define UART3_CTSB _GPIOD(25)#define PCM1_IN _GPIOD(28)#define PCM1_CLK _GPIOD(29)#define PCM1_SYNC _GPIOD(30)#define PCM1_OUT _GPIOD(31)#define I2C1_SCLK _GPIOE(0)#define I2C1_SDATA _GPIOE(1)#define I2C2_SCLK _GPIOE(2)#define I2C2_SDATA _GPIOE(3)#define CSI_DN0 _PIN(0)#define CSI_DP0 _PIN(1)#define CSI_DN1 _PIN(2)#define CSI_DP1 _PIN(3)#define CSI_CN _PIN(4)#define CSI_CP _PIN(5)#define CSI_DN2 _PIN(6)#define CSI_DP2 _PIN(7)#define CSI_DN3 _PIN(8)#define CSI_DP3 _PIN(9)#define DNAND_D0 _PIN(10)#define DNAND_D1 _PIN(11)#define DNAND_D2 _PIN(12)#define DNAND_D3 _PIN(13)#define DNAND_D4 _PIN(14)#define DNAND_D5 _PIN(15)#define DNAND_D6 _PIN(16)#define DNAND_D7 _PIN(17)#define DNAND_WRB _PIN(18)#define DNAND_RDB _PIN(19)#define DNAND_RDBN _PIN(20)#define DNAND_RB _PIN(21)#define PORB _PIN(22)#define CLKO_25M _PIN(23)#define BSEL _PIN(24)#define PKG0 _PIN(25)#define PKG1 _PIN(26)#define PKG2 _PIN(27)#define PKG3 _PIN(28)#define _FIRSTPAD _GPIOA(0)#define _LASTPAD PKG3#define NUM_PADS (_PIN(28) + 1)static const struct pinctrl_pin_desc s500_pads[] = {"dnand_dqs" ),"dnand_dqsn" ),"eth_txd0" ),"eth_txd1" ),"eth_txen" ),"eth_rxer" ),"eth_crs_dv" ),"eth_rxd1" ),"eth_rxd0" ),"eth_ref_clk" ),"eth_mdc" ),"eth_mdio" ),"sirq0" ),"sirq1" ),"sirq2" ),"i2s_d0" ),"i2s_bclk0" ),"i2s_lrclk0" ),"i2s_mclk0" ),"i2s_d1" ),"i2s_bclk1" ),"i2s_lrclk1" ),"i2s_mclk1" ),"ks_in0" ),"ks_in1" ),"ks_in2" ),"ks_in3" ),"ks_out0" ),"ks_out1" ),"ks_out2" ),"lvds_oep" ),"lvds_oen" ),"lvds_odp" ),"lvds_odn" ),"lvds_ocp" ),"lvds_ocn" ),"lvds_obp" ),"lvds_obn" ),"lvds_oap" ),"lvds_oan" ),"lvds_eep" ),"lvds_een" ),"lvds_edp" ),"lvds_edn" ),"lvds_ecp" ),"lvds_ecn" ),"lvds_ebp" ),"lvds_ebn" ),"lvds_eap" ),"lvds_ean" ),"lcd0_d18" ),"lcd0_d17" ),"dsi_dp3" ),"dsi_dn3" ),"dsi_dp1" ),"dsi_dn1" ),"dsi_cp" ),"dsi_cn" ),"dsi_dp0" ),"dsi_dn0" ),"dsi_dp2" ),"dsi_dn2" ),"sd0_d0" ),"sd0_d1" ),"sd0_d2" ),"sd0_d3" ),"sd1_d0" ),"sd1_d1" ),"sd1_d2" ),"sd1_d3" ),"sd0_cmd" ),"sd0_clk" ),"sd1_cmd" ),"sd1_clk" ),"spi0_sclk" ),"spi0_ss" ),"spi0_miso" ),"spi0_mosi" ),"uart0_rx" ),"uart0_tx" ),"i2c0_sclk" ),"i2c0_sdata" ),"sensor0_pclk" ),"sensor0_ckout" ),"dnand_ale" ),"dnand_cle" ),"dnand_ceb0" ),"dnand_ceb1" ),"dnand_ceb2" ),"dnand_ceb3" ),"uart2_rx" ),"uart2_tx" ),"uart2_rtsb" ),"uart2_ctsb" ),"uart3_rx" ),"uart3_tx" ),"uart3_rtsb" ),"uart3_ctsb" ),"pcm1_in" ),"pcm1_clk" ),"pcm1_sync" ),"pcm1_out" ),"i2c1_sclk" ),"i2c1_sdata" ),"i2c2_sclk" ),"i2c2_sdata" ),"csi_dn0" ),"csi_dp0" ),"csi_dn1" ),"csi_dp1" ),"csi_dn2" ),"csi_dp2" ),"csi_dn3" ),"csi_dp3" ),"csi_cn" ),"csi_cp" ),"dnand_d0" ),"dnand_d1" ),"dnand_d2" ),"dnand_d3" ),"dnand_d4" ),"dnand_d5" ),"dnand_d6" ),"dnand_d7" ),"dnand_rb" ),"dnand_rdb" ),"dnand_rdbn" ),"dnand_wrb" ),"porb" ),"clko_25m" ),"bsel" ),"pkg0" ),"pkg1" ),"pkg2" ),"pkg3" ),enum s500_pinmux_functions {/*S500_MUX_I2C2,*/ /*S500_MUX_SIRQ0,*/ /*S500_MUX_SIRQ1,*/ /*S500_MUX_SIRQ2,*/ /* MFPCTL group data */ /* mfp0_31_26 reserved */ /* mfp0_25_23 */ static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 };static unsigned int lcd0_d18_mfp_funcs[] = { S500_MUX_NOR,/* mfp0_22_20 */ static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV };static unsigned int rmii_crs_dv_mfp_funcs[] = { S500_MUX_ETH_RMII,/* mfp0_18_16_eth_txd0 */ static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 };static unsigned int rmii_txd0_mfp_funcs[] = { S500_MUX_ETH_RMII,/* mfp0_18_16_eth_txd1 */ static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 };static unsigned int rmii_txd1_mfp_funcs[] = { S500_MUX_ETH_RMII,/* mfp0_15_13_rmii_txen */ static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN };static unsigned int rmii_txen_mfp_funcs[] = { S500_MUX_ETH_RMII,/* mfp0_15_13_rmii_rxen */ static unsigned int rmii_rxen_mfp_pads[] = { ETH_RXER };static unsigned int rmii_rxen_mfp_funcs[] = { S500_MUX_ETH_RMII,/* mfp0_12_11 reserved */ /* mfp0_10_8_rmii_rxd1 */ static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 };static unsigned int rmii_rxd1_mfp_funcs[] = { S500_MUX_ETH_RMII,/* mfp0_10_8_rmii_rxd0 */ static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 };static unsigned int rmii_rxd0_mfp_funcs[] = { S500_MUX_ETH_RMII,/* mfp0_7_6 */ static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };static unsigned int rmii_ref_clk_mfp_funcs[] = { S500_MUX_ETH_RMII,/* mfp0_5 */ static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };static unsigned int i2s_d0_mfp_funcs[] = { S500_MUX_I2S0,/* mfp0_4_3 */ static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0, I2S_MCLK0 };static unsigned int i2s_pcm1_mfp_funcs[] = { S500_MUX_I2S0,/* mfp0_2_1_i2s0 */ static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 };static unsigned int i2s0_pcm0_mfp_funcs[] = { S500_MUX_I2S0,/* mfp0_2_1_i2s1 */ static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1, I2S_LRCLK1,static unsigned int i2s1_pcm0_mfp_funcs[] = { S500_MUX_I2S1,/* mfp0_0 */ static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };static unsigned int i2s_d1_mfp_funcs[] = { S500_MUX_I2S1,/* mfp1_31_29_ks_in0 */ static unsigned int ks_in0_mfp_pads[] = { KS_IN0 };static unsigned int ks_in0_mfp_funcs[] = { S500_MUX_KS,/* mfp1_31_29_ks_in1 */ static unsigned int ks_in1_mfp_pads[] = { KS_IN1 };static unsigned int ks_in1_mfp_funcs[] = { S500_MUX_KS,/* mfp1_31_29_ks_in2 */ static unsigned int ks_in2_mfp_pads[] = { KS_IN2 };static unsigned int ks_in2_mfp_funcs[] = { S500_MUX_KS,/* mfp1_28_26_ks_in3 */ static unsigned int ks_in3_mfp_pads[] = { KS_IN3 };static unsigned int ks_in3_mfp_funcs[] = { S500_MUX_KS,/* mfp1_28_26_ks_out0 */ static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 };static unsigned int ks_out0_mfp_funcs[] = { S500_MUX_KS,/* mfp1_28_26_ks_out1 */ static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 };static unsigned int ks_out1_mfp_funcs[] = { S500_MUX_KS,/* mfp1_25_23 */ static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 };static unsigned int ks_out2_mfp_funcs[] = { S500_MUX_SD0,/* mfp1_22_21 */ static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP, LVDS_OEN,static unsigned int lvds_o_pn_mfp_funcs[] = { S500_MUX_LVDS,/* mfp1_20_19 */ static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 };static unsigned int dsi_dn0_mfp_funcs[] = { S500_MUX_DSI,/* mfp1_18_17 */ static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 };static unsigned int dsi_dp2_mfp_funcs[] = { S500_MUX_DSI,/* mfp1_16_14 */ static unsigned int lcd0_d17_mfp_pads[] = { LCD0_D17 };static unsigned int lcd0_d17_mfp_funcs[] = { S500_MUX_NOR,/* mfp1_13_12 */ static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 };static unsigned int dsi_dp3_mfp_funcs[] = { S500_MUX_DSI,/* mfp1_11_10 */ static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 };static unsigned int dsi_dn3_mfp_funcs[] = { S500_MUX_DSI,/* mfp1_9_7 */ static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 };static unsigned int dsi_dp0_mfp_funcs[] = { S500_MUX_DSI,/* mfp1_6_5 */ static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP, LVDS_EEN };static unsigned int lvds_ee_pn_mfp_funcs[] = { S500_MUX_LVDS,/* mfp1_4_3 */ static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SCLK, SPI0_MOSI };static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S500_MUX_SPI0,/* mfp1_2_0 */ static unsigned int spi0_i2s_pcm_mfp_pads[] = { SPI0_SS, SPI0_MISO };static unsigned int spi0_i2s_pcm_mfp_funcs[] = { S500_MUX_SPI0,/* mfp2_31 reserved */ /* mfp2_30_29 */ static unsigned int dsi_dnp1_cp_mfp_pads[] = { DSI_DP1, DSI_CP, DSI_CN };static unsigned int dsi_dnp1_cp_mfp_funcs[] = { S500_MUX_DSI,/* mfp2_28_27 */ static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP, LVDS_EDN,static unsigned int lvds_e_pn_mfp_funcs[] = { S500_MUX_LVDS,/* mfp2_26_24 */ static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 };static unsigned int dsi_dn2_mfp_funcs[] = { S500_MUX_DSI,/* mfp2_23 */ static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };static unsigned int uart2_rtsb_mfp_funcs[] = { S500_MUX_UART2,/* mfp2_22 */ static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };static unsigned int uart2_ctsb_mfp_funcs[] = { S500_MUX_UART2,/* mfp2_21 */ static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };static unsigned int uart3_rtsb_mfp_funcs[] = { S500_MUX_UART3,/* mfp2_20 */ static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };static unsigned int uart3_ctsb_mfp_funcs[] = { S500_MUX_UART3,/* mfp2_19_17 */ static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };static unsigned int sd0_d0_mfp_funcs[] = { S500_MUX_SD0,/* mfp2_16_14 */ static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };static unsigned int sd0_d1_mfp_funcs[] = { S500_MUX_SD0,/* mfp2_13_11 */ static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2, SD0_D3 };static unsigned int sd0_d2_d3_mfp_funcs[] = { S500_MUX_SD0,/* mfp2_10_9 */ static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1,static unsigned int sd1_d0_d3_mfp_funcs[] = { S500_MUX_SD0,/* mfp2_8_7 */ static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };static unsigned int sd0_cmd_mfp_funcs[] = { S500_MUX_SD0,/* mfp2_6_5 */ static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };static unsigned int sd0_clk_mfp_funcs[] = { S500_MUX_SD0,/* mfp2_4_3 */ static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD };static unsigned int sd1_cmd_mfp_funcs[] = { S500_MUX_SD1,/* mfp2_2_0 */ static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };static unsigned int uart0_rx_mfp_funcs[] = { S500_MUX_UART0,/* mfp3_31 reserved */ /* mfp3_30 */ static unsigned int clko_25m_mfp_pads[] = { CLKO_25M };static unsigned int clko_25m_mfp_funcs[] = { S500_MUX_RESERVED,/* mfp3_29_28 */ static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN, CSI_CP };static unsigned int csi_cn_cp_mfp_funcs[] = { S500_MUX_MIPI_CSI,/* mfp3_27_24 reserved */ /* mfp3_23_22 */ static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT };static unsigned int sens0_ckout_mfp_funcs[] = { S500_MUX_SENS0,/* mfp3_21_19 */ static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };static unsigned int uart0_tx_mfp_funcs[] = { S500_MUX_UART0,/* mfp3_18_16 */ static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK,static unsigned int i2c0_mfp_funcs[] = { S500_MUX_I2C0,/* mfp3_15_14 */ static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0, CSI_DN1,static unsigned int csi_dn_dp_mfp_funcs[] = { S500_MUX_MIPI_CSI,/* mfp3_13_12 */ static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK };static unsigned int sen0_pclk_mfp_funcs[] = { S500_MUX_SENS0,/* mfp3_11_10 */ static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN };static unsigned int pcm1_in_mfp_funcs[] = { S500_MUX_PCM1,/* mfp3_9_8 */ static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };static unsigned int pcm1_clk_mfp_funcs[] = { S500_MUX_PCM1,/* mfp3_7_6 */ static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };static unsigned int pcm1_sync_mfp_funcs[] = { S500_MUX_PCM1,/* mfp3_5_4 */ static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT };static unsigned int pcm1_out_mfp_funcs[] = { S500_MUX_PCM1,/* mfp3_3 */ static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0, DNAND_D1,static unsigned int dnand_data_wr_mfp_funcs[] = { S500_MUX_NAND,/* mfp3_2 */ static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE,static unsigned int dnand_acle_ce0_mfp_funcs[] = { S500_MUX_NAND,/* mfp3_1_0_nand_ceb2 */ static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 };static unsigned int nand_ceb2_mfp_funcs[] = { S500_MUX_NAND,/* mfp3_1_0_nand_ceb3 */ static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 };static unsigned int nand_ceb3_mfp_funcs[] = { S500_MUX_NAND,/* PADDRV group data */ /* paddrv0_29_28 */ static unsigned int sirq_drv_pads[] = { SIRQ0, SIRQ1, SIRQ2 };/* paddrv0_23_22 */ static unsigned int rmii_txd01_txen_drv_pads[] = { ETH_TXD0, ETH_TXD1,/* paddrv0_21_20 */ static unsigned int rmii_rxer_drv_pads[] = { ETH_RXER };/* paddrv0_19_18 */ static unsigned int rmii_crs_drv_pads[] = { ETH_CRS_DV };/* paddrv0_17_16 */ static unsigned int rmii_rxd10_drv_pads[] = { ETH_RXD0, ETH_RXD1 };/* paddrv0_15_14 */ static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK };/* paddrv0_13_12 */ static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO };/* paddrv0_11_10 */ static unsigned int i2s_d0_drv_pads[] = { I2S_D0 };/* paddrv0_9_8 */ static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 };/* paddrv0_7_6 */ static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0,/* paddrv0_5_4 */ static unsigned int i2s13_drv_pads[] = { I2S_BCLK1, I2S_LRCLK1,/* paddrv0_3_2 */ static unsigned int pcm1_drv_pads[] = { PCM1_IN, PCM1_CLK,/* paddrv0_1_0 */ static unsigned int ks_in_drv_pads[] = { KS_IN0, KS_IN1,/* paddrv1_31_30 */ static unsigned int ks_out_drv_pads[] = { KS_OUT0, KS_OUT1, KS_OUT2 };/* paddrv1_29_28 */ static unsigned int lvds_all_drv_pads[] = { LVDS_OEP, LVDS_OEN,/* paddrv1_27_26 */ static unsigned int lcd_dsi_drv_pads[] = { DSI_DP3, DSI_DN3, DSI_DP1,/* paddrv1_25_24 */ static unsigned int dsi_drv_pads[] = { DSI_DP0, DSI_DN0,/* paddrv1_23_22 */ static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0, SD0_D1,/* paddrv1_21_20 */ static unsigned int sd1_d0_d3_drv_pads[] = { SD1_D0, SD1_D1,/* paddrv1_19_18 */ static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD };/* paddrv1_17_16 */ static unsigned int sd0_clk_drv_pads[] = { SD0_CLK };/* paddrv1_15_14 */ static unsigned int sd1_cmd_drv_pads[] = { SD1_CMD };/* paddrv1_13_12 */ static unsigned int sd1_clk_drv_pads[] = { SD1_CLK };/* paddrv1_11_10 */ static unsigned int spi0_all_drv_pads[] = { SPI0_SCLK, SPI0_SS,/* paddrv2_31_30 */ static unsigned int uart0_rx_drv_pads[] = { UART0_RX };/* paddrv2_29_28 */ static unsigned int uart0_tx_drv_pads[] = { UART0_TX };/* paddrv2_27_26 */ static unsigned int uart2_all_drv_pads[] = { UART2_RX, UART2_TX,/* paddrv2_24_23 */ static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK, I2C0_SDATA };/* paddrv2_22_21 */ static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK, I2C1_SDATA,/* paddrv2_19_18 */ static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK };/* paddrv2_13_12 */ static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT };/* paddrv2_3_2 */ static unsigned int uart3_all_drv_pads[] = { UART3_RX, UART3_TX,/* Pinctrl groups */ static const struct owl_pingroup s500_groups[] = {static const char * const nor_groups[] = {"lcd0_d18_mfp" ,"i2s_d0_mfp" ,"i2s0_pcm0_mfp" ,"i2s1_pcm0_mfp" ,"i2s_d1_mfp" ,"ks_in2_mfp" ,"ks_in1_mfp" ,"ks_in0_mfp" ,"ks_in3_mfp" ,"ks_out0_mfp" ,"ks_out1_mfp" ,"ks_out2_mfp" ,"lcd0_d17_mfp" ,"lvds_ee_pn_mfp" ,"spi0_i2c_pcm_mfp" ,"spi0_i2s_pcm_mfp" ,"lvds_e_pn_mfp" ,"sd0_d0_mfp" ,"sd0_d1_mfp" ,"sd0_d2_d3_mfp" ,"sd1_d0_d3_mfp" ,"sd0_cmd_mfp" ,"sd1_cmd_mfp" ,"sens0_ckout_mfp" ,"sen0_pclk_mfp" ,static const char * const eth_rmii_groups[] = {"rmii_crs_dv_mfp" ,"rmii_txd0_mfp" ,"rmii_txd1_mfp" ,"rmii_txen_mfp" ,"rmii_rxen_mfp" ,"rmii_rxd1_mfp" ,"rmii_rxd0_mfp" ,"rmii_ref_clk_mfp" ,static const char * const eth_smii_groups[] = {"rmii_crs_dv_mfp" ,"rmii_txd0_mfp" ,"rmii_txd1_mfp" ,"rmii_ref_clk_mfp" ,static const char * const spi0_groups[] = {"dsi_dn0_mfp" ,"dsi_dp2_mfp" ,"dsi_dp0_mfp" ,"spi0_i2c_pcm_mfp" ,"spi0_i2s_pcm_mfp" ,"dsi_dn2_mfp" ,static const char * const spi1_groups[] = {"uart0_rx_mfp" ,"uart0_tx_mfp" ,"i2c0_mfp" ,static const char * const spi2_groups[] = {"rmii_crs_dv_mfp" ,"rmii_txd0_mfp" ,"rmii_txd1_mfp" ,"rmii_ref_clk_mfp" ,"dnand_acle_ce0_mfp" ,static const char * const spi3_groups[] = {"rmii_txen_mfp" ,"rmii_rxen_mfp" ,"rmii_rxd1_mfp" ,"rmii_rxd0_mfp" ,static const char * const sens0_groups[] = {"csi_cn_cp_mfp" ,"sens0_ckout_mfp" ,"csi_dn_dp_mfp" ,"sen0_pclk_mfp" ,static const char * const sens1_groups[] = {"lcd0_d18_mfp" ,"ks_in2_mfp" ,"ks_in1_mfp" ,"ks_in0_mfp" ,"ks_in3_mfp" ,"ks_out0_mfp" ,"ks_out1_mfp" ,"ks_out2_mfp" ,"sens0_ckout_mfp" ,"pcm1_in_mfp" ,"pcm1_clk_mfp" ,"pcm1_sync_mfp" ,"pcm1_out_mfp" ,static const char * const uart0_groups[] = {"uart2_rtsb_mfp" ,"uart2_ctsb_mfp" ,"uart0_rx_mfp" ,"uart0_tx_mfp" ,static const char * const uart1_groups[] = {"sd0_d2_d3_mfp" ,"i2c0_mfp" ,static const char * const uart2_groups[] = {"rmii_txen_mfp" ,"rmii_rxen_mfp" ,"rmii_rxd1_mfp" ,"rmii_rxd0_mfp" ,"dsi_dn0_mfp" ,"dsi_dp2_mfp" ,"dsi_dp0_mfp" ,"dsi_dn2_mfp" ,"uart2_rtsb_mfp" ,"uart2_ctsb_mfp" ,"sd0_d0_mfp" ,"sd0_d1_mfp" ,"sd0_d2_d3_mfp" ,"uart0_rx_mfp" ,"uart0_tx_mfp" ,"i2c0_mfp" ,static const char * const uart3_groups[] = {"uart3_rtsb_mfp" ,"uart3_ctsb_mfp" ,static const char * const uart4_groups[] = {"rmii_crs_dv_mfp" ,"rmii_ref_clk_mfp" ,"pcm1_in_mfp" ,"pcm1_clk_mfp" ,static const char * const uart5_groups[] = {"rmii_rxd1_mfp" ,"rmii_rxd0_mfp" ,"ks_out0_mfp" ,"ks_out2_mfp" ,"uart3_rtsb_mfp" ,"uart3_ctsb_mfp" ,"sd0_d0_mfp" ,"sd0_d1_mfp" ,static const char * const uart6_groups[] = {"rmii_txd0_mfp" ,"rmii_txd1_mfp" ,"pcm1_sync_mfp" ,"pcm1_out_mfp" ,static const char * const i2s0_groups[] = {"i2s_d0_mfp" ,"i2s_pcm1_mfp" ,"i2s0_pcm0_mfp" ,static const char * const i2s1_groups[] = {"i2s1_pcm0_mfp" ,"i2s_d1_mfp" ,"spi0_i2s_pcm_mfp" ,"uart0_rx_mfp" ,"uart0_tx_mfp" ,static const char * const pcm1_groups[] = {"i2s_pcm1_mfp" ,"spi0_i2s_pcm_mfp" ,"uart0_rx_mfp" ,"uart0_tx_mfp" ,"pcm1_in_mfp" ,"pcm1_clk_mfp" ,"pcm1_sync_mfp" ,"pcm1_out_mfp" ,static const char * const pcm0_groups[] = {"i2s0_pcm0_mfp" ,"i2s1_pcm0_mfp" ,"spi0_i2c_pcm_mfp" ,"spi0_i2s_pcm_mfp" ,static const char * const ks_groups[] = {"ks_in2_mfp" ,"ks_in1_mfp" ,"ks_in0_mfp" ,"ks_in3_mfp" ,"ks_out0_mfp" ,"ks_out1_mfp" ,"ks_out2_mfp" ,static const char * const jtag_groups[] = {"ks_in2_mfp" ,"ks_in1_mfp" ,"ks_in0_mfp" ,"ks_in3_mfp" ,"ks_out1_mfp" ,"sd0_d0_mfp" ,"sd0_d2_d3_mfp" ,"sd0_cmd_mfp" ,"sd0_clk_mfp" ,static const char * const pwm0_groups[] = {"ks_in2_mfp" ,"ks_in0_mfp" ,"rmii_txen_mfp" ,"sen0_pclk_mfp" ,static const char * const pwm1_groups[] = {"rmii_rxen_mfp" ,"ks_in1_mfp" ,"ks_in3_mfp" ,"sens0_ckout_mfp" ,static const char * const pwm2_groups[] = {"lcd0_d18_mfp" ,"rmii_rxd1_mfp" ,"ks_out0_mfp" ,"ks_out2_mfp" ,static const char * const pwm3_groups[] = {"rmii_rxd0_mfp" ,"ks_out1_mfp" ,"lcd0_d17_mfp" ,static const char * const pwm4_groups[] = {"lcd0_d18_mfp" ,"rmii_crs_dv_mfp" ,"rmii_txd0_mfp" ,"ks_in0_mfp" ,"pcm1_in_mfp" ,"nand_ceb3_mfp" ,static const char * const pwm5_groups[] = {"rmii_txd1_mfp" ,"ks_in1_mfp" ,"pcm1_clk_mfp" ,"nand_ceb2_mfp" ,static const char * const p0_groups[] = {"ks_in2_mfp" ,"ks_in0_mfp" ,static const char * const sd0_groups[] = {"ks_out0_mfp" ,"ks_out1_mfp" ,"ks_out2_mfp" ,"lcd0_d17_mfp" ,"dsi_dp3_mfp" ,"dsi_dp0_mfp" ,"sd0_d0_mfp" ,"sd0_d1_mfp" ,"sd0_d2_d3_mfp" ,"sd1_d0_d3_mfp" ,"sd0_cmd_mfp" ,"sd0_clk_mfp" ,static const char * const sd1_groups[] = {"dsi_dp2_mfp" ,"lcd0_d17_mfp" ,"dsi_dp3_mfp" ,"dsi_dn3_mfp" ,"dsi_dnp1_cp_mfp" ,"dsi_dn2_mfp" ,"sd1_d0_d3_mfp" ,"sd1_cmd_mfp" ,static const char * const sd2_groups[] = {"dnand_data_wr_mfp" ,static const char * const i2c0_groups[] = {"uart0_rx_mfp" ,"uart0_tx_mfp" ,"i2c0_mfp" ,static const char * const i2c1_groups[] = {"i2c0_mfp" ,static const char * const i2c3_groups[] = {"spi0_i2c_pcm_mfp" ,"pcm1_sync_mfp" ,"pcm1_out_mfp" ,static const char * const lvds_groups[] = {"lvds_o_pn_mfp" ,"lvds_ee_pn_mfp" ,"lvds_e_pn_mfp" ,static const char * const ts_groups[] = {"lvds_o_pn_mfp" ,"lvds_ee_pn_mfp" ,static const char * const lcd0_groups[] = {"lcd0_d18_mfp" ,"lcd0_d17_mfp" ,"lvds_o_pn_mfp" ,"dsi_dp3_mfp" ,"dsi_dn3_mfp" ,"lvds_ee_pn_mfp" ,"dsi_dnp1_cp_mfp" ,"lvds_e_pn_mfp" ,static const char * const usb30_groups[] = {"ks_in1_mfp" ,static const char * const clko_25m_groups[] = {"clko_25m_mfp" ,static const char * const mipi_csi_groups[] = {"csi_cn_cp_mfp" ,"csi_dn_dp_mfp" ,static const char * const dsi_groups[] = {"dsi_dn0_mfp" ,"dsi_dp2_mfp" ,"dsi_dp3_mfp" ,"dsi_dn3_mfp" ,"dsi_dp0_mfp" ,"dsi_dnp1_cp_mfp" ,"dsi_dn2_mfp" ,static const char * const nand_groups[] = {"dnand_data_wr_mfp" ,"dnand_acle_ce0_mfp" ,"nand_ceb2_mfp" ,"nand_ceb3_mfp" ,static const char * const spdif_groups[] = {"uart0_tx_mfp" ,static const struct owl_pinmux_func s500_functions[] = {/*[S500_MUX_I2C2] = FUNCTION(i2c2),*/ /*[S500_MUX_SIRQ0] = FUNCTION(sirq0),*/ /*[S500_MUX_SIRQ1] = FUNCTION(sirq1),*/ /*[S500_MUX_SIRQ2] = FUNCTION(sirq2),*/ /* PAD_ST0 */ static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);static PAD_ST_CONF(UART0_RX, 0, 29, 1);static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);static PAD_ST_CONF(DSI_DP0, 0, 16, 1);static PAD_ST_CONF(DSI_DN0, 0, 15, 1);static PAD_ST_CONF(UART0_TX, 0, 14, 1);static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);static PAD_ST_CONF(SD0_CLK, 0, 12, 1);static PAD_ST_CONF(KS_IN0, 0, 11, 1);static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1);static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);static PAD_ST_CONF(KS_OUT0, 0, 6, 1);static PAD_ST_CONF(KS_OUT1, 0, 5, 1);static PAD_ST_CONF(KS_OUT2, 0, 4, 1);/* PAD_ST1 */ static PAD_ST_CONF(DSI_DP2, 1, 31, 1);static PAD_ST_CONF(DSI_DN2, 1, 30, 1);static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);static PAD_ST_CONF(UART3_RX, 1, 25, 1);static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);static PAD_ST_CONF(UART2_RX, 1, 22, 1);static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);static PAD_ST_CONF(ETH_RXER, 1, 18, 1);static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);static PAD_ST_CONF(LVDS_OAP, 1, 12, 1);static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);static PAD_ST_CONF(PCM1_IN, 1, 10, 1);static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);static PAD_ST_CONF(SPI0_SS, 1, 2, 1);static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);/* PAD_PULLCTL0 */ static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1);static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1);static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1);static PAD_PULLCTL_CONF(LCD0_D17, 0, 27, 1);static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1);static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1);static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2);static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2);static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2);static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1);static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1);static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1);static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1);static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1);static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1);static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1);static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1);static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1);/* PAD_PULLCTL1 */ static PAD_PULLCTL_CONF(DSI_CP, 1, 31, 1);static PAD_PULLCTL_CONF(DSI_CN, 1, 30, 1);static PAD_PULLCTL_CONF(DSI_DN2, 1, 28, 1);static PAD_PULLCTL_CONF(DNAND_RDBN, 1, 25, 1);static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1);static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1);static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1);static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1);static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1);static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1);static PAD_PULLCTL_CONF(SD1_CMD, 1, 11, 1);static PAD_PULLCTL_CONF(SD1_D0, 1, 6, 1);static PAD_PULLCTL_CONF(SD1_D1, 1, 5, 1);static PAD_PULLCTL_CONF(SD1_D2, 1, 4, 1);static PAD_PULLCTL_CONF(SD1_D3, 1, 3, 1);static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1);static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1);static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1);/* PAD_PULLCTL2 */ static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 12, 1);static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 11, 1);static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1);static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1);static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);static PAD_PULLCTL_CONF(DNAND_DQSN, 2, 5, 2);static PAD_PULLCTL_CONF(DNAND_DQS, 2, 3, 2);static PAD_PULLCTL_CONF(DNAND_D0, 2, 2, 1);static PAD_PULLCTL_CONF(DNAND_D1, 2, 2, 1);static PAD_PULLCTL_CONF(DNAND_D2, 2, 2, 1);static PAD_PULLCTL_CONF(DNAND_D3, 2, 2, 1);static PAD_PULLCTL_CONF(DNAND_D4, 2, 2, 1);static PAD_PULLCTL_CONF(DNAND_D5, 2, 2, 1);static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1);static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1);/* Pad info table */ static const struct owl_padinfo s500_padinfo[NUM_PADS] = {static const struct owl_gpio_port s500_gpio_ports[] = {enum s500_pinconf_pull {static int s500_pad_pinconf_arg2val(const struct owl_padinfo *info,unsigned int param, u32 *arg)switch (param) {case PIN_CONFIG_BIAS_PULL_DOWN:break ;case PIN_CONFIG_BIAS_PULL_UP:break ;case PIN_CONFIG_INPUT_SCHMITT_ENABLE:break ;default :return -EOPNOTSUPP;return 0;static int s500_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,unsigned int param, u32 *arg)switch (param) {case PIN_CONFIG_BIAS_PULL_DOWN:break ;case PIN_CONFIG_BIAS_PULL_UP:break ;case PIN_CONFIG_INPUT_SCHMITT_ENABLE:break ;default :return -EOPNOTSUPP;return 0;static struct owl_pinctrl_soc_data s500_pinctrl_data = {const struct pinctrl_pin_desc *)s500_pads,static int s500_pinctrl_probe(struct platform_device *pdev)return owl_pinctrl_probe(pdev, &s500_pinctrl_data);static const struct of_device_id s500_pinctrl_of_match[] = {"actions,s500-pinctrl" , },static struct platform_driver s500_pinctrl_driver = {"pinctrl-s500" ,static int __init s500_pinctrl_init(void )return platform_driver_register(&s500_pinctrl_driver);static void __exit s500_pinctrl_exit(void )"Actions Semi Inc." );"Cristian Ciocaltea " );"Actions Semi S500 SoC Pinctrl Driver" );
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