// SPDX-License-Identifier: GPL-2.0-only // Copyright (C) 2013-2017 Broadcom #include <linux/err.h>#include <linux/init.h>#include <linux/io.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/regmap.h>#include <linux/seq_file.h>#include <linux/slab.h>#include <linux/pinctrl/pinconf-generic.h>#include <linux/pinctrl/pinconf.h>#include <linux/pinctrl/pinctrl.h>#include <linux/pinctrl/pinmux.h>#include "../core.h" #include "../pinctrl-utils.h" /* BCM281XX Pin Control Registers Definitions */ /* Function Select bits are the same for all pin control registers */ #define BCM281XX_PIN_REG_F_SEL_MASK 0x0700#define BCM281XX_PIN_REG_F_SEL_SHIFT 8/* Standard pin register */ #define BCM281XX_STD_PIN_REG_DRV_STR_MASK 0x0007#define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT 0#define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008#define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT 3#define BCM281XX_STD_PIN_REG_SLEW_MASK 0x0010#define BCM281XX_STD_PIN_REG_SLEW_SHIFT 4#define BCM281XX_STD_PIN_REG_PULL_UP_MASK 0x0020#define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT 5#define BCM281XX_STD_PIN_REG_PULL_DN_MASK 0x0040#define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT 6#define BCM281XX_STD_PIN_REG_HYST_MASK 0x0080#define BCM281XX_STD_PIN_REG_HYST_SHIFT 7/* I2C pin register */ #define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004#define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT 2#define BCM281XX_I2C_PIN_REG_SLEW_MASK 0x0008#define BCM281XX_I2C_PIN_REG_SLEW_SHIFT 3#define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070#define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT 4/* HDMI pin register */ #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008#define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT 3#define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010#define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4/* BCM21664 access lock registers */ #define BCM21664_WR_ACCESS_OFFSET 0x07F0#define BCM21664_WR_ACCESS_PASSWORD 0xA5A501#define BCM21664_ACCESS_LOCK_OFFSET(lock) (0x0780 + (lock * 4))#define BCM21664_ACCESS_LOCK_COUNT 5/* * bcm281xx_pin_type - types of pin register enum bcm281xx_pin_type {static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD;static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;/* * bcm281xx_pin_function- define pin function struct bcm281xx_pin_function {const char *name;const char * const *groups;const unsigned int ngroups;/* * Device types (used in bcm281xx_pinctrl_desc to differentiate * the two device types from each other) enum bcm281xx_pinctrl_type {/* * bcm281xx_pinctrl_info - description of a pinctrl device supported * by this driver, intended to be used as a provider of OF match data. struct bcm281xx_pinctrl_info {enum bcm281xx_pinctrl_type device_type;/* List of all pins */ const struct pinctrl_pin_desc *pins;unsigned int npins;const struct bcm281xx_pin_function *functions;unsigned int nfunctions;const struct regmap_config *regmap_config;/* * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data * @reg_base - base of pinctrl registers struct bcm281xx_pinctrl_data {struct device *dev;void __iomem *reg_base;struct regmap *regmap;const struct bcm281xx_pinctrl_info *info;/* * Pin number definition. The order here must be the same as defined in the * PADCTRLREG block in the RDB. #define BCM281XX_PIN_ADCSYNC 0#define BCM281XX_PIN_BAT_RM 1#define BCM281XX_PIN_BSC1_SCL 2#define BCM281XX_PIN_BSC1_SDA 3#define BCM281XX_PIN_BSC2_SCL 4#define BCM281XX_PIN_BSC2_SDA 5#define BCM281XX_PIN_CLASSGPWR 6#define BCM281XX_PIN_CLK_CX8 7#define BCM281XX_PIN_CLKOUT_0 8#define BCM281XX_PIN_CLKOUT_1 9#define BCM281XX_PIN_CLKOUT_2 10#define BCM281XX_PIN_CLKOUT_3 11#define BCM281XX_PIN_CLKREQ_IN_0 12#define BCM281XX_PIN_CLKREQ_IN_1 13#define BCM281XX_PIN_CWS_SYS_REQ1 14#define BCM281XX_PIN_CWS_SYS_REQ2 15#define BCM281XX_PIN_CWS_SYS_REQ3 16#define BCM281XX_PIN_DIGMIC1_CLK 17#define BCM281XX_PIN_DIGMIC1_DQ 18#define BCM281XX_PIN_DIGMIC2_CLK 19#define BCM281XX_PIN_DIGMIC2_DQ 20#define BCM281XX_PIN_GPEN13 21#define BCM281XX_PIN_GPEN14 22#define BCM281XX_PIN_GPEN15 23#define BCM281XX_PIN_GPIO00 24#define BCM281XX_PIN_GPIO01 25#define BCM281XX_PIN_GPIO02 26#define BCM281XX_PIN_GPIO03 27#define BCM281XX_PIN_GPIO04 28#define BCM281XX_PIN_GPIO05 29#define BCM281XX_PIN_GPIO06 30#define BCM281XX_PIN_GPIO07 31#define BCM281XX_PIN_GPIO08 32#define BCM281XX_PIN_GPIO09 33#define BCM281XX_PIN_GPIO10 34#define BCM281XX_PIN_GPIO11 35#define BCM281XX_PIN_GPIO12 36#define BCM281XX_PIN_GPIO13 37#define BCM281XX_PIN_GPIO14 38#define BCM281XX_PIN_GPS_PABLANK 39#define BCM281XX_PIN_GPS_TMARK 40#define BCM281XX_PIN_HDMI_SCL 41#define BCM281XX_PIN_HDMI_SDA 42#define BCM281XX_PIN_IC_DM 43#define BCM281XX_PIN_IC_DP 44#define BCM281XX_PIN_KP_COL_IP_0 45#define BCM281XX_PIN_KP_COL_IP_1 46#define BCM281XX_PIN_KP_COL_IP_2 47#define BCM281XX_PIN_KP_COL_IP_3 48#define BCM281XX_PIN_KP_ROW_OP_0 49#define BCM281XX_PIN_KP_ROW_OP_1 50#define BCM281XX_PIN_KP_ROW_OP_2 51#define BCM281XX_PIN_KP_ROW_OP_3 52#define BCM281XX_PIN_LCD_B_0 53#define BCM281XX_PIN_LCD_B_1 54#define BCM281XX_PIN_LCD_B_2 55#define BCM281XX_PIN_LCD_B_3 56#define BCM281XX_PIN_LCD_B_4 57#define BCM281XX_PIN_LCD_B_5 58#define BCM281XX_PIN_LCD_B_6 59#define BCM281XX_PIN_LCD_B_7 60#define BCM281XX_PIN_LCD_G_0 61#define BCM281XX_PIN_LCD_G_1 62#define BCM281XX_PIN_LCD_G_2 63#define BCM281XX_PIN_LCD_G_3 64#define BCM281XX_PIN_LCD_G_4 65#define BCM281XX_PIN_LCD_G_5 66#define BCM281XX_PIN_LCD_G_6 67#define BCM281XX_PIN_LCD_G_7 68#define BCM281XX_PIN_LCD_HSYNC 69#define BCM281XX_PIN_LCD_OE 70#define BCM281XX_PIN_LCD_PCLK 71#define BCM281XX_PIN_LCD_R_0 72#define BCM281XX_PIN_LCD_R_1 73#define BCM281XX_PIN_LCD_R_2 74#define BCM281XX_PIN_LCD_R_3 75#define BCM281XX_PIN_LCD_R_4 76#define BCM281XX_PIN_LCD_R_5 77#define BCM281XX_PIN_LCD_R_6 78#define BCM281XX_PIN_LCD_R_7 79#define BCM281XX_PIN_LCD_VSYNC 80#define BCM281XX_PIN_MDMGPIO0 81#define BCM281XX_PIN_MDMGPIO1 82#define BCM281XX_PIN_MDMGPIO2 83#define BCM281XX_PIN_MDMGPIO3 84#define BCM281XX_PIN_MDMGPIO4 85#define BCM281XX_PIN_MDMGPIO5 86#define BCM281XX_PIN_MDMGPIO6 87#define BCM281XX_PIN_MDMGPIO7 88#define BCM281XX_PIN_MDMGPIO8 89#define BCM281XX_PIN_MPHI_DATA_0 90#define BCM281XX_PIN_MPHI_DATA_1 91#define BCM281XX_PIN_MPHI_DATA_2 92#define BCM281XX_PIN_MPHI_DATA_3 93#define BCM281XX_PIN_MPHI_DATA_4 94#define BCM281XX_PIN_MPHI_DATA_5 95#define BCM281XX_PIN_MPHI_DATA_6 96#define BCM281XX_PIN_MPHI_DATA_7 97#define BCM281XX_PIN_MPHI_DATA_8 98#define BCM281XX_PIN_MPHI_DATA_9 99#define BCM281XX_PIN_MPHI_DATA_10 100#define BCM281XX_PIN_MPHI_DATA_11 101#define BCM281XX_PIN_MPHI_DATA_12 102#define BCM281XX_PIN_MPHI_DATA_13 103#define BCM281XX_PIN_MPHI_DATA_14 104#define BCM281XX_PIN_MPHI_DATA_15 105#define BCM281XX_PIN_MPHI_HA0 106#define BCM281XX_PIN_MPHI_HAT0 107#define BCM281XX_PIN_MPHI_HAT1 108#define BCM281XX_PIN_MPHI_HCE0_N 109#define BCM281XX_PIN_MPHI_HCE1_N 110#define BCM281XX_PIN_MPHI_HRD_N 111#define BCM281XX_PIN_MPHI_HWR_N 112#define BCM281XX_PIN_MPHI_RUN0 113#define BCM281XX_PIN_MPHI_RUN1 114#define BCM281XX_PIN_MTX_SCAN_CLK 115#define BCM281XX_PIN_MTX_SCAN_DATA 116#define BCM281XX_PIN_NAND_AD_0 117#define BCM281XX_PIN_NAND_AD_1 118#define BCM281XX_PIN_NAND_AD_2 119#define BCM281XX_PIN_NAND_AD_3 120#define BCM281XX_PIN_NAND_AD_4 121#define BCM281XX_PIN_NAND_AD_5 122#define BCM281XX_PIN_NAND_AD_6 123#define BCM281XX_PIN_NAND_AD_7 124#define BCM281XX_PIN_NAND_ALE 125#define BCM281XX_PIN_NAND_CEN_0 126#define BCM281XX_PIN_NAND_CEN_1 127#define BCM281XX_PIN_NAND_CLE 128#define BCM281XX_PIN_NAND_OEN 129#define BCM281XX_PIN_NAND_RDY_0 130#define BCM281XX_PIN_NAND_RDY_1 131#define BCM281XX_PIN_NAND_WEN 132#define BCM281XX_PIN_NAND_WP 133#define BCM281XX_PIN_PC1 134#define BCM281XX_PIN_PC2 135#define BCM281XX_PIN_PMU_INT 136#define BCM281XX_PIN_PMU_SCL 137#define BCM281XX_PIN_PMU_SDA 138#define BCM281XX_PIN_RFST2G_MTSLOTEN3G 139#define BCM281XX_PIN_RGMII_0_RX_CTL 140#define BCM281XX_PIN_RGMII_0_RXC 141#define BCM281XX_PIN_RGMII_0_RXD_0 142#define BCM281XX_PIN_RGMII_0_RXD_1 143#define BCM281XX_PIN_RGMII_0_RXD_2 144#define BCM281XX_PIN_RGMII_0_RXD_3 145#define BCM281XX_PIN_RGMII_0_TX_CTL 146#define BCM281XX_PIN_RGMII_0_TXC 147#define BCM281XX_PIN_RGMII_0_TXD_0 148#define BCM281XX_PIN_RGMII_0_TXD_1 149#define BCM281XX_PIN_RGMII_0_TXD_2 150#define BCM281XX_PIN_RGMII_0_TXD_3 151#define BCM281XX_PIN_RGMII_1_RX_CTL 152#define BCM281XX_PIN_RGMII_1_RXC 153#define BCM281XX_PIN_RGMII_1_RXD_0 154#define BCM281XX_PIN_RGMII_1_RXD_1 155#define BCM281XX_PIN_RGMII_1_RXD_2 156#define BCM281XX_PIN_RGMII_1_RXD_3 157#define BCM281XX_PIN_RGMII_1_TX_CTL 158#define BCM281XX_PIN_RGMII_1_TXC 159#define BCM281XX_PIN_RGMII_1_TXD_0 160#define BCM281XX_PIN_RGMII_1_TXD_1 161#define BCM281XX_PIN_RGMII_1_TXD_2 162#define BCM281XX_PIN_RGMII_1_TXD_3 163#define BCM281XX_PIN_RGMII_GPIO_0 164#define BCM281XX_PIN_RGMII_GPIO_1 165#define BCM281XX_PIN_RGMII_GPIO_2 166#define BCM281XX_PIN_RGMII_GPIO_3 167#define BCM281XX_PIN_RTXDATA2G_TXDATA3G1 168#define BCM281XX_PIN_RTXEN2G_TXDATA3G2 169#define BCM281XX_PIN_RXDATA3G0 170#define BCM281XX_PIN_RXDATA3G1 171#define BCM281XX_PIN_RXDATA3G2 172#define BCM281XX_PIN_SDIO1_CLK 173#define BCM281XX_PIN_SDIO1_CMD 174#define BCM281XX_PIN_SDIO1_DATA_0 175#define BCM281XX_PIN_SDIO1_DATA_1 176#define BCM281XX_PIN_SDIO1_DATA_2 177#define BCM281XX_PIN_SDIO1_DATA_3 178#define BCM281XX_PIN_SDIO4_CLK 179#define BCM281XX_PIN_SDIO4_CMD 180#define BCM281XX_PIN_SDIO4_DATA_0 181#define BCM281XX_PIN_SDIO4_DATA_1 182#define BCM281XX_PIN_SDIO4_DATA_2 183#define BCM281XX_PIN_SDIO4_DATA_3 184#define BCM281XX_PIN_SIM_CLK 185#define BCM281XX_PIN_SIM_DATA 186#define BCM281XX_PIN_SIM_DET 187#define BCM281XX_PIN_SIM_RESETN 188#define BCM281XX_PIN_SIM2_CLK 189#define BCM281XX_PIN_SIM2_DATA 190#define BCM281XX_PIN_SIM2_DET 191#define BCM281XX_PIN_SIM2_RESETN 192#define BCM281XX_PIN_SRI_C 193#define BCM281XX_PIN_SRI_D 194#define BCM281XX_PIN_SRI_E 195#define BCM281XX_PIN_SSP_EXTCLK 196#define BCM281XX_PIN_SSP0_CLK 197#define BCM281XX_PIN_SSP0_FS 198#define BCM281XX_PIN_SSP0_RXD 199#define BCM281XX_PIN_SSP0_TXD 200#define BCM281XX_PIN_SSP2_CLK 201#define BCM281XX_PIN_SSP2_FS_0 202#define BCM281XX_PIN_SSP2_FS_1 203#define BCM281XX_PIN_SSP2_FS_2 204#define BCM281XX_PIN_SSP2_FS_3 205#define BCM281XX_PIN_SSP2_RXD_0 206#define BCM281XX_PIN_SSP2_RXD_1 207#define BCM281XX_PIN_SSP2_TXD_0 208#define BCM281XX_PIN_SSP2_TXD_1 209#define BCM281XX_PIN_SSP3_CLK 210#define BCM281XX_PIN_SSP3_FS 211#define BCM281XX_PIN_SSP3_RXD 212#define BCM281XX_PIN_SSP3_TXD 213#define BCM281XX_PIN_SSP4_CLK 214#define BCM281XX_PIN_SSP4_FS 215#define BCM281XX_PIN_SSP4_RXD 216#define BCM281XX_PIN_SSP4_TXD 217#define BCM281XX_PIN_SSP5_CLK 218#define BCM281XX_PIN_SSP5_FS 219#define BCM281XX_PIN_SSP5_RXD 220#define BCM281XX_PIN_SSP5_TXD 221#define BCM281XX_PIN_SSP6_CLK 222#define BCM281XX_PIN_SSP6_FS 223#define BCM281XX_PIN_SSP6_RXD 224#define BCM281XX_PIN_SSP6_TXD 225#define BCM281XX_PIN_STAT_1 226#define BCM281XX_PIN_STAT_2 227#define BCM281XX_PIN_SYSCLKEN 228#define BCM281XX_PIN_TRACECLK 229#define BCM281XX_PIN_TRACEDT00 230#define BCM281XX_PIN_TRACEDT01 231#define BCM281XX_PIN_TRACEDT02 232#define BCM281XX_PIN_TRACEDT03 233#define BCM281XX_PIN_TRACEDT04 234#define BCM281XX_PIN_TRACEDT05 235#define BCM281XX_PIN_TRACEDT06 236#define BCM281XX_PIN_TRACEDT07 237#define BCM281XX_PIN_TRACEDT08 238#define BCM281XX_PIN_TRACEDT09 239#define BCM281XX_PIN_TRACEDT10 240#define BCM281XX_PIN_TRACEDT11 241#define BCM281XX_PIN_TRACEDT12 242#define BCM281XX_PIN_TRACEDT13 243#define BCM281XX_PIN_TRACEDT14 244#define BCM281XX_PIN_TRACEDT15 245#define BCM281XX_PIN_TXDATA3G0 246#define BCM281XX_PIN_TXPWRIND 247#define BCM281XX_PIN_UARTB1_UCTS 248#define BCM281XX_PIN_UARTB1_URTS 249#define BCM281XX_PIN_UARTB1_URXD 250#define BCM281XX_PIN_UARTB1_UTXD 251#define BCM281XX_PIN_UARTB2_URXD 252#define BCM281XX_PIN_UARTB2_UTXD 253#define BCM281XX_PIN_UARTB3_UCTS 254#define BCM281XX_PIN_UARTB3_URTS 255#define BCM281XX_PIN_UARTB3_URXD 256#define BCM281XX_PIN_UARTB3_UTXD 257#define BCM281XX_PIN_UARTB4_UCTS 258#define BCM281XX_PIN_UARTB4_URTS 259#define BCM281XX_PIN_UARTB4_URXD 260#define BCM281XX_PIN_UARTB4_UTXD 261#define BCM281XX_PIN_VC_CAM1_SCL 262#define BCM281XX_PIN_VC_CAM1_SDA 263#define BCM281XX_PIN_VC_CAM2_SCL 264#define BCM281XX_PIN_VC_CAM2_SDA 265#define BCM281XX_PIN_VC_CAM3_SCL 266#define BCM281XX_PIN_VC_CAM3_SDA 267#define BCM281XX_PIN_DESC(a, b, c) \## _pin }/* * Pin description definition. The order here must be the same as defined in * the PADCTRLREG block in the RDB, since the pin number is used as an index * into this array. static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = {"adcsync" , std),"bat_rm" , std),"bsc1_scl" , i2c),"bsc1_sda" , i2c),"bsc2_scl" , i2c),"bsc2_sda" , i2c),"classgpwr" , std),"clk_cx8" , std),"clkout_0" , std),"clkout_1" , std),"clkout_2" , std),"clkout_3" , std),"clkreq_in_0" , std),"clkreq_in_1" , std),"cws_sys_req1" , std),"cws_sys_req2" , std),"cws_sys_req3" , std),"digmic1_clk" , std),"digmic1_dq" , std),"digmic2_clk" , std),"digmic2_dq" , std),"gpen13" , std),"gpen14" , std),"gpen15" , std),"gpio00" , std),"gpio01" , std),"gpio02" , std),"gpio03" , std),"gpio04" , std),"gpio05" , std),"gpio06" , std),"gpio07" , std),"gpio08" , std),"gpio09" , std),"gpio10" , std),"gpio11" , std),"gpio12" , std),"gpio13" , std),"gpio14" , std),"gps_pablank" , std),"gps_tmark" , std),"hdmi_scl" , hdmi),"hdmi_sda" , hdmi),"ic_dm" , std),"ic_dp" , std),"kp_col_ip_0" , std),"kp_col_ip_1" , std),"kp_col_ip_2" , std),"kp_col_ip_3" , std),"kp_row_op_0" , std),"kp_row_op_1" , std),"kp_row_op_2" , std),"kp_row_op_3" , std),"lcd_b_0" , std),"lcd_b_1" , std),"lcd_b_2" , std),"lcd_b_3" , std),"lcd_b_4" , std),"lcd_b_5" , std),"lcd_b_6" , std),"lcd_b_7" , std),"lcd_g_0" , std),"lcd_g_1" , std),"lcd_g_2" , std),"lcd_g_3" , std),"lcd_g_4" , std),"lcd_g_5" , std),"lcd_g_6" , std),"lcd_g_7" , std),"lcd_hsync" , std),"lcd_oe" , std),"lcd_pclk" , std),"lcd_r_0" , std),"lcd_r_1" , std),"lcd_r_2" , std),"lcd_r_3" , std),"lcd_r_4" , std),"lcd_r_5" , std),"lcd_r_6" , std),"lcd_r_7" , std),"lcd_vsync" , std),"mdmgpio0" , std),"mdmgpio1" , std),"mdmgpio2" , std),"mdmgpio3" , std),"mdmgpio4" , std),"mdmgpio5" , std),"mdmgpio6" , std),"mdmgpio7" , std),"mdmgpio8" , std),"mphi_data_0" , std),"mphi_data_1" , std),"mphi_data_2" , std),"mphi_data_3" , std),"mphi_data_4" , std),"mphi_data_5" , std),"mphi_data_6" , std),"mphi_data_7" , std),"mphi_data_8" , std),"mphi_data_9" , std),"mphi_data_10" , std),"mphi_data_11" , std),"mphi_data_12" , std),"mphi_data_13" , std),"mphi_data_14" , std),"mphi_data_15" , std),"mphi_ha0" , std),"mphi_hat0" , std),"mphi_hat1" , std),"mphi_hce0_n" , std),"mphi_hce1_n" , std),"mphi_hrd_n" , std),"mphi_hwr_n" , std),"mphi_run0" , std),"mphi_run1" , std),"mtx_scan_clk" , std),"mtx_scan_data" , std),"nand_ad_0" , std),"nand_ad_1" , std),"nand_ad_2" , std),"nand_ad_3" , std),"nand_ad_4" , std),"nand_ad_5" , std),"nand_ad_6" , std),"nand_ad_7" , std),"nand_ale" , std),"nand_cen_0" , std),"nand_cen_1" , std),"nand_cle" , std),"nand_oen" , std),"nand_rdy_0" , std),"nand_rdy_1" , std),"nand_wen" , std),"nand_wp" , std),"pc1" , std),"pc2" , std),"pmu_int" , std),"pmu_scl" , i2c),"pmu_sda" , i2c),"rfst2g_mtsloten3g" ,"rgmii_0_rx_ctl" , std),"rgmii_0_rxc" , std),"rgmii_0_rxd_0" , std),"rgmii_0_rxd_1" , std),"rgmii_0_rxd_2" , std),"rgmii_0_rxd_3" , std),"rgmii_0_tx_ctl" , std),"rgmii_0_txc" , std),"rgmii_0_txd_0" , std),"rgmii_0_txd_1" , std),"rgmii_0_txd_2" , std),"rgmii_0_txd_3" , std),"rgmii_1_rx_ctl" , std),"rgmii_1_rxc" , std),"rgmii_1_rxd_0" , std),"rgmii_1_rxd_1" , std),"rgmii_1_rxd_2" , std),"rgmii_1_rxd_3" , std),"rgmii_1_tx_ctl" , std),"rgmii_1_txc" , std),"rgmii_1_txd_0" , std),"rgmii_1_txd_1" , std),"rgmii_1_txd_2" , std),"rgmii_1_txd_3" , std),"rgmii_gpio_0" , std),"rgmii_gpio_1" , std),"rgmii_gpio_2" , std),"rgmii_gpio_3" , std),"rtxdata2g_txdata3g1" , std),"rtxen2g_txdata3g2" ,"rxdata3g0" , std),"rxdata3g1" , std),"rxdata3g2" , std),"sdio1_clk" , std),"sdio1_cmd" , std),"sdio1_data_0" , std),"sdio1_data_1" , std),"sdio1_data_2" , std),"sdio1_data_3" , std),"sdio4_clk" , std),"sdio4_cmd" , std),"sdio4_data_0" , std),"sdio4_data_1" , std),"sdio4_data_2" , std),"sdio4_data_3" , std),"sim_clk" , std),"sim_data" , std),"sim_det" , std),"sim_resetn" , std),"sim2_clk" , std),"sim2_data" , std),"sim2_det" , std),"sim2_resetn" , std),"sri_c" , std),"sri_d" , std),"sri_e" , std),"ssp_extclk" , std),"ssp0_clk" , std),"ssp0_fs" , std),"ssp0_rxd" , std),"ssp0_txd" , std),"ssp2_clk" , std),"ssp2_fs_0" , std),"ssp2_fs_1" , std),"ssp2_fs_2" , std),"ssp2_fs_3" , std),"ssp2_rxd_0" , std),"ssp2_rxd_1" , std),"ssp2_txd_0" , std),"ssp2_txd_1" , std),"ssp3_clk" , std),"ssp3_fs" , std),"ssp3_rxd" , std),"ssp3_txd" , std),"ssp4_clk" , std),"ssp4_fs" , std),"ssp4_rxd" , std),"ssp4_txd" , std),"ssp5_clk" , std),"ssp5_fs" , std),"ssp5_rxd" , std),"ssp5_txd" , std),"ssp6_clk" , std),"ssp6_fs" , std),"ssp6_rxd" , std),"ssp6_txd" , std),"stat_1" , std),"stat_2" , std),"sysclken" , std),"traceclk" , std),"tracedt00" , std),"tracedt01" , std),"tracedt02" , std),"tracedt03" , std),"tracedt04" , std),"tracedt05" , std),"tracedt06" , std),"tracedt07" , std),"tracedt08" , std),"tracedt09" , std),"tracedt10" , std),"tracedt11" , std),"tracedt12" , std),"tracedt13" , std),"tracedt14" , std),"tracedt15" , std),"txdata3g0" , std),"txpwrind" , std),"uartb1_ucts" , std),"uartb1_urts" , std),"uartb1_urxd" , std),"uartb1_utxd" , std),"uartb2_urxd" , std),"uartb2_utxd" , std),"uartb3_ucts" , std),"uartb3_urts" , std),"uartb3_urxd" , std),"uartb3_utxd" , std),"uartb4_ucts" , std),"uartb4_urts" , std),"uartb4_urxd" , std),"uartb4_utxd" , std),"vc_cam1_scl" , i2c),"vc_cam1_sda" , i2c),"vc_cam2_scl" , i2c),"vc_cam2_sda" , i2c),"vc_cam3_scl" , i2c),"vc_cam3_sda" , i2c),static const char * const bcm281xx_alt_groups[] = {"adcsync" ,"bat_rm" ,"bsc1_scl" ,"bsc1_sda" ,"bsc2_scl" ,"bsc2_sda" ,"classgpwr" ,"clk_cx8" ,"clkout_0" ,"clkout_1" ,"clkout_2" ,"clkout_3" ,"clkreq_in_0" ,"clkreq_in_1" ,"cws_sys_req1" ,"cws_sys_req2" ,"cws_sys_req3" ,"digmic1_clk" ,"digmic1_dq" ,"digmic2_clk" ,"digmic2_dq" ,"gpen13" ,"gpen14" ,"gpen15" ,"gpio00" ,"gpio01" ,"gpio02" ,"gpio03" ,"gpio04" ,"gpio05" ,"gpio06" ,"gpio07" ,"gpio08" ,"gpio09" ,"gpio10" ,"gpio11" ,"gpio12" ,"gpio13" ,"gpio14" ,"gps_pablank" ,"gps_tmark" ,"hdmi_scl" ,"hdmi_sda" ,"ic_dm" ,"ic_dp" ,"kp_col_ip_0" ,"kp_col_ip_1" ,"kp_col_ip_2" ,"kp_col_ip_3" ,"kp_row_op_0" ,"kp_row_op_1" ,"kp_row_op_2" ,"kp_row_op_3" ,"lcd_b_0" ,"lcd_b_1" ,"lcd_b_2" ,"lcd_b_3" ,"lcd_b_4" ,"lcd_b_5" ,"lcd_b_6" ,"lcd_b_7" ,"lcd_g_0" ,"lcd_g_1" ,"lcd_g_2" ,"lcd_g_3" ,"lcd_g_4" ,"lcd_g_5" ,"lcd_g_6" ,"lcd_g_7" ,"lcd_hsync" ,"lcd_oe" ,"lcd_pclk" ,"lcd_r_0" ,"lcd_r_1" ,"lcd_r_2" ,"lcd_r_3" ,"lcd_r_4" ,"lcd_r_5" ,"lcd_r_6" ,"lcd_r_7" ,"lcd_vsync" ,"mdmgpio0" ,"mdmgpio1" ,"mdmgpio2" ,"mdmgpio3" ,"mdmgpio4" ,"mdmgpio5" ,"mdmgpio6" ,"mdmgpio7" ,"mdmgpio8" ,"mphi_data_0" ,"mphi_data_1" ,"mphi_data_2" ,"mphi_data_3" ,"mphi_data_4" ,"mphi_data_5" ,"mphi_data_6" ,"mphi_data_7" ,"mphi_data_8" ,"mphi_data_9" ,"mphi_data_10" ,"mphi_data_11" ,"mphi_data_12" ,"mphi_data_13" ,"mphi_data_14" ,"mphi_data_15" ,"mphi_ha0" ,"mphi_hat0" ,"mphi_hat1" ,"mphi_hce0_n" ,"mphi_hce1_n" ,"mphi_hrd_n" ,"mphi_hwr_n" ,"mphi_run0" ,"mphi_run1" ,"mtx_scan_clk" ,"mtx_scan_data" ,"nand_ad_0" ,"nand_ad_1" ,"nand_ad_2" ,"nand_ad_3" ,"nand_ad_4" ,"nand_ad_5" ,"nand_ad_6" ,"nand_ad_7" ,"nand_ale" ,"nand_cen_0" ,"nand_cen_1" ,"nand_cle" ,"nand_oen" ,"nand_rdy_0" ,"nand_rdy_1" ,"nand_wen" ,"nand_wp" ,"pc1" ,"pc2" ,"pmu_int" ,"pmu_scl" ,"pmu_sda" ,"rfst2g_mtsloten3g" ,"rgmii_0_rx_ctl" ,"rgmii_0_rxc" ,"rgmii_0_rxd_0" ,"rgmii_0_rxd_1" ,"rgmii_0_rxd_2" ,"rgmii_0_rxd_3" ,"rgmii_0_tx_ctl" ,"rgmii_0_txc" ,"rgmii_0_txd_0" ,"rgmii_0_txd_1" ,"rgmii_0_txd_2" ,"rgmii_0_txd_3" ,"rgmii_1_rx_ctl" ,"rgmii_1_rxc" ,"rgmii_1_rxd_0" ,"rgmii_1_rxd_1" ,"rgmii_1_rxd_2" ,"rgmii_1_rxd_3" ,"rgmii_1_tx_ctl" ,"rgmii_1_txc" ,"rgmii_1_txd_0" ,"rgmii_1_txd_1" ,"rgmii_1_txd_2" ,"rgmii_1_txd_3" ,"rgmii_gpio_0" ,"rgmii_gpio_1" ,"rgmii_gpio_2" ,"rgmii_gpio_3" ,"rtxdata2g_txdata3g1" ,"rtxen2g_txdata3g2" ,"rxdata3g0" ,"rxdata3g1" ,"rxdata3g2" ,"sdio1_clk" ,"sdio1_cmd" ,"sdio1_data_0" ,"sdio1_data_1" ,"sdio1_data_2" ,"sdio1_data_3" ,"sdio4_clk" ,"sdio4_cmd" ,"sdio4_data_0" ,"sdio4_data_1" ,"sdio4_data_2" ,"sdio4_data_3" ,"sim_clk" ,"sim_data" ,"sim_det" ,"sim_resetn" ,"sim2_clk" ,"sim2_data" ,"sim2_det" ,"sim2_resetn" ,"sri_c" ,"sri_d" ,"sri_e" ,"ssp_extclk" ,"ssp0_clk" ,"ssp0_fs" ,"ssp0_rxd" ,"ssp0_txd" ,"ssp2_clk" ,"ssp2_fs_0" ,"ssp2_fs_1" ,"ssp2_fs_2" ,"ssp2_fs_3" ,"ssp2_rxd_0" ,"ssp2_rxd_1" ,"ssp2_txd_0" ,"ssp2_txd_1" ,"ssp3_clk" ,"ssp3_fs" ,"ssp3_rxd" ,"ssp3_txd" ,"ssp4_clk" ,"ssp4_fs" ,"ssp4_rxd" ,"ssp4_txd" ,"ssp5_clk" ,"ssp5_fs" ,"ssp5_rxd" ,"ssp5_txd" ,"ssp6_clk" ,"ssp6_fs" ,"ssp6_rxd" ,"ssp6_txd" ,"stat_1" ,"stat_2" ,"sysclken" ,"traceclk" ,"tracedt00" ,"tracedt01" ,"tracedt02" ,"tracedt03" ,"tracedt04" ,"tracedt05" ,"tracedt06" ,"tracedt07" ,"tracedt08" ,"tracedt09" ,"tracedt10" ,"tracedt11" ,"tracedt12" ,"tracedt13" ,"tracedt14" ,"tracedt15" ,"txdata3g0" ,"txpwrind" ,"uartb1_ucts" ,"uartb1_urts" ,"uartb1_urxd" ,"uartb1_utxd" ,"uartb2_urxd" ,"uartb2_utxd" ,"uartb3_ucts" ,"uartb3_urts" ,"uartb3_urxd" ,"uartb3_utxd" ,"uartb4_ucts" ,"uartb4_urts" ,"uartb4_urxd" ,"uartb4_utxd" ,"vc_cam1_scl" ,"vc_cam1_sda" ,"vc_cam2_scl" ,"vc_cam2_sda" ,"vc_cam3_scl" ,"vc_cam3_sda" ,/* Every pin can implement all ALT1-ALT4 functions */ #define BCM281XX_PIN_FUNCTION(fcn_name) \#fcn_name , \static const struct bcm281xx_pin_function bcm281xx_functions[] = {static const struct regmap_config bcm281xx_pinctrl_regmap_config = {static const struct bcm281xx_pinctrl_info bcm281xx_pinctrl = {/* BCM21664 data */ #define BCM21664_PIN_ADCSYN 0#define BCM21664_PIN_BATRM 1#define BCM21664_PIN_BSC1CLK 2#define BCM21664_PIN_BSC1DAT 3#define BCM21664_PIN_CAMCS0 4#define BCM21664_PIN_CAMCS1 5#define BCM21664_PIN_CLK32K 6#define BCM21664_PIN_CLK_CX8 7#define BCM21664_PIN_DCLK1 8#define BCM21664_PIN_DCLK4 9#define BCM21664_PIN_DCLKREQ1 10#define BCM21664_PIN_DCLKREQ4 11#define BCM21664_PIN_DMIC0CLK 12#define BCM21664_PIN_DMIC0DQ 13#define BCM21664_PIN_DSI0TE 14#define BCM21664_PIN_GPIO00 15#define BCM21664_PIN_GPIO01 16#define BCM21664_PIN_GPIO02 17#define BCM21664_PIN_GPIO03 18#define BCM21664_PIN_GPIO04 19#define BCM21664_PIN_GPIO05 20#define BCM21664_PIN_GPIO06 21#define BCM21664_PIN_GPIO07 22#define BCM21664_PIN_GPIO08 23#define BCM21664_PIN_GPIO09 24#define BCM21664_PIN_GPIO10 25#define BCM21664_PIN_GPIO11 26#define BCM21664_PIN_GPIO12 27#define BCM21664_PIN_GPIO13 28#define BCM21664_PIN_GPIO14 29#define BCM21664_PIN_GPIO15 30#define BCM21664_PIN_GPIO16 31#define BCM21664_PIN_GPIO17 32#define BCM21664_PIN_GPIO18 33#define BCM21664_PIN_GPIO19 34#define BCM21664_PIN_GPIO20 35#define BCM21664_PIN_GPIO21 36#define BCM21664_PIN_GPIO22 37#define BCM21664_PIN_GPIO23 38#define BCM21664_PIN_GPIO24 39#define BCM21664_PIN_GPIO25 40#define BCM21664_PIN_GPIO26 41#define BCM21664_PIN_GPIO27 42#define BCM21664_PIN_GPIO28 43#define BCM21664_PIN_GPIO32 44#define BCM21664_PIN_GPIO33 45#define BCM21664_PIN_GPIO34 46#define BCM21664_PIN_GPS_CALREQ 47#define BCM21664_PIN_GPS_HOSTREQ 48#define BCM21664_PIN_GPS_PABLANK 49#define BCM21664_PIN_GPS_TMARK 50#define BCM21664_PIN_ICUSBDM 51#define BCM21664_PIN_ICUSBDP 52#define BCM21664_PIN_LCDCS0 53#define BCM21664_PIN_LCDRES 54#define BCM21664_PIN_LCDSCL 55#define BCM21664_PIN_LCDSDA 56#define BCM21664_PIN_LCDTE 57#define BCM21664_PIN_MDMGPIO00 58#define BCM21664_PIN_MDMGPIO01 59#define BCM21664_PIN_MDMGPIO02 60#define BCM21664_PIN_MDMGPIO03 61#define BCM21664_PIN_MDMGPIO04 62#define BCM21664_PIN_MDMGPIO05 63#define BCM21664_PIN_MDMGPIO06 64#define BCM21664_PIN_MDMGPIO07 65#define BCM21664_PIN_MDMGPIO08 66#define BCM21664_PIN_MMC0CK 67#define BCM21664_PIN_MMC0CMD 68#define BCM21664_PIN_MMC0DAT0 69#define BCM21664_PIN_MMC0DAT1 70#define BCM21664_PIN_MMC0DAT2 71#define BCM21664_PIN_MMC0DAT3 72#define BCM21664_PIN_MMC0DAT4 73#define BCM21664_PIN_MMC0DAT5 74#define BCM21664_PIN_MMC0DAT6 75#define BCM21664_PIN_MMC0DAT7 76#define BCM21664_PIN_MMC0RST 77#define BCM21664_PIN_MMC1CK 78#define BCM21664_PIN_MMC1CMD 79#define BCM21664_PIN_MMC1DAT0 80#define BCM21664_PIN_MMC1DAT1 81#define BCM21664_PIN_MMC1DAT2 82#define BCM21664_PIN_MMC1DAT3 83#define BCM21664_PIN_MMC1DAT4 84#define BCM21664_PIN_MMC1DAT5 85#define BCM21664_PIN_MMC1DAT6 86#define BCM21664_PIN_MMC1DAT7 87#define BCM21664_PIN_MMC1RST 88#define BCM21664_PIN_PC1 89#define BCM21664_PIN_PC2 90#define BCM21664_PIN_PMBSCCLK 91#define BCM21664_PIN_PMBSCDAT 92#define BCM21664_PIN_PMUINT 93#define BCM21664_PIN_RESETN 94#define BCM21664_PIN_RFST2G_MTSLOTEN3G 95#define BCM21664_PIN_RTXDATA2G_TXDATA3G1 96#define BCM21664_PIN_RTXEN2G_TXDATA3G2 97#define BCM21664_PIN_RXDATA3G0 98#define BCM21664_PIN_RXDATA3G1 99#define BCM21664_PIN_RXDATA3G2 100#define BCM21664_PIN_SDCK 101#define BCM21664_PIN_SDCMD 102#define BCM21664_PIN_SDDAT0 103#define BCM21664_PIN_SDDAT1 104#define BCM21664_PIN_SDDAT2 105#define BCM21664_PIN_SDDAT3 106#define BCM21664_PIN_SIMCLK 107#define BCM21664_PIN_SIMDAT 108#define BCM21664_PIN_SIMDET 109#define BCM21664_PIN_SIMRST 110#define BCM21664_PIN_GPIO93 111#define BCM21664_PIN_GPIO94 112#define BCM21664_PIN_SPI0CLK 113#define BCM21664_PIN_SPI0FSS 114#define BCM21664_PIN_SPI0RXD 115#define BCM21664_PIN_SPI0TXD 116#define BCM21664_PIN_SRI_C 117#define BCM21664_PIN_SRI_D 118#define BCM21664_PIN_SRI_E 119#define BCM21664_PIN_SSPCK 120#define BCM21664_PIN_SSPDI 121#define BCM21664_PIN_SSPDO 122#define BCM21664_PIN_SSPSYN 123#define BCM21664_PIN_STAT1 124#define BCM21664_PIN_STAT2 125#define BCM21664_PIN_SWCLKTCK 126#define BCM21664_PIN_SWDIOTMS 127#define BCM21664_PIN_SYSCLKEN 128#define BCM21664_PIN_TDI 129#define BCM21664_PIN_TDO 130#define BCM21664_PIN_TESTMODE 131#define BCM21664_PIN_TRACECLK 132#define BCM21664_PIN_TRACEDT00 133#define BCM21664_PIN_TRACEDT01 134#define BCM21664_PIN_TRACEDT02 135#define BCM21664_PIN_TRACEDT03 136#define BCM21664_PIN_TRACEDT04 137#define BCM21664_PIN_TRACEDT05 138#define BCM21664_PIN_TRACEDT06 139#define BCM21664_PIN_TRACEDT07 140#define BCM21664_PIN_TRSTB 141#define BCM21664_PIN_TXDATA3G0 142#define BCM21664_PIN_UBCTSN 143#define BCM21664_PIN_UBRTSN 144#define BCM21664_PIN_UBRX 145#define BCM21664_PIN_UBTX 146#define BCM21664_PIN_TRACEDT08 147#define BCM21664_PIN_TRACEDT09 148#define BCM21664_PIN_TRACEDT10 149#define BCM21664_PIN_TRACEDT11 150#define BCM21664_PIN_TRACEDT12 151#define BCM21664_PIN_TRACEDT13 152#define BCM21664_PIN_TRACEDT14 153#define BCM21664_PIN_TRACEDT15 154static const struct pinctrl_pin_desc bcm21664_pinctrl_pins[] = {"adcsyn" , std),"batrm" , std),"bsc1clk" , i2c),"bsc1dat" , i2c),"camcs0" , std),"camcs1" , std),"clk32k" , std),"clk_cx8" , std),"dclk1" , std),"dclk4" , std),"dclkreq1" , std),"dclkreq4" , std),"dmic0clk" , std),"dmic0dq" , std),"dsi0te" , std),"gpio00" , std),"gpio01" , std),"gpio02" , std),"gpio03" , std),"gpio04" , std),"gpio05" , std),"gpio06" , std),"gpio07" , std),"gpio08" , std),"gpio09" , std),"gpio10" , std),"gpio11" , std),"gpio12" , std),"gpio13" , std),"gpio14" , std),"gpio15" , std),"gpio16" , i2c),"gpio17" , i2c),"gpio18" , std),"gpio19" , std),"gpio20" , std),"gpio21" , std),"gpio22" , std),"gpio23" , std),"gpio24" , std),"gpio25" , std),"gpio26" , std),"gpio27" , std),"gpio28" , std),"gpio32" , std),"gpio33" , std),"gpio34" , std),"gps_calreq" , std),"gps_hostreq" , std),"gps_pablank" , std),"gps_tmark" , std),"icusbdm" , std),"icusbdp" , std),"lcdcs0" , std),"lcdres" , std),"lcdscl" , std),"lcdsda" , std),"lcdte" , std),"mdmgpio00" , std),"mdmgpio01" , std),"mdmgpio02" , std),"mdmgpio03" , std),"mdmgpio04" , std),"mdmgpio05" , std),"mdmgpio06" , std),"mdmgpio07" , std),"mdmgpio08" , std),"mmc0ck" , std),"mmc0cmd" , std),"mmc0dat0" , std),"mmc0dat1" , std),"mmc0dat2" , std),"mmc0dat3" , std),"mmc0dat4" , std),"mmc0dat5" , std),"mmc0dat6" , std),"mmc0dat7" , std),"mmc0rst" , std),"mmc1ck" , std),"mmc1cmd" , std),"mmc1dat0" , std),"mmc1dat1" , std),"mmc1dat2" , std),"mmc1dat3" , std),"mmc1dat4" , std),"mmc1dat5" , std),"mmc1dat6" , std),"mmc1dat7" , std),"mmc1rst" , std),"pc1" , std),"pc2" , std),"pmbscclk" , i2c),"pmbscdat" , i2c),"pmuint" , std),"resetn" , std),"rfst2g_mtsloten3g" , std),"rtxdata2g_txdata3g1" , std),"rtxen2g_txdata3g2" , std),"rxdata3g0" , std),"rxdata3g1" , std),"rxdata3g2" , std),"sdck" , std),"sdcmd" , std),"sddat0" , std),"sddat1" , std),"sddat2" , std),"sddat3" , std),"simclk" , std),"simdat" , std),"simdet" , std),"simrst" , std),"gpio93" , std),"gpio94" , std),"spi0clk" , std),"spi0fss" , std),"spi0rxd" , std),"spi0txd" , std),"sri_c" , std),"sri_d" , std),"sri_e" , std),"sspck" , std),"sspdi" , std),"sspdo" , std),"sspsyn" , std),"stat1" , std),"stat2" , std),"swclktck" , std),"swdiotms" , std),"sysclken" , std),"tdi" , std),"tdo" , std),"testmode" , std),"traceclk" , std),"tracedt00" , std),"tracedt01" , std),"tracedt02" , std),"tracedt03" , std),"tracedt04" , std),"tracedt05" , std),"tracedt06" , std),"tracedt07" , std),"trstb" , std),"txdata3g0" , std),"ubctsn" , std),"ubrtsn" , std),"ubrx" , std),"ubtx" , std),"tracedt08" , std),"tracedt09" , std),"tracedt10" , std),"tracedt11" , std),"tracedt12" , std),"tracedt13" , std),"tracedt14" , std),"tracedt15" , std),static const char * const bcm21664_alt_groups[] = {"adcsyn" ,"batrm" ,"bsc1clk" ,"bsc1dat" ,"camcs0" ,"camcs1" ,"clk32k" ,"clk_cx8" ,"dclk1" ,"dclk4" ,"dclkreq1" ,"dclkreq4" ,"dmic0clk" ,"dmic0dq" ,"dsi0te" ,"gpio00" ,"gpio01" ,"gpio02" ,"gpio03" ,"gpio04" ,"gpio05" ,"gpio06" ,"gpio07" ,"gpio08" ,"gpio09" ,"gpio10" ,"gpio11" ,"gpio12" ,"gpio13" ,"gpio14" ,"gpio15" ,"gpio16" ,"gpio17" ,"gpio18" ,"gpio19" ,"gpio20" ,"gpio21" ,"gpio22" ,"gpio23" ,"gpio24" ,"gpio25" ,"gpio26" ,"gpio27" ,"gpio28" ,"gpio32" ,"gpio33" ,"gpio34" ,"gps_calreq" ,"gps_hostreq" ,"gps_pablank" ,"gps_tmark" ,"icusbdm" ,"icusbdp" ,"lcdcs0" ,"lcdres" ,"lcdscl" ,"lcdsda" ,"lcdte" ,"mdmgpio00" ,"mdmgpio01" ,"mdmgpio02" ,"mdmgpio03" ,"mdmgpio04" ,"mdmgpio05" ,"mdmgpio06" ,"mdmgpio07" ,"mdmgpio08" ,"mmc0ck" ,"mmc0cmd" ,"mmc0dat0" ,"mmc0dat1" ,"mmc0dat2" ,"mmc0dat3" ,"mmc0dat4" ,"mmc0dat5" ,"mmc0dat6" ,"mmc0dat7" ,"mmc0rst" ,"mmc1ck" ,"mmc1cmd" ,"mmc1dat0" ,"mmc1dat1" ,"mmc1dat2" ,"mmc1dat3" ,"mmc1dat4" ,"mmc1dat5" ,"mmc1dat6" ,"mmc1dat7" ,"mmc1rst" ,"pc1" ,"pc2" ,"pmbscclk" ,"pmbscdat" ,"pmuint" ,"resetn" ,"rfst2g_mtsloten3g" ,"rtxdata2g_txdata3g1" ,"rtxen2g_txdata3g2" ,"rxdata3g0" ,"rxdata3g1" ,"rxdata3g2" ,"sdck" ,"sdcmd" ,"sddat0" ,"sddat1" ,"sddat2" ,"sddat3" ,"simclk" ,"simdat" ,"simdet" ,"simrst" ,"gpio93" ,"gpio94" ,"spi0clk" ,"spi0fss" ,"spi0rxd" ,"spi0txd" ,"sri_c" ,"sri_d" ,"sri_e" ,"sspck" ,"sspdi" ,"sspdo" ,"sspsyn" ,"stat1" ,"stat2" ,"swclktck" ,"swdiotms" ,"sysclken" ,"tdi" ,"tdo" ,"testmode" ,"traceclk" ,"tracedt00" ,"tracedt01" ,"tracedt02" ,"tracedt03" ,"tracedt04" ,"tracedt05" ,"tracedt06" ,"tracedt07" ,"trstb" ,"txdata3g0" ,"ubctsn" ,"ubrtsn" ,"ubrx" ,"ubtx" ,"tracedt08" ,"tracedt09" ,"tracedt10" ,"tracedt11" ,"tracedt12" ,"tracedt13" ,"tracedt14" ,"tracedt15" ,#define BCM21664_PIN_FUNCTION(fcn_name) \#fcn_name , \static const struct bcm281xx_pin_function bcm21664_functions[] = {static const struct regmap_config bcm21664_pinctrl_regmap_config = {static const struct bcm281xx_pinctrl_info bcm21664_pinctrl = {/* BCM21664 pinctrl access lock handlers */ static int bcm21664_pinctrl_lock_all(struct bcm281xx_pinctrl_data *pdata)int i, rc;for (i = 0; i < BCM21664_ACCESS_LOCK_COUNT; i++) {if (rc) {"Failed to enable write access: %d\n" ,return rc;if (rc) {"Failed to write access lock: %d\n" ,return rc;return 0;static int bcm21664_pinctrl_set_pin_lock(struct bcm281xx_pinctrl_data *pdata,unsigned int pin, bool lock)unsigned int access_lock = pin / 32;int rc;"%s(): %s pin %s (%d)\n" ,"Lock" : "Unlock" , pdata->info->pins[pin].name,if (rc) {"Failed to enable write access: %d\n" ,return rc;int )lock << (pin % 32));if (rc) {"Failed to %s pin: %d\n" ,"lock" : "unlock" , rc);return rc;return 0;static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev,unsigned int pin)struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);if (pin >= pdata->info->npins)return BCM281XX_PIN_TYPE_UNKNOWN;return *(enum bcm281xx_pin_type *)(pdata->info->pins[pin].drv_data);#define BCM281XX_PIN_SHIFT(type, param) \## type ## _PIN_REG_ ## param ## _SHIFT)#define BCM281XX_PIN_MASK(type, param) \## type ## _PIN_REG_ ## param ## _MASK)/* * This helper function is used to build up the value and mask used to write to * a pin register, but does not actually write to the register. static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);return pdata->info->npins;static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,unsigned int group)struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);return pdata->info->pins[group].name;static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,unsigned int group,const unsigned **pins,unsigned int *num_pins)struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);return 0;static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,struct seq_file *s,unsigned int offset)" %s" , dev_name(pctldev->dev));static const struct pinctrl_ops bcm281xx_pinctrl_ops = {static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);return pdata->info->nfunctions;static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,unsigned int function)struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);return pdata->info->functions[function].name;static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,unsigned int function,const char * const **groups,unsigned int * const num_groups)struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);return 0;static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,unsigned int function,unsigned int group)struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);const struct bcm281xx_pin_function *f = &pdata->info->functions[function];enum bcm281xx_pinctrl_type device_type = pdata->info->device_type;unsigned int pin = pdata->info->pins[group].number;int rc = 0;"%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n" ,if (device_type == BCM21664_PINCTRL_TYPE) {false );if (rc) {/* Error is printed in bcm21664_pinctrl_set_pin_lock */ return rc;if (rc)"Error updating register for pin %s (%d).\n" ,if (device_type == BCM21664_PINCTRL_TYPE) {true );if (rc) {/* Error is printed in bcm21664_pinctrl_set_pin_lock */ return rc;return rc;static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,unsigned int pin,unsigned long *config)return -ENOTSUPP;/* Goes through the configs and update register val/mask */ static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev,unsigned int pin,unsigned long *configs,unsigned int num_configs,struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);int i;enum pin_config_param param;for (i = 0; i < num_configs; i++) {switch (param) {case PIN_CONFIG_INPUT_SCHMITT_ENABLE:break ;/* * The pin bias can only be one of pull-up, pull-down, or * disable. The user does not need to specify a value for the * property, and the default value from pinconf-generic is * ignored. case PIN_CONFIG_BIAS_DISABLE:break ;case PIN_CONFIG_BIAS_PULL_UP:break ;case PIN_CONFIG_BIAS_PULL_DOWN:break ;case PIN_CONFIG_SLEW_RATE:break ;case PIN_CONFIG_INPUT_ENABLE:/* inversed since register is for input _disable_ */ break ;case PIN_CONFIG_DRIVE_STRENGTH:/* Valid range is 2-16 mA, even numbers only */ if ((arg < 2) || (arg > 16) || (arg % 2)) {"Invalid Drive Strength value (%d) for " "pin %s (%d). Valid values are " "(2..16) mA, even numbers only.\n" ,return -EINVAL;break ;default :"Unrecognized pin config %d for pin %s (%d).\n" ,return -EINVAL;/* switch config */ /* for each config */ return 0;/* * The pull-up strength for an I2C pin is represented by bits 4-6 in the * register with the following mapping: * 0b000: No pull-up * 0b001: 1200 Ohm * 0b010: 1800 Ohm * 0b011: 720 Ohm * 0b100: 2700 Ohm * 0b101: 831 Ohm * 0b110: 1080 Ohm * 0b111: 568 Ohm * This array maps pull-up strength in Ohms to register values (1+index). static const u16 bcm281xx_pullup_map[] = {/* Goes through the configs and update register val/mask */ static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev,unsigned int pin,unsigned long *configs,unsigned int num_configs,struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);int i, j;enum pin_config_param param;for (i = 0; i < num_configs; i++) {switch (param) {case PIN_CONFIG_BIAS_PULL_UP:for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++)if (bcm281xx_pullup_map[j] == arg)break ;if (j == ARRAY_SIZE(bcm281xx_pullup_map)) {"Invalid pull-up value (%d) for pin %s " "(%d). Valid values are 568, 720, 831, " "1080, 1200, 1800, 2700 Ohms.\n" ,return -EINVAL;break ;case PIN_CONFIG_BIAS_DISABLE:break ;case PIN_CONFIG_SLEW_RATE:break ;case PIN_CONFIG_INPUT_ENABLE:/* inversed since register is for input _disable_ */ break ;default :"Unrecognized pin config %d for pin %s (%d).\n" ,return -EINVAL;/* switch config */ /* for each config */ return 0;/* Goes through the configs and update register val/mask */ static int bcm21664_i2c_pin_update(struct pinctrl_dev *pctldev,unsigned int pin,unsigned long *configs,unsigned int num_configs,struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);int i;enum pin_config_param param;for (i = 0; i < num_configs; i++) {/* * BCM21664 I2C pins use the same config bits as standard pins, * but only pull up/none, slew rate and input enable/disable * options are supported. switch (param) {case PIN_CONFIG_BIAS_PULL_UP:break ;case PIN_CONFIG_BIAS_DISABLE:break ;case PIN_CONFIG_SLEW_RATE:break ;case PIN_CONFIG_INPUT_ENABLE:/* inversed since register is for input _disable_ */ break ;default :"Unrecognized pin config %d for pin %s (%d).\n" ,return -EINVAL;/* switch config */ /* for each config */ return 0;/* Goes through the configs and update register val/mask */ static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev,unsigned int pin,unsigned long *configs,unsigned int num_configs,struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);int i;enum pin_config_param param;for (i = 0; i < num_configs; i++) {switch (param) {case PIN_CONFIG_SLEW_RATE:
Messung V0.5 C=95 H=93 G=93
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