// SPDX-License-Identifier: GPL-2.0 /* * Intel Denverton SoC pinctrl/GPIO driver * * Copyright (C) 2017, Intel Corporation * Author: Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define DNV_PAD_OWN 0x020#define DNV_PADCFGLOCK 0x090#define DNV_HOSTSW_OWN 0x0C0#define DNV_GPI_IS 0x100#define DNV_GPI_IE 0x120#define DNV_GPP(n, s, e) \#define DNV_COMMUNITY(b, s, e, g) \/* Denverton */ static const struct pinctrl_pin_desc dnv_pins[] = {/* North ALL */ "GBE0_SDP0" ),"GBE1_SDP0" ),"GBE0_SDP1" ),"GBE1_SDP1" ),"GBE0_SDP2" ),"GBE1_SDP2" ),"GBE0_SDP3" ),"GBE1_SDP3" ),"GBE2_LED0" ),"GBE2_LED1" ),"GBE0_I2C_CLK" ),"GBE0_I2C_DATA" ),"GBE1_I2C_CLK" ),"GBE1_I2C_DATA" ),"NCSI_RXD0" ),"NCSI_CLK_IN" ),"NCSI_RXD1" ),"NCSI_CRS_DV" ),"IDSLDO_VID_TICKLE" ),"NCSI_TX_EN" ),"NCSI_TXD0" ),"NCSI_TXD1" ),"NCSI_ARB_OUT" ),"GBE0_LED0" ),"GBE0_LED1" ),"GBE1_LED0" ),"GBE1_LED1" ),"SPARE_0" ),"PCIE_CLKREQ0_N" ),"PCIE_CLKREQ1_N" ),"PCIE_CLKREQ2_N" ),"PCIE_CLKREQ3_N" ),"PCIE_CLKREQ4_N" ),"GBE_MDC" ),"GBE_MDIO" ),"SVID_ALERT_N" ),"SVID_DATA" ),"SVID_CLK" ),"THERMTRIP_N" ),"PROCHOT_N" ),"MEMHOT_N" ),/* South DFX */ "DFX_PORT_CLK0" ),"DFX_PORT_CLK1" ),"DFX_PORT0" ),"DFX_PORT1" ),"DFX_PORT2" ),"DFX_PORT3" ),"DFX_PORT4" ),"DFX_PORT5" ),"DFX_PORT6" ),"DFX_PORT7" ),"DFX_PORT8" ),"DFX_PORT9" ),"DFX_PORT10" ),"DFX_PORT11" ),"DFX_PORT12" ),"DFX_PORT13" ),"DFX_PORT14" ),"DFX_PORT15" ),/* South GPP0 */ "SPI_TPM_CS_N" ),"UART2_CTS" ),"PCIE_CLKREQ5_N" ),"PCIE_CLKREQ6_N" ),"PCIE_CLKREQ7_N" ),"UART0_RXD" ),"UART0_TXD" ),"CPU_RESET_N" ),"NMI" ),"ERROR2_N" ),"ERROR1_N" ),"ERROR0_N" ),"IERR_N" ),"MCERR_N" ),"SMB0_LEG_CLK" ),"SMB0_LEG_DATA" ),"SMB0_LEG_ALRT_N" ),"SMB1_HOST_DATA" ),"SMB1_HOST_CLK" ),"SMB2_PECI_DATA" ),"SMB2_PECI_CLK" ),"SMB4_CSME0_DATA" ),"SMB4_CSME0_CLK" ),"SMB4_CSME0_ALRT_N" ),"USB_OC0_N" ),"FLEX_CLK_SE0" ),"FLEX_CLK_SE1" ),"SPARE_4" ),"SMB3_IE0_CLK" ),"SMB3_IE0_DATA" ),"SMB3_IE0_ALRT_N" ),"SATA0_LED_N" ),"SATA1_LED_N" ),"SATA_PDETECT0" ),"SATA_PDETECT1" ),"UART1_RTS" ),"UART1_CTS" ),"UART1_RXD" ),"UART1_TXD" ),"SPARE_8" ),"SPARE_9" ),"TCK" ),"TRST_N" ),"TMS" ),"TDI" ),"TDO" ),"CX_PRDY_N" ),"CX_PREQ_N" ),"TAP1_TCK" ),"TAP1_TRST_N" ),"TAP1_TMS" ),"TAP1_TDI" ),"TAP1_TDO" ),/* South GPP1 */ "SUSPWRDNACK" ),"PMU_SUSCLK" ),"ADR_TRIGGER" ),"PMU_SLP_S45_N" ),"PMU_SLP_S3_N" ),"PMU_WAKE_N" ),"PMU_PWRBTN_N" ),"PMU_RESETBUTTON_N" ),"PMU_PLTRST_N" ),"SUS_STAT_N" ),"SLP_S0IX_N" ),"SPI_CS0_N" ),"SPI_CS1_N" ),"SPI_MOSI_IO0" ),"SPI_MISO_IO1" ),"SPI_IO2" ),"SPI_IO3" ),"SPI_CLK" ),"SPI_CLK_LOOPBK" ),"ESPI_IO0" ),"ESPI_IO1" ),"ESPI_IO2" ),"ESPI_IO3" ),"ESPI_CS0_N" ),"ESPI_CLK" ),"ESPI_RST_N" ),"ESPI_ALRT0_N" ),"ESPI_CS1_N" ),"ESPI_ALRT1_N" ),"ESPI_CLK_LOOPBK" ),"EMMC_CMD" ),"EMMC_STROBE" ),"EMMC_CLK" ),"EMMC_D0" ),"EMMC_D1" ),"EMMC_D2" ),"EMMC_D3" ),"EMMC_D4" ),"EMMC_D5" ),"EMMC_D6" ),"EMMC_D7" ),"SPARE_3" ),static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 };static const unsigned int dnv_emmc_pins[] = {static const struct intel_pingroup dnv_groups[] = {"uart0_grp" , dnv_uart0_pins, dnv_uart0_modes),"uart1_grp" , dnv_uart1_pins, 1),"uart2_grp" , dnv_uart2_pins, dnv_uart2_modes),"emmc_grp" , dnv_emmc_pins, 1),static const char * const dnv_uart0_groups[] = { "uart0_grp" };static const char * const dnv_uart1_groups[] = { "uart1_grp" };static const char * const dnv_uart2_groups[] = { "uart2_grp" };static const char * const dnv_emmc_groups[] = { "emmc_grp" };static const struct intel_function dnv_functions[] = {"uart0" , dnv_uart0_groups),"uart1" , dnv_uart1_groups),"uart2" , dnv_uart2_groups),"emmc" , dnv_emmc_groups),static const struct intel_padgroup dnv_north_gpps[] = {/* North ALL_0 */ /* North ALL_1 */ static const struct intel_padgroup dnv_south_gpps[] = {/* South DFX */ /* South GPP0_0 */ /* South GPP0_1 */ /* South GPP1_0 */ /* South GPP1_1 */ static const struct intel_community dnv_communities[] = {static const struct intel_pinctrl_soc_data dnv_soc_data = {static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {"INTC3000" , (kernel_ulong_t)&dnv_soc_data },static const struct platform_device_id dnv_pinctrl_platform_ids[] = {"denverton-pinctrl" , (kernel_ulong_t)&dnv_soc_data },static struct platform_driver dnv_pinctrl_driver = {"denverton-pinctrl" ,static int __init dnv_pinctrl_init(void )return platform_driver_register(&dnv_pinctrl_driver);static void __exit dnv_pinctrl_exit(void )"Mika Westerberg " );"Intel Denverton SoC pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 C=93 H=97 G=94
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