// SPDX-License-Identifier: GPL-2.0 /* * Intel Gemini Lake SoC pinctrl/GPIO driver * * Copyright (C) 2017 Intel Corporation * Author: Mika Westerberg <mika.westerberg@linux.intel.com> #include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/pm.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-intel.h" #define GLK_PAD_OWN 0x020#define GLK_PADCFGLOCK 0x080#define GLK_HOSTSW_OWN 0x0b0#define GLK_GPI_IS 0x100#define GLK_GPI_IE 0x110#define GLK_COMMUNITY(b, s, e) \/* GLK */ static const struct pinctrl_pin_desc glk_northwest_pins[] = {"TCK" ),"TRST_B" ),"TMS" ),"TDI" ),"TDO" ),"JTAGX" ),"CX_PREQ_B" ),"CX_PRDY_B" ),"GPIO_8" ),"GPIO_9" ),"GPIO_10" ),"GPIO_11" ),"GPIO_12" ),"GPIO_13" ),"GPIO_14" ),"GPIO_15" ),"GPIO_16" ),"GPIO_17" ),"GPIO_18" ),"GPIO_19" ),"GPIO_20" ),"GPIO_21" ),"GPIO_22" ),"GPIO_23" ),"GPIO_24" ),"GPIO_25" ),"ISH_GPIO_0" ),"ISH_GPIO_1" ),"ISH_GPIO_2" ),"ISH_GPIO_3" ),"ISH_GPIO_4" ),"ISH_GPIO_5" ),"ISH_GPIO_6" ),"ISH_GPIO_7" ),"ISH_GPIO_8" ),"ISH_GPIO_9" ),"GPIO_36" ),"GPIO_37" ),"GPIO_38" ),"GPIO_39" ),"GPIO_40" ),"GPIO_41" ),"GP_INTD_DSI_TE1" ),"GP_INTD_DSI_TE2" ),"USB_OC0_B" ),"USB_OC1_B" ),"DSI_I2C_SDA" ),"DSI_I2C_SCL" ),"PMC_I2C_SDA" ),"PMC_I2C_SCL" ),"LPSS_I2C0_SDA" ),"LPSS_I2C0_SCL" ),"LPSS_I2C1_SDA" ),"LPSS_I2C1_SCL" ),"LPSS_I2C2_SDA" ),"LPSS_I2C2_SCL" ),"LPSS_I2C3_SDA" ),"LPSS_I2C3_SCL" ),"LPSS_I2C4_SDA" ),"LPSS_I2C4_SCL" ),"LPSS_UART0_RXD" ),"LPSS_UART0_TXD" ),"LPSS_UART0_RTS_B" ),"LPSS_UART0_CTS_B" ),"LPSS_UART2_RXD" ),"LPSS_UART2_TXD" ),"LPSS_UART2_RTS_B" ),"LPSS_UART2_CTS_B" ),"PMC_SPI_FS0" ),"PMC_SPI_FS1" ),"PMC_SPI_FS2" ),"PMC_SPI_RXD" ),"PMC_SPI_TXD" ),"PMC_SPI_CLK" ),"THERMTRIP_B" ),"PROCHOT_B" ),"EMMC_RST_B" ),"GPIO_212" ),"GPIO_213" ),"GPIO_214" ),static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 };static const unsigned int glk_northwest_pwm0_pins[] = { 42 };static const unsigned int glk_northwest_pwm1_pins[] = { 43 };static const unsigned int glk_northwest_pwm2_pins[] = { 44 };static const unsigned int glk_northwest_pwm3_pins[] = { 45 };static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 };static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 };static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 };static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 };static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 };static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 };static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 };static const struct intel_pingroup glk_northwest_groups[] = {"uart1_grp" , glk_northwest_uart1_pins, 2),"pwm0_grp" , glk_northwest_pwm0_pins, 2),"pwm1_grp" , glk_northwest_pwm1_pins, 2),"pwm2_grp" , glk_northwest_pwm2_pins, 2),"pwm3_grp" , glk_northwest_pwm3_pins, 2),"i2c0_grp" , glk_northwest_i2c0_pins, 1),"i2c1_grp" , glk_northwest_i2c1_pins, 1),"i2c2_grp" , glk_northwest_i2c2_pins, 1),"i2c3_grp" , glk_northwest_i2c3_pins, 1),"i2c4_grp" , glk_northwest_i2c4_pins, 1),"uart0_grp" , glk_northwest_uart0_pins, 1),"uart2_grp" , glk_northwest_uart2_pins, 1),static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" };static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" };static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" };static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" };static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" };static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" };static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" };static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" };static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" };static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" };static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" };static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" };static const struct intel_function glk_northwest_functions[] = {"uart1" , glk_northwest_uart1_groups),"pmw0" , glk_northwest_pwm0_groups),"pmw1" , glk_northwest_pwm1_groups),"pmw2" , glk_northwest_pwm2_groups),"pmw3" , glk_northwest_pwm3_groups),"i2c0" , glk_northwest_i2c0_groups),"i2c1" , glk_northwest_i2c1_groups),"i2c2" , glk_northwest_i2c2_groups),"i2c3" , glk_northwest_i2c3_groups),"i2c4" , glk_northwest_i2c4_groups),"uart0" , glk_northwest_uart0_groups),"uart2" , glk_northwest_uart2_groups),static const struct intel_community glk_northwest_communities[] = {static const struct intel_pinctrl_soc_data glk_northwest_soc_data = {"1" ,static const struct pinctrl_pin_desc glk_north_pins[] = {"SVID0_ALERT_B" ),"SVID0_DATA" ),"SVID0_CLK" ),"LPSS_SPI_0_CLK" ),"LPSS_SPI_0_FS0" ),"LPSS_SPI_0_FS1" ),"LPSS_SPI_0_RXD" ),"LPSS_SPI_0_TXD" ),"LPSS_SPI_2_CLK" ),"LPSS_SPI_2_FS0" ),"LPSS_SPI_2_FS1" ),"LPSS_SPI_2_FS2" ),"LPSS_SPI_2_RXD" ),"LPSS_SPI_2_TXD" ),"FST_SPI_CS0_B" ),"FST_SPI_CS1_B" ),"FST_SPI_MOSI_IO0" ),"FST_SPI_MISO_IO1" ),"FST_SPI_IO2" ),"FST_SPI_IO3" ),"FST_SPI_CLK" ),"FST_SPI_CLK_FB" ),"PMU_PLTRST_B" ),"PMU_PWRBTN_B" ),"PMU_SLP_S0_B" ),"PMU_SLP_S3_B" ),"PMU_SLP_S4_B" ),"SUSPWRDNACK" ),"EMMC_DNX_PWR_EN_B" ),"GPIO_105" ),"PMU_BATLOW_B" ),"PMU_RESETBUTTON_B" ),"PMU_SUSCLK" ),"SUS_STAT_B" ),"LPSS_I2C5_SDA" ),"LPSS_I2C5_SCL" ),"LPSS_I2C6_SDA" ),"LPSS_I2C6_SCL" ),"LPSS_I2C7_SDA" ),"LPSS_I2C7_SCL" ),"PCIE_WAKE0_B" ),"PCIE_WAKE1_B" ),"PCIE_WAKE2_B" ),"PCIE_WAKE3_B" ),"PCIE_CLKREQ0_B" ),"PCIE_CLKREQ1_B" ),"PCIE_CLKREQ2_B" ),"PCIE_CLKREQ3_B" ),"HV_DDI0_DDC_SDA" ),"HV_DDI0_DDC_SCL" ),"HV_DDI1_DDC_SDA" ),"HV_DDI1_DDC_SCL" ),"PANEL0_VDDEN" ),"PANEL0_BKLTEN" ),"PANEL0_BKLTCTL" ),"HV_DDI0_HPD" ),"HV_DDI1_HPD" ),"HV_EDP_HPD" ),"GPIO_134" ),"GPIO_135" ),"GPIO_136" ),"GPIO_137" ),"GPIO_138" ),"GPIO_139" ),"GPIO_140" ),"GPIO_141" ),"GPIO_142" ),"GPIO_143" ),"GPIO_144" ),"GPIO_145" ),"GPIO_146" ),"LPC_ILB_SERIRQ" ),"LPC_CLKOUT0" ),"LPC_CLKOUT1" ),"LPC_AD0" ),"LPC_AD1" ),"LPC_AD2" ),"LPC_AD3" ),"LPC_CLKRUNB" ),"LPC_FRAMEB" ),static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 };static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 };static const unsigned int glk_north_i2c5_pins[] = { 34, 35 };static const unsigned int glk_north_i2c6_pins[] = { 36, 37 };static const unsigned int glk_north_i2c7_pins[] = { 38, 39 };static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 };static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 };static const struct intel_pingroup glk_north_groups[] = {"spi0_grp" , glk_north_spi0_pins, 1),"spi1_grp" , glk_north_spi1_pins, 1),"i2c5_grp" , glk_north_i2c5_pins, 1),"i2c6_grp" , glk_north_i2c6_pins, 1),"i2c7_grp" , glk_north_i2c7_pins, 1),"uart0_grp" , glk_north_uart0_pins, 2),"spi0b_grp" , glk_north_spi0b_pins, 2),static const char * const glk_north_spi0_groups[] = { "spi0_grp" , "spi0b_grp" };static const char * const glk_north_spi1_groups[] = { "spi1_grp" };static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" };static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" };static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" };static const char * const glk_north_uart0_groups[] = { "uart0_grp" };static const struct intel_function glk_north_functions[] = {"spi0" , glk_north_spi0_groups),"spi1" , glk_north_spi1_groups),"i2c5" , glk_north_i2c5_groups),"i2c6" , glk_north_i2c6_groups),"i2c7" , glk_north_i2c7_groups),"uart0" , glk_north_uart0_groups),static const struct intel_community glk_north_communities[] = {static const struct intel_pinctrl_soc_data glk_north_soc_data = {"2" ,static const struct pinctrl_pin_desc glk_audio_pins[] = {"AVS_I2S0_MCLK" ),"AVS_I2S0_BCLK" ),"AVS_I2S0_WS_SYNC" ),"AVS_I2S0_SDI" ),"AVS_I2S0_SDO" ),"AVS_I2S1_MCLK" ),"AVS_I2S1_BCLK" ),"AVS_I2S1_WS_SYNC" ),"AVS_I2S1_SDI" ),"AVS_I2S1_SDO" ),"AVS_HDA_BCLK" ),"AVS_HDA_WS_SYNC" ),"AVS_HDA_SDI" ),"AVS_HDA_SDO" ),"AVS_HDA_RSTB" ),"AVS_M_CLK_A1" ),"AVS_M_CLK_B1" ),"AVS_M_DATA_1" ),"AVS_M_CLK_AB2" ),"AVS_M_DATA_2" ),static const struct intel_community glk_audio_communities[] = {static const struct intel_pinctrl_soc_data glk_audio_soc_data = {"3" ,static const struct pinctrl_pin_desc glk_scc_pins[] = {"SMB_ALERTB" ),"SMB_CLK" ),"SMB_DATA" ),"SDCARD_LVL_WP" ),"SDCARD_CLK" ),"SDCARD_CLK_FB" ),"SDCARD_D0" ),"SDCARD_D1" ),"SDCARD_D2" ),"SDCARD_D3" ),"SDCARD_CMD" ),"SDCARD_CD_B" ),"SDCARD_PWR_DOWN_B" ),"GPIO_210" ),"OSC_CLK_OUT_0" ),"OSC_CLK_OUT_1" ),"CNV_BRI_DT" ),"CNV_BRI_RSP" ),"CNV_RGI_DT" ),"CNV_RGI_RSP" ),"CNV_RF_RESET_B" ),"XTAL_CLKREQ" ),"SDIO_CLK_FB" ),"EMMC0_CLK" ),"EMMC0_CLK_FB" ),"EMMC0_D0" ),"EMMC0_D1" ),"EMMC0_D2" ),"EMMC0_D3" ),"EMMC0_D4" ),"EMMC0_D5" ),"EMMC0_D6" ),"EMMC0_D7" ),"EMMC0_CMD" ),"EMMC0_STROBE" ),static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 };static const unsigned int glk_scc_sdcard_pins[] = {static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 };static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 };static const unsigned int glk_scc_emmc_pins[] = {static const struct intel_pingroup glk_scc_groups[] = {"i2c7_grp" , glk_scc_i2c7_pins, 2),"sdcard_grp" , glk_scc_sdcard_pins, 1),"sdio_grp" , glk_scc_sdio_pins, 2),"uart1_grp" , glk_scc_uart1_pins, 3),"emmc_grp" , glk_scc_emmc_pins, 1),static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" };static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" };static const char * const glk_scc_sdio_groups[] = { "sdio_grp" };static const char * const glk_scc_uart1_groups[] = { "uart1_grp" };static const char * const glk_scc_emmc_groups[] = { "emmc_grp" };static const struct intel_function glk_scc_functions[] = {"i2c7" , glk_scc_i2c7_groups),"sdcard" , glk_scc_sdcard_groups),"sdio" , glk_scc_sdio_groups),"uart1" , glk_scc_uart1_groups),"emmc" , glk_scc_emmc_groups),static const struct intel_community glk_scc_communities[] = {static const struct intel_pinctrl_soc_data glk_scc_soc_data = {"4" ,static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {static const struct acpi_device_id glk_pinctrl_acpi_match[] = {"INT3453" , (kernel_ulong_t)glk_pinctrl_soc_data },static struct platform_driver glk_pinctrl_driver = {"geminilake-pinctrl" ,static int __init glk_pinctrl_init(void )return platform_driver_register(&glk_pinctrl_driver);static void __exit glk_pinctrl_exit(void )"Mika Westerberg " );"Intel Gemini Lake SoC pinctrl/GPIO driver" );"GPL v2" );"PINCTRL_INTEL" );
Messung V0.5 C=97 H=94 G=95
¤ Dauer der Verarbeitung: 0.5 Sekunden
¤ *© Formatika GbR, Deutschland
