// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2016-2018 Nuvoton Technology corporation. // Copyright (c) 2016, Dell Inc #include <linux/device.h>#include <linux/gpio/driver.h>#include <linux/interrupt.h>#include <linux/irq.h>#include <linux/mfd/syscon.h>#include <linux/mod_devicetable.h>#include <linux/module.h>#include <linux/platform_device.h>#include <linux/property.h>#include <linux/regmap.h>#include <linux/seq_file.h>#include <linux/pinctrl/consumer.h>#include <linux/pinctrl/machine.h>#include <linux/pinctrl/pinconf-generic.h>#include <linux/pinctrl/pinconf.h>#include <linux/pinctrl/pinctrl.h>#include <linux/pinctrl/pinmux.h>/* GCR registers */ #define NPCM7XX_GCR_PDID 0x00#define NPCM7XX_GCR_MFSEL1 0x0C#define NPCM7XX_GCR_MFSEL2 0x10#define NPCM7XX_GCR_MFSEL3 0x64#define NPCM7XX_GCR_MFSEL4 0xb0#define NPCM7XX_GCR_CPCTL 0xD0#define NPCM7XX_GCR_CP2BST 0xD4#define NPCM7XX_GCR_B2CPNT 0xD8#define NPCM7XX_GCR_I2CSEGSEL 0xE0#define NPCM7XX_GCR_I2CSEGCTL 0xE4#define NPCM7XX_GCR_SRCNT 0x68#define NPCM7XX_GCR_FLOCKR1 0x74#define NPCM7XX_GCR_DSCNT 0x78#define SRCNT_ESPI BIT(3)/* GPIO registers */ #define NPCM7XX_GP_N_TLOCK1 0x00#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ #define NPCM7XX_GP_N_POL 0x08 /* Polarity */ #define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ #define NPCM7XX_GP_N_OE 0x10 /* Output Enable */ #define NPCM7XX_GP_N_OTYP 0x14#define NPCM7XX_GP_N_MP 0x18#define NPCM7XX_GP_N_PU 0x1c /* Pull-up */ #define NPCM7XX_GP_N_PD 0x20 /* Pull-down */ #define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ #define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ #define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ #define NPCM7XX_GP_N_OBL0 0x30#define NPCM7XX_GP_N_OBL1 0x34#define NPCM7XX_GP_N_OBL2 0x38#define NPCM7XX_GP_N_OBL3 0x3c#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ #define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ #define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ #define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ #define NPCM7XX_GP_N_SPLCK 0x50#define NPCM7XX_GP_N_MPLCK 0x54#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ #define NPCM7XX_GP_N_OSRC 0x5c#define NPCM7XX_GP_N_ODSC 0x60#define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */ #define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */ #define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */ #define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */ #define NPCM7XX_GP_N_TLOCK2 0x7c#define NPCM7XX_GPIO_PER_BANK 32#define NPCM7XX_GPIO_BANK_NUM 8#define NPCM7XX_GCR_NONE 0/* Structure for register banks */ struct npcm7xx_gpio {void __iomem *base;struct gpio_chip gc;int irqbase;int irq;int (*direction_input)(struct gpio_chip *chip, unsigned int offset);int (*direction_output)(struct gpio_chip *chip, unsigned int offset,int value);int (*request)(struct gpio_chip *chip, unsigned int offset);void (*free)(struct gpio_chip *chip, unsigned int offset);struct npcm7xx_pinctrl {struct pinctrl_dev *pctldev;struct device *dev;struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM];struct irq_domain *domain;struct regmap *gcr_regmap;void __iomem *regs;/* GPIO handling in the pinctrl driver */ static void npcm_gpio_set(struct gpio_chip *gc, void __iomem *reg,unsigned int pinmask)unsigned long flags;unsigned long val;static void npcm_gpio_clr(struct gpio_chip *gc, void __iomem *reg,unsigned int pinmask)unsigned long flags;unsigned long val;static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)struct npcm7xx_gpio *bank = gpiochip_get_data(chip);"-- module %d [gpio%d - %d]\n" ,"DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n" ,"PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n" ,"ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n" ,"OTYP:%.8x OSRC:%.8x ODSC:%.8x\n" ,"OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n" ,"SLCK:%.8x MLCK:%.8x\n" ,static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset)struct npcm7xx_gpio *bank = gpiochip_get_data(chip);int ret;if (ret)return ret;return bank->direction_input(chip, offset);/* Set GPIO to Output with initial value */ static int npcmgpio_direction_output(struct gpio_chip *chip,unsigned int offset, int value)struct npcm7xx_gpio *bank = gpiochip_get_data(chip);int ret;"gpio_direction_output: offset%d = %x\n" , offset,if (ret)return ret;return bank->direction_output(chip, offset, value);static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset)struct npcm7xx_gpio *bank = gpiochip_get_data(chip);int ret;"gpio_request: offset%d\n" , offset);if (ret)return ret;return bank->request(chip, offset);static void npcmgpio_irq_handler(struct irq_desc *desc)struct gpio_chip *gc;struct irq_chip *chip;struct npcm7xx_gpio *bank;unsigned long sts, en, bit;"==> got irq sts %.8lx %.8lx\n" , sts,static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type)struct gpio_chip *gc = irq_data_get_irq_chip_data(d);struct npcm7xx_gpio *bank = gpiochip_get_data(gc);unsigned int gpio = BIT(irqd_to_hwirq(d));"setirqtype: %u.%u = %u\n" , gpio,switch (type) {case IRQ_TYPE_EDGE_RISING:"edge.rising\n" );break ;case IRQ_TYPE_EDGE_FALLING:"edge.falling\n" );break ;case IRQ_TYPE_EDGE_BOTH:"edge.both\n" );break ;case IRQ_TYPE_LEVEL_LOW:"level.low\n" );break ;case IRQ_TYPE_LEVEL_HIGH:"level.high\n" );break ;default :"invalid irq type\n" );return -EINVAL;if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISINGreturn 0;static void npcmgpio_irq_ack(struct irq_data *d)struct gpio_chip *gc = irq_data_get_irq_chip_data(d);struct npcm7xx_gpio *bank = gpiochip_get_data(gc);unsigned int gpio = irqd_to_hwirq(d);"irq_ack: %u.%u\n" , gpio, d->irq);/* Disable GPIO interrupt */ static void npcmgpio_irq_mask(struct irq_data *d)struct gpio_chip *gc = irq_data_get_irq_chip_data(d);struct npcm7xx_gpio *bank = gpiochip_get_data(gc);unsigned int gpio = irqd_to_hwirq(d);/* Clear events */ "irq_mask: %u.%u\n" , gpio, d->irq);/* Enable GPIO interrupt */ static void npcmgpio_irq_unmask(struct irq_data *d)struct gpio_chip *gc = irq_data_get_irq_chip_data(d);struct npcm7xx_gpio *bank = gpiochip_get_data(gc);unsigned int gpio = irqd_to_hwirq(d);/* Enable events */ "irq_unmask: %u.%u\n" , gpio, d->irq);static unsigned int npcmgpio_irq_startup(struct irq_data *d)struct gpio_chip *gc = irq_data_get_irq_chip_data(d);unsigned int gpio = irqd_to_hwirq(d);/* active-high, input, clear interrupt, enable interrupt */ "startup: %u.%u\n" , gpio, d->irq);return 0;static const struct irq_chip npcmgpio_irqchip = {"NPCM7XX-GPIO-IRQ" ,/* pinmux handing in the pinctrl driver*/ static const int smb0_pins[] = { 115, 114 };static const int smb0b_pins[] = { 195, 194 };static const int smb0c_pins[] = { 202, 196 };static const int smb0d_pins[] = { 198, 199 };static const int smb0den_pins[] = { 197 };static const int smb1_pins[] = { 117, 116 };static const int smb1b_pins[] = { 126, 127 };static const int smb1c_pins[] = { 124, 125 };static const int smb1d_pins[] = { 4, 5 };static const int smb2_pins[] = { 119, 118 };static const int smb2b_pins[] = { 122, 123 };static const int smb2c_pins[] = { 120, 121 };static const int smb2d_pins[] = { 6, 7 };static const int smb3_pins[] = { 30, 31 };static const int smb3b_pins[] = { 39, 40 };static const int smb3c_pins[] = { 37, 38 };static const int smb3d_pins[] = { 59, 60 };static const int smb4_pins[] = { 28, 29 };static const int smb4b_pins[] = { 18, 19 };static const int smb4c_pins[] = { 20, 21 };static const int smb4d_pins[] = { 22, 23 };static const int smb4den_pins[] = { 17 };static const int smb5_pins[] = { 26, 27 };static const int smb5b_pins[] = { 13, 12 };static const int smb5c_pins[] = { 15, 14 };static const int smb5d_pins[] = { 94, 93 };static const int ga20kbc_pins[] = { 94, 93 };static const int smb6_pins[] = { 172, 171 };static const int smb7_pins[] = { 174, 173 };static const int smb8_pins[] = { 129, 128 };static const int smb9_pins[] = { 131, 130 };static const int smb10_pins[] = { 133, 132 };static const int smb11_pins[] = { 135, 134 };static const int smb12_pins[] = { 221, 220 };static const int smb13_pins[] = { 223, 222 };static const int smb14_pins[] = { 22, 23 };static const int smb15_pins[] = { 20, 21 };static const int fanin0_pins[] = { 64 };static const int fanin1_pins[] = { 65 };static const int fanin2_pins[] = { 66 };static const int fanin3_pins[] = { 67 };static const int fanin4_pins[] = { 68 };static const int fanin5_pins[] = { 69 };static const int fanin6_pins[] = { 70 };static const int fanin7_pins[] = { 71 };static const int fanin8_pins[] = { 72 };static const int fanin9_pins[] = { 73 };static const int fanin10_pins[] = { 74 };static const int fanin11_pins[] = { 75 };static const int fanin12_pins[] = { 76 };static const int fanin13_pins[] = { 77 };static const int fanin14_pins[] = { 78 };static const int fanin15_pins[] = { 79 };static const int faninx_pins[] = { 175, 176, 177, 203 };static const int pwm0_pins[] = { 80 };static const int pwm1_pins[] = { 81 };static const int pwm2_pins[] = { 82 };static const int pwm3_pins[] = { 83 };static const int pwm4_pins[] = { 144 };static const int pwm5_pins[] = { 145 };static const int pwm6_pins[] = { 146 };static const int pwm7_pins[] = { 147 };static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 };static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 };/* RGMII 1 pin group */ static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105,/* RGMII 1 MD interface pin group */ static const int rg1mdio_pins[] = { 108, 109 };/* RGMII 2 pin group */ static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,/* RGMII 2 MD interface pin group */ static const int rg2mdio_pins[] = { 216, 217 };static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212,/* Serial I/O Expander 1 */ static const int iox1_pins[] = { 0, 1, 2, 3 };/* Serial I/O Expander 2 */ static const int iox2_pins[] = { 4, 5, 6, 7 };/* Host Serial I/O Expander 2 */ static const int ioxh_pins[] = { 10, 11, 24, 25 };static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 };static const int mmcwp_pins[] = { 153 };static const int mmccd_pins[] = { 155 };static const int mmcrst_pins[] = { 155 };static const int mmc8_pins[] = { 148, 149, 150, 151 };/* RMII 1 pin groups */ static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 };static const int r1err_pins[] = { 56 };static const int r1md_pins[] = { 57, 58 };/* RMII 2 pin groups */ static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 };static const int r2err_pins[] = { 90 };static const int r2md_pins[] = { 91, 92 };static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 };static const int sd1pwr_pins[] = { 143 };static const int wdog1_pins[] = { 218 };static const int wdog2_pins[] = { 219 };/* BMC serial port 0 */ static const int bmcuart0a_pins[] = { 41, 42 };static const int bmcuart0b_pins[] = { 48, 49 };static const int bmcuart1_pins[] = { 43, 44, 62, 63 };/* System Control Interrupt and Power Management Event pin group */ static const int scipme_pins[] = { 169 };/* System Management Interrupt pin group */ static const int sci_pins[] = { 170 };/* Serial Interrupt Line pin group */ static const int serirq_pins[] = { 162 };static const int clkout_pins[] = { 160 };static const int clkreq_pins[] = { 231 };static const int jtag2_pins[] = { 43, 44, 45, 46, 47 };/* Graphics SPI Clock pin group */ static const int gspi_pins[] = { 12, 13, 14, 15 };static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 };static const int spixcs1_pins[] = { 228 };static const int pspi1_pins[] = { 175, 176, 177 };static const int pspi2_pins[] = { 17, 18, 19 };static const int spi0cs1_pins[] = { 32 };static const int spi3_pins[] = { 183, 184, 185, 186 };static const int spi3cs1_pins[] = { 187 };static const int spi3quad_pins[] = { 188, 189 };static const int spi3cs2_pins[] = { 188 };static const int spi3cs3_pins[] = { 189 };static const int ddc_pins[] = { 204, 205, 206, 207 };static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 };static const int lpcclk_pins[] = { 168 };static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 };static const int lkgpo0_pins[] = { 16 };static const int lkgpo1_pins[] = { 8 };static const int lkgpo2_pins[] = { 9 };static const int nprd_smi_pins[] = { 190 };#define NPCM7XX_GRPS \enum {#define NPCM7XX_GRP(x) fn_ ## x/* add placeholder for none/gpio */ #undef NPCM7XX_GRPstatic struct pingroup npcm7xx_groups[] = {#define NPCM7XX_GRP(x) PINCTRL_PINGROUP(#x , x ## _pins, ARRAY_SIZE(x ## _pins))#undef NPCM7XX_GRP#define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a )#define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b }/* Function names */ static struct pinfunction npcm7xx_funcs[] = {#define NPCM7XX_MKFUNC(nm) PINCTRL_PINFUNCTION(#nm , nm ## _grp, ARRAY_SIZE(nm ## _grp))#undef NPCM7XX_MKFUNC#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \/* Drive strength controlled by NPCM7XX_GP_N_ODSC */ #define DRIVE_STRENGTH_LO_SHIFT 8#define DRIVE_STRENGTH_HI_SHIFT 12#define DRIVE_STRENGTH_MASK 0x0000FF00#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF)#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF)#define GPI 0x1 /* Not GPO */ #define GPO 0x2 /* Not GPI */ #define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */ #define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */ struct npcm7xx_pincfg {int flag;int fn0, reg0, bit0;int fn1, reg1, bit1;int fn2, reg2, bit2;static const struct npcm7xx_pincfg pincfg[] = {/* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */ /* Z1/A1 */ /* Z1/A1 */ LEW),LEW),/* XX */ /* XX */ /* SDHC1 power */ /* SDHC2 power */ /* DACOSEL */ /* number, name, drv_data */ static const struct pinctrl_pin_desc npcm7xx_pins[] = {"GPIO0/IOX1DI" ),"GPIO1/IOX1LD" ),"GPIO2/IOX1CK" ),"GPIO3/IOX1D0" ),"GPIO4/IOX2DI/SMB1DSDA" ),"GPIO5/IOX2LD/SMB1DSCL" ),"GPIO6/IOX2CK/SMB2DSDA" ),"GPIO7/IOX2D0/SMB2DSCL" ),"GPIO8/LKGPO1" ),"GPIO9/LKGPO2" ),"GPIO10/IOXHLD" ),"GPIO11/IOXHCK" ),"GPIO12/GSPICK/SMB5BSCL" ),"GPIO13/GSPIDO/SMB5BSDA" ),"GPIO14/GSPIDI/SMB5CSCL" ),"GPIO15/GSPICS/SMB5CSDA" ),"GPIO16/LKGPO0" ),"GPIO17/PSPI2DI/SMB4DEN" ),"GPIO18/PSPI2D0/SMB4BSDA" ),"GPIO19/PSPI2CK/SMB4BSCL" ),"GPIO20/SMB4CSDA/SMB15SDA" ),"GPIO21/SMB4CSCL/SMB15SCL" ),"GPIO22/SMB4DSDA/SMB14SDA" ),"GPIO23/SMB4DSCL/SMB14SCL" ),"GPIO24/IOXHDO" ),"GPIO25/IOXHDI" ),"GPIO26/SMB5SDA" ),"GPIO27/SMB5SCL" ),"GPIO28/SMB4SDA" ),"GPIO29/SMB4SCL" ),"GPIO30/SMB3SDA" ),"GPIO31/SMB3SCL" ),"GPIO32/nSPI0CS1" ),"SPI0D2" ),"SPI0D3" ),"GPIO37/SMB3CSDA" ),"GPIO38/SMB3CSCL" ),"GPIO39/SMB3BSDA" ),"GPIO40/SMB3BSCL" ),"GPIO41/BSPRXD" ),"GPO42/BSPTXD/STRAP11" ),"GPIO43/RXD1/JTMS2/BU1RXD" ),"GPIO44/nCTS1/JTDI2/BU1CTS" ),"GPIO45/nDCD1/JTDO2" ),"GPIO46/nDSR1/JTCK2" ),"GPIO47/nRI1/JCP_RDY2" ),"GPIO48/TXD2/BSPTXD" ),"GPIO49/RXD2/BSPRXD" ),"GPIO50/nCTS2" ),"GPO51/nRTS2/STRAP2" ),"GPIO52/nDCD2" ),"GPO53/nDTR2_BOUT2/STRAP1" ),"GPIO54/nDSR2" ),"GPIO55/nRI2" ),"GPIO56/R1RXERR" ),"GPIO57/R1MDC" ),"GPIO58/R1MDIO" ),"GPIO59/SMB3DSDA" ),"GPIO60/SMB3DSCL" ),"GPO61/nDTR1_BOUT1/STRAP6" ),"GPO62/nRTST1/STRAP5" ),"GPO63/TXD1/STRAP4" ),"GPIO64/FANIN0" ),"GPIO65/FANIN1" ),"GPIO66/FANIN2" ),"GPIO67/FANIN3" ),"GPIO68/FANIN4" ),"GPIO69/FANIN5" ),"GPIO70/FANIN6" ),"GPIO71/FANIN7" ),"GPIO72/FANIN8" ),"GPIO73/FANIN9" ),"GPIO74/FANIN10" ),"GPIO75/FANIN11" ),"GPIO76/FANIN12" ),"GPIO77/FANIN13" ),"GPIO78/FANIN14" ),"GPIO79/FANIN15" ),"GPIO80/PWM0" ),"GPIO81/PWM1" ),"GPIO82/PWM2" ),"GPIO83/PWM3" ),"GPIO84/R2TXD0" ),"GPIO85/R2TXD1" ),"GPIO86/R2TXEN" ),"GPIO87/R2RXD0" ),"GPIO88/R2RXD1" ),"GPIO89/R2CRSDV" ),"GPIO90/R2RXERR" ),"GPIO91/R2MDC" ),"GPIO92/R2MDIO" ),"GPIO93/GA20/SMB5DSCL" ),"GPIO94/nKBRST/SMB5DSDA" ),"GPIO95/nLRESET/nESPIRST" ),"GPIO96/RG1TXD0" ),"GPIO97/RG1TXD1" ),"GPIO98/RG1TXD2" ),"GPIO99/RG1TXD3" ),"GPIO100/RG1TXC" ),"GPIO101/RG1TXCTL" ),"GPIO102/RG1RXD0" ),"GPIO103/RG1RXD1" ),"GPIO104/RG1RXD2" ),"GPIO105/RG1RXD3" ),"GPIO106/RG1RXC" ),"GPIO107/RG1RXCTL" ),"GPIO108/RG1MDC" ),"GPIO109/RG1MDIO" ),"GPIO110/RG2TXD0/DDRV0" ),"GPIO111/RG2TXD1/DDRV1" ),"GPIO112/RG2TXD2/DDRV2" ),"GPIO113/RG2TXD3/DDRV3" ),"GPIO114/SMB0SCL" ),"GPIO115/SMB0SDA" ),"GPIO116/SMB1SCL" ),"GPIO117/SMB1SDA" ),"GPIO118/SMB2SCL" ),"GPIO119/SMB2SDA" ),"GPIO120/SMB2CSDA" ),"GPIO121/SMB2CSCL" ),"GPIO122/SMB2BSDA" ),"GPIO123/SMB2BSCL" ),"GPIO124/SMB1CSDA" ),"GPIO125/SMB1CSCL" ),"GPIO126/SMB1BSDA" ),"GPIO127/SMB1BSCL" ),"GPIO128/SMB8SCL" ),"GPIO129/SMB8SDA" ),"GPIO130/SMB9SCL" ),"GPIO131/SMB9SDA" ),"GPIO132/SMB10SCL" ),"GPIO133/SMB10SDA" ),"GPIO134/SMB11SCL" ),"GPIO135/SMB11SDA" ),"GPIO136/SD1DT0" ),"GPIO137/SD1DT1" ),"GPIO138/SD1DT2" ),"GPIO139/SD1DT3" ),"GPIO140/SD1CLK" ),"GPIO141/SD1WP" ),"GPIO142/SD1CMD" ),"GPIO143/SD1CD/SD1PWR" ),"GPIO144/PWM4" ),"GPIO145/PWM5" ),"GPIO146/PWM6" ),"GPIO147/PWM7" ),"GPIO148/MMCDT4" ),"GPIO149/MMCDT5" ),"GPIO150/MMCDT6" ),"GPIO151/MMCDT7" ),"GPIO152/MMCCLK" ),"GPIO153/MMCWP" ),"GPIO154/MMCCMD" ),"GPIO155/nMMCCD/nMMCRST" ),"GPIO156/MMCDT0" ),"GPIO157/MMCDT1" ),"GPIO158/MMCDT2" ),"GPIO159/MMCDT3" ),"GPIO160/CLKOUT/RNGOSCOUT" ),"GPIO161/nLFRAME/nESPICS" ),"GPIO162/SERIRQ" ),"GPIO163/LCLK/ESPICLK" ),"GPIO164/LAD0/ESPI_IO0" /*dscnt6*/), "GPIO165/LAD1/ESPI_IO1" /*dscnt6*/), "GPIO166/LAD2/ESPI_IO2" /*dscnt6*/), "GPIO167/LAD3/ESPI_IO3" /*dscnt6*/), "GPIO168/nCLKRUN/nESPIALERT" ),"GPIO169/nSCIPME" ),"GPIO170/nSMI" ),"GPIO171/SMB6SCL" ),"GPIO172/SMB6SDA" ),"GPIO173/SMB7SCL" ),"GPIO174/SMB7SDA" ),"GPIO175/PSPI1CK/FANIN19" ),"GPIO176/PSPI1DO/FANIN18" ),"GPIO177/PSPI1DI/FANIN17" ),"GPIO178/R1TXD0" ),"GPIO179/R1TXD1" ),"GPIO180/R1TXEN" ),"GPIO181/R1RXD0" ),"GPIO182/R1RXD1" ),"GPIO183/SPI3CK" ),"GPO184/SPI3D0/STRAP9" ),"GPO185/SPI3D1/STRAP10" ),"GPIO186/nSPI3CS0" ),"GPIO187/nSPI3CS1" ),"GPIO188/SPI3D2/nSPI3CS2" ),"GPIO189/SPI3D3/nSPI3CS3" ),"GPIO190/nPRD_SMI" ),"GPIO191" ),"GPIO192" ),"GPIO193/R1CRSDV" ),"GPIO194/SMB0BSCL" ),"GPIO195/SMB0BSDA" ),"GPIO196/SMB0CSCL" ),"GPIO197/SMB0DEN" ),"GPIO198/SMB0DSDA" ),"GPIO199/SMB0DSCL" ),"GPIO200/R2CK" ),"GPIO201/R1CK" ),"GPIO202/SMB0CSDA" ),"GPIO203/FANIN16" ),"GPIO204/DDC2SCL" ),"GPIO205/DDC2SDA" ),"GPIO206/HSYNC2" ),"GPIO207/VSYNC2" ),"GPIO208/RG2TXC/DVCK" ),"GPIO209/RG2TXCTL/DDRV4" ),"GPIO210/RG2RXD0/DDRV5" ),"GPIO211/RG2RXD1/DDRV6" ),"GPIO212/RG2RXD2/DDRV7" ),"GPIO213/RG2RXD3/DDRV8" ),"GPIO214/RG2RXC/DDRV9" ),"GPIO215/RG2RXCTL/DDRV10" ),"GPIO216/RG2MDC/DDRV11" ),"GPIO217/RG2MDIO/DVHSYNC" ),"GPIO218/nWDO1" ),"GPIO219/nWDO2" ),"GPIO220/SMB12SCL" ),"GPIO221/SMB12SDA" ),"GPIO222/SMB13SCL" ),"GPIO223/SMB13SDA" ),"GPIO224/SPIXCK" ),"GPO225/SPIXD0/STRAP12" ),"GPO226/SPIXD1/STRAP13" ),"GPIO227/nSPIXCS0" ),"GPIO228/nSPIXCS1" ),"GPO229/SPIXD2/STRAP3" ),"GPIO230/SPIXD3" ),"GPIO231/nCLKREQ" ),"GPI255/DACOSEL" ),/* Enable mode in pin group */ static void npcm7xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin,int pin_number, int mode)const struct npcm7xx_pincfg *cfg;int i;for (i = 0 ; i < pin_number ; i++) {if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) {if (cfg->reg0)if (cfg->reg1)if (cfg->reg2)/* Get slew rate of pin (high/low) */ static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank,struct regmap *gcr_regmap, unsigned int pin)int gpio = (pin % bank->gc.ngpio);unsigned long pinmask = BIT(gpio);if (pincfg[pin].flag & SLEW)return ioread32(bank->base + NPCM7XX_GP_N_OSRC)/* LPC Slew rate in SRCNT register */ if (pincfg[pin].flag & SLEWLPC) {return !!(val & SRCNT_ESPI);return -EINVAL;/* Set slew rate of pin (high/low) */ static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank,struct regmap *gcr_regmap, unsigned int pin,int arg)int gpio = BIT(pin % bank->gc.ngpio);if (pincfg[pin].flag & SLEW) {switch (arg) {case 0:return 0;case 1:return 0;default :return -EINVAL;/* LPC Slew rate in SRCNT register */ if (pincfg[pin].flag & SLEWLPC) {switch (arg) {case 0:return 0;case 1:return 0;default :return -EINVAL;return -EINVAL;/* Get drive strength for a pin, if supported */ static int npcm7xx_get_drive_strength(struct pinctrl_dev *pctldev,unsigned int pin)struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);struct npcm7xx_gpio *bank =int gpio = (pin % bank->gc.ngpio);unsigned long pinmask = BIT(gpio);int flg, val;if (flg & DRIVE_STRENGTH_MASK) {/* Get standard reading */ "pin %d strength %d = %d\n" , pin, val, ds);return ds;return -EINVAL;/* Set drive strength for a pin, if supported */ static int npcm7xx_set_drive_strength(struct npcm7xx_pinctrl *npcm,unsigned int pin, int nval)int v;struct npcm7xx_gpio *bank =int gpio = BIT(pin % bank->gc.ngpio);if (!nval || !v)return -ENOTSUPP;if (DSLO(v) == nval) {"setting pin %d to low strength [%d]\n" , pin, nval);return 0;else if (DSHI(v) == nval) {"setting pin %d to high strength [%d]\n" , pin, nval);return 0;return -ENOTSUPP;/* pinctrl_ops */ static void npcm7xx_pin_dbg_show(struct pinctrl_dev *pctldev,struct seq_file *s, unsigned int offset)"pinctrl_ops.dbg: %d" , offset);static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev)struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);"group size: %zu\n" , ARRAY_SIZE(npcm7xx_groups));return ARRAY_SIZE(npcm7xx_groups);static const char *npcm7xx_get_group_name(struct pinctrl_dev *pctldev,unsigned int selector)return npcm7xx_groups[selector].name;static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev,unsigned int selector,const unsigned int **pins,unsigned int *npins)return 0;static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev,struct pinctrl_map *map, u32 num_maps)static const struct pinctrl_ops npcm7xx_pinctrl_ops = {/* pinmux_ops */ static int npcm7xx_get_functions_count(struct pinctrl_dev *pctldev)return ARRAY_SIZE(npcm7xx_funcs);static const char *npcm7xx_get_function_name(struct pinctrl_dev *pctldev,unsigned int function)return npcm7xx_funcs[function].name;static int npcm7xx_get_function_groups(struct pinctrl_dev *pctldev,unsigned int function,const char * const **groups,unsigned int * const ngroups)return 0;static int npcm7xx_pinmux_set_mux(struct pinctrl_dev *pctldev,unsigned int function,unsigned int group)struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);"set_mux: %d, %d[%s]\n" , function, group,return 0;static int npcm7xx_gpio_request_enable(struct pinctrl_dev *pctldev,struct pinctrl_gpio_range *range,unsigned int offset)struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);if (!range) {"invalid range\n" );return -EINVAL;if (!range->gc) {"invalid gpiochip\n" );return -EINVAL;return 0;/* Release GPIO back to pinctrl mode */ static void npcm7xx_gpio_request_free(struct pinctrl_dev *pctldev,struct pinctrl_gpio_range *range,unsigned int offset)struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);int virq;if (virq)/* Set GPIO direction */ static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev,struct pinctrl_gpio_range *range,unsigned int offset, bool input)struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);struct npcm7xx_gpio *bank =int gpio = BIT(offset % bank->gc.ngpio);"GPIO Set Direction: %d = %d\n" , offset,if (input)else return 0;static const struct pinmux_ops npcm7xx_pinmux_ops = {/* pinconf_ops */ static int npcm7xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin,unsigned long *config)enum pin_config_param param = pinconf_to_config_param(*config);struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev);struct npcm7xx_gpio *bank =int gpio = (pin % bank->gc.ngpio);unsigned long pinmask = BIT(gpio);int rc = 0;switch (param) {case PIN_CONFIG_BIAS_DISABLE:case PIN_CONFIG_BIAS_PULL_UP:case PIN_CONFIG_BIAS_PULL_DOWN:if (param == PIN_CONFIG_BIAS_DISABLE)else if (param == PIN_CONFIG_BIAS_PULL_UP)else if (param == PIN_CONFIG_BIAS_PULL_DOWN)break ;case PIN_CONFIG_OUTPUT:case PIN_CONFIG_INPUT_ENABLE:if (param == PIN_CONFIG_INPUT_ENABLE)else if (param == PIN_CONFIG_OUTPUT)break ;case PIN_CONFIG_DRIVE_PUSH_PULL:
Messung V0.5 C=95 H=100 G=97
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