// SPDX-License-Identifier: GPL-2.0-only /* * linux/drivers/pinctrl/pinmux-xway.c * based on linux/drivers/pinctrl/pinmux-pxa910.c * * Copyright (C) 2012 John Crispin <john@phrozen.org> * Copyright (C) 2015 Martin Schiller <mschiller@tdt.de> #include <linux/err.h>#include <linux/gpio/driver.h>#include <linux/slab.h>#include <linux/module.h>#include <linux/of.h>#include <linux/ioport.h>#include <linux/io.h>#include <linux/device.h>#include <linux/platform_device.h>#include <linux/property.h>#include "pinctrl-lantiq.h" #include <lantiq_soc.h>/* we have up to 4 banks of 16 bit each */ #define PINS 16#define PORT3 3#define PORT(x) (x / PINS)#define PORT_PIN(x) (x % PINS)/* we have 2 mux bits that can be set for each pin */ #define MUX_ALT0 0x1#define MUX_ALT1 0x2/* * each bank has this offset apart from the 4th bank that is mixed into the * other 3 ranges #define REG_OFF 0x30/* these are the offsets to our registers */ #define GPIO_BASE(p) (REG_OFF * PORT(p))#define GPIO_OUT(p) GPIO_BASE(p)#define GPIO_IN(p) (GPIO_BASE(p) + 0x04)#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08)#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C)#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10)#define GPIO_OD(p) (GPIO_BASE(p) + 0x14)#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)/* the 4th port needs special offsets for some registers */ #define GPIO3_OD (GPIO_BASE(0) + 0x24)#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24)/* macros to help us access the registers */ #define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p)))#define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r)#define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r)#define MFP_XWAY(a, f0, f1, f2, f3) \#a , \## f0, \## f1, \## f2, \## f3, \#define GRP_MUX(a, m, p) \## m, .pins = p, .npins = ARRAY_SIZE(p), }#define FUNC_MUX(f, m) \## m, }enum xway_mux {/* --------- ase related code --------- */ #define ASE_MAX_PIN 32static const struct ltq_mfp_pin ase_mfp[] = {/* pin f0 f1 f2 f3 */ static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0};static const unsigned ase_pins_exin0[] = {GPIO6};static const unsigned ase_pins_exin1[] = {GPIO29};static const unsigned ase_pins_exin2[] = {GPIO0};static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27};static const unsigned ase_pins_ephy_led0[] = {GPIO2};static const unsigned ase_pins_ephy_led1[] = {GPIO3};static const unsigned ase_pins_ephy_led2[] = {GPIO4};static const unsigned ase_pins_dfe_led0[] = {GPIO1};static const unsigned ase_pins_dfe_led1[] = {GPIO2};static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; /* DEPRECATED */ static const unsigned ase_pins_spi_di[] = {GPIO8};static const unsigned ase_pins_spi_do[] = {GPIO9};static const unsigned ase_pins_spi_clk[] = {GPIO10};static const unsigned ase_pins_spi_cs1[] = {GPIO7};static const unsigned ase_pins_spi_cs2[] = {GPIO15};static const unsigned ase_pins_spi_cs3[] = {GPIO14};static const unsigned ase_pins_gpt1[] = {GPIO5};static const unsigned ase_pins_gpt2[] = {GPIO4};static const unsigned ase_pins_gpt3[] = {GPIO25};static const unsigned ase_pins_clkout0[] = {GPIO23};static const unsigned ase_pins_clkout1[] = {GPIO22};static const unsigned ase_pins_clkout2[] = {GPIO14};static const struct ltq_pin_group ase_grps[] = {"exin0" , EXIN, ase_pins_exin0),"exin1" , EXIN, ase_pins_exin1),"exin2" , EXIN, ase_pins_exin2),"jtag" , JTAG, ase_pins_jtag),"spi" , SPI, ase_pins_spi), /* DEPRECATED */ "spi_di" , SPI, ase_pins_spi_di),"spi_do" , SPI, ase_pins_spi_do),"spi_clk" , SPI, ase_pins_spi_clk),"spi_cs1" , SPI, ase_pins_spi_cs1),"spi_cs2" , SPI, ase_pins_spi_cs2),"spi_cs3" , SPI, ase_pins_spi_cs3),"asc" , ASC, ase_pins_asc),"stp" , STP, ase_pins_stp),"gpt1" , GPT, ase_pins_gpt1),"gpt2" , GPT, ase_pins_gpt2),"gpt3" , GPT, ase_pins_gpt3),"clkout0" , CGU, ase_pins_clkout0),"clkout1" , CGU, ase_pins_clkout1),"clkout2" , CGU, ase_pins_clkout2),"mdio" , MDIO, ase_pins_mdio),"dfe led0" , DFE, ase_pins_dfe_led0),"dfe led1" , DFE, ase_pins_dfe_led1),"ephy led0" , EPHY, ase_pins_ephy_led0),"ephy led1" , EPHY, ase_pins_ephy_led1),"ephy led2" , EPHY, ase_pins_ephy_led2),static const char * const ase_exin_grps[] = {"exin0" , "exin1" , "exin2" };static const char * const ase_gpt_grps[] = {"gpt1" , "gpt2" , "gpt3" };static const char * const ase_cgu_grps[] = {"clkout0" , "clkout1" ,"clkout2" };static const char * const ase_mdio_grps[] = {"mdio" };static const char * const ase_dfe_grps[] = {"dfe led0" , "dfe led1" };static const char * const ase_ephy_grps[] = {"ephy led0" , "ephy led1" ,"ephy led2" };static const char * const ase_asc_grps[] = {"asc" };static const char * const ase_jtag_grps[] = {"jtag" };static const char * const ase_stp_grps[] = {"stp" };static const char * const ase_spi_grps[] = {"spi" , /* DEPRECATED */ "spi_di" , "spi_do" ,"spi_clk" , "spi_cs1" ,"spi_cs2" , "spi_cs3" };static const struct ltq_pmx_func ase_funcs[] = {"spi" , ARRAY_AND_SIZE(ase_spi_grps)},"asc" , ARRAY_AND_SIZE(ase_asc_grps)},"cgu" , ARRAY_AND_SIZE(ase_cgu_grps)},"jtag" , ARRAY_AND_SIZE(ase_jtag_grps)},"exin" , ARRAY_AND_SIZE(ase_exin_grps)},"stp" , ARRAY_AND_SIZE(ase_stp_grps)},"gpt" , ARRAY_AND_SIZE(ase_gpt_grps)},"mdio" , ARRAY_AND_SIZE(ase_mdio_grps)},"ephy" , ARRAY_AND_SIZE(ase_ephy_grps)},"dfe" , ARRAY_AND_SIZE(ase_dfe_grps)},/* --------- danube related code --------- */ #define DANUBE_MAX_PIN 32static const struct ltq_mfp_pin danube_mfp[] = {/* pin f0 f1 f2 f3 */ static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2};static const unsigned danube_pins_exin0[] = {GPIO0};static const unsigned danube_pins_exin1[] = {GPIO1};static const unsigned danube_pins_exin2[] = {GPIO2};static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, GPIO20};static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12};static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10};static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6};static const unsigned danube_pins_nmi[] = {GPIO8};static const unsigned danube_pins_dfe_led0[] = {GPIO4};static const unsigned danube_pins_dfe_led1[] = {GPIO5};static const unsigned danube_pins_ebu_a24[] = {GPIO13};static const unsigned danube_pins_ebu_clk[] = {GPIO21};static const unsigned danube_pins_ebu_cs1[] = {GPIO23};static const unsigned danube_pins_ebu_a23[] = {GPIO24};static const unsigned danube_pins_ebu_wait[] = {GPIO26};static const unsigned danube_pins_ebu_a25[] = {GPIO31};static const unsigned danube_pins_nand_ale[] = {GPIO13};static const unsigned danube_pins_nand_cs1[] = {GPIO23};static const unsigned danube_pins_nand_cle[] = {GPIO24};static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; /* DEPRECATED */ static const unsigned danube_pins_spi_di[] = {GPIO16};static const unsigned danube_pins_spi_do[] = {GPIO17};static const unsigned danube_pins_spi_clk[] = {GPIO18};static const unsigned danube_pins_spi_cs1[] = {GPIO15};static const unsigned danube_pins_spi_cs2[] = {GPIO21};static const unsigned danube_pins_spi_cs3[] = {GPIO13};static const unsigned danube_pins_spi_cs4[] = {GPIO10};static const unsigned danube_pins_spi_cs5[] = {GPIO9};static const unsigned danube_pins_spi_cs6[] = {GPIO11};static const unsigned danube_pins_gpt1[] = {GPIO28};static const unsigned danube_pins_gpt2[] = {GPIO21};static const unsigned danube_pins_gpt3[] = {GPIO6};static const unsigned danube_pins_clkout0[] = {GPIO8};static const unsigned danube_pins_clkout1[] = {GPIO7};static const unsigned danube_pins_clkout2[] = {GPIO3};static const unsigned danube_pins_clkout3[] = {GPIO2};static const unsigned danube_pins_pci_gnt1[] = {GPIO30};static const unsigned danube_pins_pci_gnt2[] = {GPIO23};static const unsigned danube_pins_pci_gnt3[] = {GPIO19};static const unsigned danube_pins_pci_req1[] = {GPIO29};static const unsigned danube_pins_pci_req2[] = {GPIO31};static const unsigned danube_pins_pci_req3[] = {GPIO3};static const struct ltq_pin_group danube_grps[] = {"exin0" , EXIN, danube_pins_exin0),"exin1" , EXIN, danube_pins_exin1),"exin2" , EXIN, danube_pins_exin2),"jtag" , JTAG, danube_pins_jtag),"ebu a23" , EBU, danube_pins_ebu_a23),"ebu a24" , EBU, danube_pins_ebu_a24),"ebu a25" , EBU, danube_pins_ebu_a25),"ebu clk" , EBU, danube_pins_ebu_clk),"ebu cs1" , EBU, danube_pins_ebu_cs1),"ebu wait" , EBU, danube_pins_ebu_wait),"nand ale" , EBU, danube_pins_nand_ale),"nand cs1" , EBU, danube_pins_nand_cs1),"nand cle" , EBU, danube_pins_nand_cle),"spi" , SPI, danube_pins_spi), /* DEPRECATED */ "spi_di" , SPI, danube_pins_spi_di),"spi_do" , SPI, danube_pins_spi_do),"spi_clk" , SPI, danube_pins_spi_clk),"spi_cs1" , SPI, danube_pins_spi_cs1),"spi_cs2" , SPI, danube_pins_spi_cs2),"spi_cs3" , SPI, danube_pins_spi_cs3),"spi_cs4" , SPI, danube_pins_spi_cs4),"spi_cs5" , SPI, danube_pins_spi_cs5),"spi_cs6" , SPI, danube_pins_spi_cs6),"asc0" , ASC, danube_pins_asc0),"asc0 cts rts" , ASC, danube_pins_asc0_cts_rts),"stp" , STP, danube_pins_stp),"nmi" , NMI, danube_pins_nmi),"gpt1" , GPT, danube_pins_gpt1),"gpt2" , GPT, danube_pins_gpt2),"gpt3" , GPT, danube_pins_gpt3),"clkout0" , CGU, danube_pins_clkout0),"clkout1" , CGU, danube_pins_clkout1),"clkout2" , CGU, danube_pins_clkout2),"clkout3" , CGU, danube_pins_clkout3),"gnt1" , PCI, danube_pins_pci_gnt1),"gnt2" , PCI, danube_pins_pci_gnt2),"gnt3" , PCI, danube_pins_pci_gnt3),"req1" , PCI, danube_pins_pci_req1),"req2" , PCI, danube_pins_pci_req2),"req3" , PCI, danube_pins_pci_req3),"dfe led0" , DFE, danube_pins_dfe_led0),"dfe led1" , DFE, danube_pins_dfe_led1),static const char * const danube_pci_grps[] = {"gnt1" , "gnt2" ,"gnt3" , "req1" ,"req2" , "req3" };static const char * const danube_spi_grps[] = {"spi" , /* DEPRECATED */ "spi_di" , "spi_do" ,"spi_clk" , "spi_cs1" ,"spi_cs2" , "spi_cs3" ,"spi_cs4" , "spi_cs5" ,"spi_cs6" };static const char * const danube_cgu_grps[] = {"clkout0" , "clkout1" ,"clkout2" , "clkout3" };static const char * const danube_ebu_grps[] = {"ebu a23" , "ebu a24" ,"ebu a25" , "ebu cs1" ,"ebu wait" , "ebu clk" ,"nand ale" , "nand cs1" ,"nand cle" };static const char * const danube_dfe_grps[] = {"dfe led0" , "dfe led1" };static const char * const danube_exin_grps[] = {"exin0" , "exin1" , "exin2" };static const char * const danube_gpt_grps[] = {"gpt1" , "gpt2" , "gpt3" };static const char * const danube_asc_grps[] = {"asc0" , "asc0 cts rts" };static const char * const danube_jtag_grps[] = {"jtag" };static const char * const danube_stp_grps[] = {"stp" };static const char * const danube_nmi_grps[] = {"nmi" };static const struct ltq_pmx_func danube_funcs[] = {"spi" , ARRAY_AND_SIZE(danube_spi_grps)},"asc" , ARRAY_AND_SIZE(danube_asc_grps)},"cgu" , ARRAY_AND_SIZE(danube_cgu_grps)},"jtag" , ARRAY_AND_SIZE(danube_jtag_grps)},"exin" , ARRAY_AND_SIZE(danube_exin_grps)},"stp" , ARRAY_AND_SIZE(danube_stp_grps)},"gpt" , ARRAY_AND_SIZE(danube_gpt_grps)},"nmi" , ARRAY_AND_SIZE(danube_nmi_grps)},"pci" , ARRAY_AND_SIZE(danube_pci_grps)},"ebu" , ARRAY_AND_SIZE(danube_ebu_grps)},"dfe" , ARRAY_AND_SIZE(danube_dfe_grps)},/* --------- xrx100 related code --------- */ #define XRX100_MAX_PIN 56static const struct ltq_mfp_pin xrx100_mfp[] = {/* pin f0 f1 f2 f3 */ static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};static const unsigned xrx100_pins_exin0[] = {GPIO0};static const unsigned xrx100_pins_exin1[] = {GPIO1};static const unsigned xrx100_pins_exin2[] = {GPIO2};static const unsigned xrx100_pins_exin3[] = {GPIO39};static const unsigned xrx100_pins_exin4[] = {GPIO10};static const unsigned xrx100_pins_exin5[] = {GPIO9};static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12};static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10};static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6};static const unsigned xrx100_pins_nmi[] = {GPIO8};static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43};static const unsigned xrx100_pins_dfe_led0[] = {GPIO4};static const unsigned xrx100_pins_dfe_led1[] = {GPIO5};static const unsigned xrx100_pins_ebu_a24[] = {GPIO13};static const unsigned xrx100_pins_ebu_clk[] = {GPIO21};static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23};static const unsigned xrx100_pins_ebu_a23[] = {GPIO24};static const unsigned xrx100_pins_ebu_wait[] = {GPIO26};static const unsigned xrx100_pins_ebu_a25[] = {GPIO31};static const unsigned xrx100_pins_nand_ale[] = {GPIO13};static const unsigned xrx100_pins_nand_cs1[] = {GPIO23};static const unsigned xrx100_pins_nand_cle[] = {GPIO24};static const unsigned xrx100_pins_nand_rdy[] = {GPIO48};static const unsigned xrx100_pins_nand_rd[] = {GPIO49};static const unsigned xrx100_pins_spi_di[] = {GPIO16};static const unsigned xrx100_pins_spi_do[] = {GPIO17};static const unsigned xrx100_pins_spi_clk[] = {GPIO18};static const unsigned xrx100_pins_spi_cs1[] = {GPIO15};static const unsigned xrx100_pins_spi_cs2[] = {GPIO22};static const unsigned xrx100_pins_spi_cs3[] = {GPIO13};static const unsigned xrx100_pins_spi_cs4[] = {GPIO10};static const unsigned xrx100_pins_spi_cs5[] = {GPIO9};static const unsigned xrx100_pins_spi_cs6[] = {GPIO11};static const unsigned xrx100_pins_gpt1[] = {GPIO28};static const unsigned xrx100_pins_gpt2[] = {GPIO21};static const unsigned xrx100_pins_gpt3[] = {GPIO6};static const unsigned xrx100_pins_clkout0[] = {GPIO8};static const unsigned xrx100_pins_clkout1[] = {GPIO7};static const unsigned xrx100_pins_clkout2[] = {GPIO3};static const unsigned xrx100_pins_clkout3[] = {GPIO2};static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30};static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23};static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19};static const unsigned xrx100_pins_pci_gnt4[] = {GPIO38};static const unsigned xrx100_pins_pci_req1[] = {GPIO29};static const unsigned xrx100_pins_pci_req2[] = {GPIO31};static const unsigned xrx100_pins_pci_req3[] = {GPIO3};static const unsigned xrx100_pins_pci_req4[] = {GPIO37};static const struct ltq_pin_group xrx100_grps[] = {"exin0" , EXIN, xrx100_pins_exin0),"exin1" , EXIN, xrx100_pins_exin1),"exin2" , EXIN, xrx100_pins_exin2),"exin3" , EXIN, xrx100_pins_exin3),"exin4" , EXIN, xrx100_pins_exin4),"exin5" , EXIN, xrx100_pins_exin5),"ebu a23" , EBU, xrx100_pins_ebu_a23),"ebu a24" , EBU, xrx100_pins_ebu_a24),"ebu a25" , EBU, xrx100_pins_ebu_a25),"ebu clk" , EBU, xrx100_pins_ebu_clk),"ebu cs1" , EBU, xrx100_pins_ebu_cs1),"ebu wait" , EBU, xrx100_pins_ebu_wait),"nand ale" , EBU, xrx100_pins_nand_ale),"nand cs1" , EBU, xrx100_pins_nand_cs1),"nand cle" , EBU, xrx100_pins_nand_cle),"nand rdy" , EBU, xrx100_pins_nand_rdy),"nand rd" , EBU, xrx100_pins_nand_rd),"spi_di" , SPI, xrx100_pins_spi_di),"spi_do" , SPI, xrx100_pins_spi_do),"spi_clk" , SPI, xrx100_pins_spi_clk),"spi_cs1" , SPI, xrx100_pins_spi_cs1),"spi_cs2" , SPI, xrx100_pins_spi_cs2),"spi_cs3" , SPI, xrx100_pins_spi_cs3),"spi_cs4" , SPI, xrx100_pins_spi_cs4),"spi_cs5" , SPI, xrx100_pins_spi_cs5),"spi_cs6" , SPI, xrx100_pins_spi_cs6),"asc0" , ASC, xrx100_pins_asc0),"asc0 cts rts" , ASC, xrx100_pins_asc0_cts_rts),"stp" , STP, xrx100_pins_stp),"nmi" , NMI, xrx100_pins_nmi),"gpt1" , GPT, xrx100_pins_gpt1),"gpt2" , GPT, xrx100_pins_gpt2),"gpt3" , GPT, xrx100_pins_gpt3),"clkout0" , CGU, xrx100_pins_clkout0),"clkout1" , CGU, xrx100_pins_clkout1),"clkout2" , CGU, xrx100_pins_clkout2),"clkout3" , CGU, xrx100_pins_clkout3),"gnt1" , PCI, xrx100_pins_pci_gnt1),"gnt2" , PCI, xrx100_pins_pci_gnt2),"gnt3" , PCI, xrx100_pins_pci_gnt3),"gnt4" , PCI, xrx100_pins_pci_gnt4),"req1" , PCI, xrx100_pins_pci_req1),"req2" , PCI, xrx100_pins_pci_req2),"req3" , PCI, xrx100_pins_pci_req3),"req4" , PCI, xrx100_pins_pci_req4),"mdio" , MDIO, xrx100_pins_mdio),"dfe led0" , DFE, xrx100_pins_dfe_led0),"dfe led1" , DFE, xrx100_pins_dfe_led1),static const char * const xrx100_pci_grps[] = {"gnt1" , "gnt2" ,"gnt3" , "gnt4" ,"req1" , "req2" ,"req3" , "req4" };static const char * const xrx100_spi_grps[] = {"spi_di" , "spi_do" ,"spi_clk" , "spi_cs1" ,"spi_cs2" , "spi_cs3" ,"spi_cs4" , "spi_cs5" ,"spi_cs6" };static const char * const xrx100_cgu_grps[] = {"clkout0" , "clkout1" ,"clkout2" , "clkout3" };static const char * const xrx100_ebu_grps[] = {"ebu a23" , "ebu a24" ,"ebu a25" , "ebu cs1" ,"ebu wait" , "ebu clk" ,"nand ale" , "nand cs1" ,"nand cle" , "nand rdy" ,"nand rd" };static const char * const xrx100_exin_grps[] = {"exin0" , "exin1" , "exin2" ,"exin3" , "exin4" , "exin5" };static const char * const xrx100_gpt_grps[] = {"gpt1" , "gpt2" , "gpt3" };static const char * const xrx100_asc_grps[] = {"asc0" , "asc0 cts rts" };static const char * const xrx100_stp_grps[] = {"stp" };static const char * const xrx100_nmi_grps[] = {"nmi" };static const char * const xrx100_mdio_grps[] = {"mdio" };static const char * const xrx100_dfe_grps[] = {"dfe led0" , "dfe led1" };static const struct ltq_pmx_func xrx100_funcs[] = {"spi" , ARRAY_AND_SIZE(xrx100_spi_grps)},"asc" , ARRAY_AND_SIZE(xrx100_asc_grps)},"cgu" , ARRAY_AND_SIZE(xrx100_cgu_grps)},"exin" , ARRAY_AND_SIZE(xrx100_exin_grps)},"stp" , ARRAY_AND_SIZE(xrx100_stp_grps)},"gpt" , ARRAY_AND_SIZE(xrx100_gpt_grps)},"nmi" , ARRAY_AND_SIZE(xrx100_nmi_grps)},"pci" , ARRAY_AND_SIZE(xrx100_pci_grps)},"ebu" , ARRAY_AND_SIZE(xrx100_ebu_grps)},"mdio" , ARRAY_AND_SIZE(xrx100_mdio_grps)},"dfe" , ARRAY_AND_SIZE(xrx100_dfe_grps)},/* --------- xrx200 related code --------- */ #define XRX200_MAX_PIN 50static const struct ltq_mfp_pin xrx200_mfp[] = {/* pin f0 f1 f2 f3 */ static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};static const unsigned xrx200_pins_exin0[] = {GPIO0};static const unsigned xrx200_pins_exin1[] = {GPIO1};static const unsigned xrx200_pins_exin2[] = {GPIO2};static const unsigned xrx200_pins_exin3[] = {GPIO39};static const unsigned xrx200_pins_exin4[] = {GPIO10};static const unsigned xrx200_pins_exin5[] = {GPIO9};static const unsigned xrx200_pins_usif_uart_rx[] = {GPIO11};static const unsigned xrx200_pins_usif_uart_tx[] = {GPIO12};static const unsigned xrx200_pins_usif_uart_rts[] = {GPIO9};static const unsigned xrx200_pins_usif_uart_cts[] = {GPIO10};static const unsigned xrx200_pins_usif_uart_dtr[] = {GPIO4};static const unsigned xrx200_pins_usif_uart_dsr[] = {GPIO6};static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25};static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27};static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11};static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12};static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38};static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37};static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39};static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14};static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6};static const unsigned xrx200_pins_nmi[] = {GPIO8};static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43};static const unsigned xrx200_pins_dfe_led0[] = {GPIO4};static const unsigned xrx200_pins_dfe_led1[] = {GPIO5};static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5};static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7};static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2};static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44};static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45};static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47};static const unsigned xrx200_pins_ebu_a24[] = {GPIO13};static const unsigned xrx200_pins_ebu_clk[] = {GPIO21};static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23};static const unsigned xrx200_pins_ebu_a23[] = {GPIO24};static const unsigned xrx200_pins_ebu_wait[] = {GPIO26};static const unsigned xrx200_pins_ebu_a25[] = {GPIO31};static const unsigned xrx200_pins_nand_ale[] = {GPIO13};static const unsigned xrx200_pins_nand_cs1[] = {GPIO23};static const unsigned xrx200_pins_nand_cle[] = {GPIO24};static const unsigned xrx200_pins_nand_rdy[] = {GPIO48};static const unsigned xrx200_pins_nand_rd[] = {GPIO49};static const unsigned xrx200_pins_spi_di[] = {GPIO16};static const unsigned xrx200_pins_spi_do[] = {GPIO17};static const unsigned xrx200_pins_spi_clk[] = {GPIO18};static const unsigned xrx200_pins_spi_cs1[] = {GPIO15};static const unsigned xrx200_pins_spi_cs2[] = {GPIO22};static const unsigned xrx200_pins_spi_cs3[] = {GPIO13};static const unsigned xrx200_pins_spi_cs4[] = {GPIO10};static const unsigned xrx200_pins_spi_cs5[] = {GPIO9};static const unsigned xrx200_pins_spi_cs6[] = {GPIO11};static const unsigned xrx200_pins_gpt1[] = {GPIO28};static const unsigned xrx200_pins_gpt2[] = {GPIO21};static const unsigned xrx200_pins_gpt3[] = {GPIO6};static const unsigned xrx200_pins_clkout0[] = {GPIO8};static const unsigned xrx200_pins_clkout1[] = {GPIO7};static const unsigned xrx200_pins_clkout2[] = {GPIO3};static const unsigned xrx200_pins_clkout3[] = {GPIO2};static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28};static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23};static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19};static const unsigned xrx200_pins_pci_gnt4[] = {GPIO38};static const unsigned xrx200_pins_pci_req1[] = {GPIO29};static const unsigned xrx200_pins_pci_req2[] = {GPIO31};static const unsigned xrx200_pins_pci_req3[] = {GPIO3};static const unsigned xrx200_pins_pci_req4[] = {GPIO37};static const struct ltq_pin_group xrx200_grps[] = {"exin0" , EXIN, xrx200_pins_exin0),"exin1" , EXIN, xrx200_pins_exin1),"exin2" , EXIN, xrx200_pins_exin2),"exin3" , EXIN, xrx200_pins_exin3),"exin4" , EXIN, xrx200_pins_exin4),"exin5" , EXIN, xrx200_pins_exin5),"ebu a23" , EBU, xrx200_pins_ebu_a23),"ebu a24" , EBU, xrx200_pins_ebu_a24),"ebu a25" , EBU, xrx200_pins_ebu_a25),"ebu clk" , EBU, xrx200_pins_ebu_clk),"ebu cs1" , EBU, xrx200_pins_ebu_cs1),"ebu wait" , EBU, xrx200_pins_ebu_wait),"nand ale" , EBU, xrx200_pins_nand_ale),"nand cs1" , EBU, xrx200_pins_nand_cs1),"nand cle" , EBU, xrx200_pins_nand_cle),"nand rdy" , EBU, xrx200_pins_nand_rdy),"nand rd" , EBU, xrx200_pins_nand_rd),"spi_di" , SPI, xrx200_pins_spi_di),"spi_do" , SPI, xrx200_pins_spi_do),"spi_clk" , SPI, xrx200_pins_spi_clk),"spi_cs1" , SPI, xrx200_pins_spi_cs1),"spi_cs2" , SPI, xrx200_pins_spi_cs2),"spi_cs3" , SPI, xrx200_pins_spi_cs3),"spi_cs4" , SPI, xrx200_pins_spi_cs4),"spi_cs5" , SPI, xrx200_pins_spi_cs5),"spi_cs6" , SPI, xrx200_pins_spi_cs6),"usif uart_rx" , USIF, xrx200_pins_usif_uart_rx),"usif uart_tx" , USIF, xrx200_pins_usif_uart_tx),"usif uart_rts" , USIF, xrx200_pins_usif_uart_rts),"usif uart_cts" , USIF, xrx200_pins_usif_uart_cts),"usif uart_dtr" , USIF, xrx200_pins_usif_uart_dtr),"usif uart_dsr" , USIF, xrx200_pins_usif_uart_dsr),"usif uart_dcd" , USIF, xrx200_pins_usif_uart_dcd),"usif uart_ri" , USIF, xrx200_pins_usif_uart_ri),"usif spi_di" , USIF, xrx200_pins_usif_spi_di),"usif spi_do" , USIF, xrx200_pins_usif_spi_do),"usif spi_clk" , USIF, xrx200_pins_usif_spi_clk),"usif spi_cs0" , USIF, xrx200_pins_usif_spi_cs0),"usif spi_cs1" , USIF, xrx200_pins_usif_spi_cs1),"usif spi_cs2" , USIF, xrx200_pins_usif_spi_cs2),"stp" , STP, xrx200_pins_stp),"nmi" , NMI, xrx200_pins_nmi),"gpt1" , GPT, xrx200_pins_gpt1),"gpt2" , GPT, xrx200_pins_gpt2),"gpt3" , GPT, xrx200_pins_gpt3),"clkout0" , CGU, xrx200_pins_clkout0),"clkout1" , CGU, xrx200_pins_clkout1),"clkout2" , CGU, xrx200_pins_clkout2),"clkout3" , CGU, xrx200_pins_clkout3),"gnt1" , PCI, xrx200_pins_pci_gnt1),"gnt2" , PCI, xrx200_pins_pci_gnt2),"gnt3" , PCI, xrx200_pins_pci_gnt3),"gnt4" , PCI, xrx200_pins_pci_gnt4),"req1" , PCI, xrx200_pins_pci_req1),"req2" , PCI, xrx200_pins_pci_req2),"req3" , PCI, xrx200_pins_pci_req3),"req4" , PCI, xrx200_pins_pci_req4),"mdio" , MDIO, xrx200_pins_mdio),"dfe led0" , DFE, xrx200_pins_dfe_led0),"dfe led1" , DFE, xrx200_pins_dfe_led1),"gphy0 led0" , GPHY, xrx200_pins_gphy0_led0),"gphy0 led1" , GPHY, xrx200_pins_gphy0_led1),"gphy0 led2" , GPHY, xrx200_pins_gphy0_led2),"gphy1 led0" , GPHY, xrx200_pins_gphy1_led0),"gphy1 led1" , GPHY, xrx200_pins_gphy1_led1),"gphy1 led2" , GPHY, xrx200_pins_gphy1_led2),static const char * const xrx200_pci_grps[] = {"gnt1" , "gnt2" ,"gnt3" , "gnt4" ,"req1" , "req2" ,"req3" , "req4" };static const char * const xrx200_spi_grps[] = {"spi_di" , "spi_do" ,"spi_clk" , "spi_cs1" ,"spi_cs2" , "spi_cs3" ,"spi_cs4" , "spi_cs5" ,"spi_cs6" };static const char * const xrx200_cgu_grps[] = {"clkout0" , "clkout1" ,"clkout2" , "clkout3" };static const char * const xrx200_ebu_grps[] = {"ebu a23" , "ebu a24" ,"ebu a25" , "ebu cs1" ,"ebu wait" , "ebu clk" ,"nand ale" , "nand cs1" ,"nand cle" , "nand rdy" ,"nand rd" };static const char * const xrx200_exin_grps[] = {"exin0" , "exin1" , "exin2" ,"exin3" , "exin4" , "exin5" };static const char * const xrx200_gpt_grps[] = {"gpt1" , "gpt2" , "gpt3" };static const char * const xrx200_usif_grps[] = {"usif uart_rx" , "usif uart_tx" ,"usif uart_rts" , "usif uart_cts" ,"usif uart_dtr" , "usif uart_dsr" ,"usif uart_dcd" , "usif uart_ri" ,"usif spi_di" , "usif spi_do" ,"usif spi_clk" , "usif spi_cs0" ,"usif spi_cs1" , "usif spi_cs2" };static const char * const xrx200_stp_grps[] = {"stp" };static const char * const xrx200_nmi_grps[] = {"nmi" };static const char * const xrx200_mdio_grps[] = {"mdio" };static const char * const xrx200_dfe_grps[] = {"dfe led0" , "dfe led1" };static const char * const xrx200_gphy_grps[] = {"gphy0 led0" , "gphy0 led1" ,"gphy0 led2" , "gphy1 led0" ,"gphy1 led1" , "gphy1 led2" };static const struct ltq_pmx_func xrx200_funcs[] = {"spi" , ARRAY_AND_SIZE(xrx200_spi_grps)},"usif" , ARRAY_AND_SIZE(xrx200_usif_grps)},"cgu" , ARRAY_AND_SIZE(xrx200_cgu_grps)},"exin" , ARRAY_AND_SIZE(xrx200_exin_grps)},"stp" , ARRAY_AND_SIZE(xrx200_stp_grps)},"gpt" , ARRAY_AND_SIZE(xrx200_gpt_grps)},"nmi" , ARRAY_AND_SIZE(xrx200_nmi_grps)},"pci" , ARRAY_AND_SIZE(xrx200_pci_grps)},"ebu" , ARRAY_AND_SIZE(xrx200_ebu_grps)},"mdio" , ARRAY_AND_SIZE(xrx200_mdio_grps)},"dfe" , ARRAY_AND_SIZE(xrx200_dfe_grps)},"gphy" , ARRAY_AND_SIZE(xrx200_gphy_grps)},/* --------- xrx300 related code --------- */ #define XRX300_MAX_PIN 64static const struct ltq_mfp_pin xrx300_mfp[] = {/* pin f0 f1 f2 f3 */ static const unsigned xrx300_exin_pin_map[] = {GPIO0, GPIO1, GPIO16, GPIO10, GPIO9};static const unsigned xrx300_pins_exin0[] = {GPIO0};static const unsigned xrx300_pins_exin1[] = {GPIO1};static const unsigned xrx300_pins_exin2[] = {GPIO16};/* EXIN3 is not available on xrX300 */ static const unsigned xrx300_pins_exin4[] = {GPIO10};static const unsigned xrx300_pins_exin5[] = {GPIO9};static const unsigned xrx300_pins_usif_uart_rx[] = {GPIO11};static const unsigned xrx300_pins_usif_uart_tx[] = {GPIO10};static const unsigned xrx300_pins_usif_spi_di[] = {GPIO11};static const unsigned xrx300_pins_usif_spi_do[] = {GPIO10};static const unsigned xrx300_pins_usif_spi_clk[] = {GPIO19};static const unsigned xrx300_pins_usif_spi_cs0[] = {GPIO14};static const unsigned xrx300_pins_stp[] = {GPIO4, GPIO5, GPIO6};static const unsigned xrx300_pins_mdio[] = {GPIO42, GPIO43};static const unsigned xrx300_pins_dfe_led0[] = {GPIO4};static const unsigned xrx300_pins_dfe_led1[] = {GPIO5};static const unsigned xrx300_pins_ephy0_led0[] = {GPIO5};static const unsigned xrx300_pins_ephy0_led1[] = {GPIO8};static const unsigned xrx300_pins_ephy1_led0[] = {GPIO14};static const unsigned xrx300_pins_ephy1_led1[] = {GPIO19};static const unsigned xrx300_pins_nand_ale[] = {GPIO13};static const unsigned xrx300_pins_nand_cs1[] = {GPIO23};static const unsigned xrx300_pins_nand_cle[] = {GPIO24};static const unsigned xrx300_pins_nand_rdy[] = {GPIO48};static const unsigned xrx300_pins_nand_rd[] = {GPIO49};static const unsigned xrx300_pins_nand_d1[] = {GPIO50};static const unsigned xrx300_pins_nand_d0[] = {GPIO51};static const unsigned xrx300_pins_nand_d2[] = {GPIO52};static const unsigned xrx300_pins_nand_d7[] = {GPIO53};static const unsigned xrx300_pins_nand_d6[] = {GPIO54};static const unsigned xrx300_pins_nand_d5[] = {GPIO55};static const unsigned xrx300_pins_nand_d4[] = {GPIO56};static const unsigned xrx300_pins_nand_d3[] = {GPIO57};static const unsigned xrx300_pins_nand_cs0[] = {GPIO58};static const unsigned xrx300_pins_nand_wr[] = {GPIO59};static const unsigned xrx300_pins_nand_wp[] = {GPIO60};static const unsigned xrx300_pins_nand_se[] = {GPIO61};static const unsigned xrx300_pins_spi_di[] = {GPIO16};static const unsigned xrx300_pins_spi_do[] = {GPIO17};static const unsigned xrx300_pins_spi_clk[] = {GPIO18};static const unsigned xrx300_pins_spi_cs1[] = {GPIO15};/* SPI_CS2 is not available on xrX300 */ /* SPI_CS3 is not available on xrX300 */ static const unsigned xrx300_pins_spi_cs4[] = {GPIO10};/* SPI_CS5 is not available on xrX300 */ static const unsigned xrx300_pins_spi_cs6[] = {GPIO11};/* CLKOUT0 is not available on xrX300 */ /* CLKOUT1 is not available on xrX300 */ static const unsigned xrx300_pins_clkout2[] = {GPIO3};static const struct ltq_pin_group xrx300_grps[] = {"exin0" , EXIN, xrx300_pins_exin0),"exin1" , EXIN, xrx300_pins_exin1),"exin2" , EXIN, xrx300_pins_exin2),"exin4" , EXIN, xrx300_pins_exin4),"exin5" , EXIN, xrx300_pins_exin5),"nand ale" , EBU, xrx300_pins_nand_ale),"nand cs1" , EBU, xrx300_pins_nand_cs1),"nand cle" , EBU, xrx300_pins_nand_cle),"nand rdy" , EBU, xrx300_pins_nand_rdy),"nand rd" , EBU, xrx300_pins_nand_rd),"nand d1" , EBU, xrx300_pins_nand_d1),"nand d0" , EBU, xrx300_pins_nand_d0),"nand d2" , EBU, xrx300_pins_nand_d2),"nand d7" , EBU, xrx300_pins_nand_d7),"nand d6" , EBU, xrx300_pins_nand_d6),"nand d5" , EBU, xrx300_pins_nand_d5),"nand d4" , EBU, xrx300_pins_nand_d4),"nand d3" , EBU, xrx300_pins_nand_d3),"nand cs0" , EBU, xrx300_pins_nand_cs0),"nand wr" , EBU, xrx300_pins_nand_wr),"nand wp" , EBU, xrx300_pins_nand_wp),"nand se" , EBU, xrx300_pins_nand_se),"spi_di" , SPI, xrx300_pins_spi_di),"spi_do" , SPI, xrx300_pins_spi_do),"spi_clk" , SPI, xrx300_pins_spi_clk),"spi_cs1" , SPI, xrx300_pins_spi_cs1),"spi_cs4" , SPI, xrx300_pins_spi_cs4),"spi_cs6" , SPI, xrx300_pins_spi_cs6),"usif uart_rx" , USIF, xrx300_pins_usif_uart_rx),"usif uart_tx" , USIF, xrx300_pins_usif_uart_tx),"usif spi_di" , USIF, xrx300_pins_usif_spi_di),"usif spi_do" , USIF, xrx300_pins_usif_spi_do),"usif spi_clk" , USIF, xrx300_pins_usif_spi_clk),"usif spi_cs0" , USIF, xrx300_pins_usif_spi_cs0),"stp" , STP, xrx300_pins_stp),"clkout2" , CGU, xrx300_pins_clkout2),"mdio" , MDIO, xrx300_pins_mdio),"dfe led0" , DFE, xrx300_pins_dfe_led0),"dfe led1" , DFE, xrx300_pins_dfe_led1),"ephy0 led0" , GPHY, xrx300_pins_ephy0_led0),"ephy0 led1" , GPHY, xrx300_pins_ephy0_led1),"ephy1 led0" , GPHY, xrx300_pins_ephy1_led0),"ephy1 led1" , GPHY, xrx300_pins_ephy1_led1),static const char * const xrx300_spi_grps[] = {"spi_di" , "spi_do" ,"spi_clk" , "spi_cs1" ,"spi_cs4" , "spi_cs6" };static const char * const xrx300_cgu_grps[] = {"clkout2" };static const char * const xrx300_ebu_grps[] = {"nand ale" , "nand cs1" ,"nand cle" , "nand rdy" ,"nand rd" , "nand d1" ,"nand d0" , "nand d2" ,"nand d7" , "nand d6" ,"nand d5" , "nand d4" ,"nand d3" , "nand cs0" ,"nand wr" , "nand wp" ,"nand se" };static const char * const xrx300_exin_grps[] = {"exin0" , "exin1" , "exin2" ,"exin4" , "exin5" };static const char * const xrx300_usif_grps[] = {"usif uart_rx" , "usif uart_tx" ,"usif spi_di" , "usif spi_do" ,"usif spi_clk" , "usif spi_cs0" };static const char * const xrx300_stp_grps[] = {"stp" };static const char * const xrx300_mdio_grps[] = {"mdio" };static const char * const xrx300_dfe_grps[] = {"dfe led0" , "dfe led1" };static const char * const xrx300_gphy_grps[] = {"ephy0 led0" , "ephy0 led1" ,"ephy1 led0" , "ephy1 led1" };static const struct ltq_pmx_func xrx300_funcs[] = {"spi" , ARRAY_AND_SIZE(xrx300_spi_grps)},"usif" , ARRAY_AND_SIZE(xrx300_usif_grps)},"cgu" , ARRAY_AND_SIZE(xrx300_cgu_grps)},"exin" , ARRAY_AND_SIZE(xrx300_exin_grps)},"stp" , ARRAY_AND_SIZE(xrx300_stp_grps)},"ebu" , ARRAY_AND_SIZE(xrx300_ebu_grps)},"mdio" , ARRAY_AND_SIZE(xrx300_mdio_grps)},"dfe" , ARRAY_AND_SIZE(xrx300_dfe_grps)},"ephy" , ARRAY_AND_SIZE(xrx300_gphy_grps)},/* --------- pinconf related code --------- */ static int xway_pinconf_get(struct pinctrl_dev *pctldev,unsigned pin,unsigned long *config)struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);int port = PORT(pin);switch (param) {case LTQ_PINCONF_PARAM_OPEN_DRAIN:if (port == PORT3)else break ;case LTQ_PINCONF_PARAM_PULL:if (port == PORT3)else if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {break ;if (port == PORT3)else if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))else break ;case LTQ_PINCONF_PARAM_OUTPUT:break ;default :"Invalid config param %04x\n" , param);return -ENOTSUPP;return 0;static int xway_pinconf_set(struct pinctrl_dev *pctldev,unsigned pin,unsigned long *configs,unsigned num_configs)struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);enum ltq_pinconf_param param;int arg;int port = PORT(pin);int i;for (i = 0; i < num_configs; i++) {switch (param) {case LTQ_PINCONF_PARAM_OPEN_DRAIN:if (port == PORT3)else if (arg == 0)else break ;case LTQ_PINCONF_PARAM_PULL:if (port == PORT3)else if (arg == 0) {break ;if (port == PORT3)else if (arg == 1)else if (arg == 2)else "Invalid pull value %d\n" , arg);break ;case LTQ_PINCONF_PARAM_OUTPUT:if (arg == 0)else break ;default :"Invalid config param %04x\n" , param);return -ENOTSUPP;/* for each config */ return 0;static int xway_pinconf_group_set(struct pinctrl_dev *pctldev,unsigned int selector,unsigned long *configs,unsigned int num_configs)struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);int i, ret = 0;for (i = 0; i < info->grps[selector].npins && !ret; i++)return ret;static const struct pinconf_ops xway_pinconf_ops = {static struct pinctrl_desc xway_pctrl_desc = {static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,int pin, int mux)struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);int port = PORT(pin);if (port == PORT3)if (mux & MUX_ALT0)else if (mux & MUX_ALT1)else return 0;static const struct ltq_cfg_param xway_cfg_params[] = {"lantiq,pull" , LTQ_PINCONF_PARAM_PULL},"lantiq,open-drain" , LTQ_PINCONF_PARAM_OPEN_DRAIN},"lantiq,output" , LTQ_PINCONF_PARAM_OUTPUT},static struct ltq_pinmux_info xway_info = {/* --------- gpio_chip related code --------- */ static int xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);if (val)else return 0;static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);return !!gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);return 0;static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);if (PORT(pin) == PORT3)else return xway_gpio_set(chip, pin, val);/* * gpiolib gpiod_to_irq callback function. * Returns the mapped IRQ (external interrupt) number for a given GPIO pin. static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);int i;for (i = 0; i < info->num_exin; i++)if (info->exin[i] == offset)return ltq_eiu_get_irq(i);return -1;static struct gpio_chip xway_chip = {"gpio-xway" ,/* --------- register the pinctrl layer --------- */ struct pinctrl_xway_soc {int pin_count;const struct ltq_mfp_pin *mfp;const struct ltq_pin_group *grps;unsigned int num_grps;const struct ltq_pmx_func *funcs;unsigned int num_funcs;const unsigned *exin;unsigned int num_exin;/* XWAY AMAZON Family */ static struct pinctrl_xway_soc ase_pinctrl = {/* XWAY DANUBE Family */ static struct pinctrl_xway_soc danube_pinctrl = {/* XWAY xRX100 Family */ static struct pinctrl_xway_soc xrx100_pinctrl = {/* XWAY xRX200 Family */ static struct pinctrl_xway_soc xrx200_pinctrl = {/* XWAY xRX300 Family */ static struct pinctrl_xway_soc xrx300_pinctrl = {static struct pinctrl_gpio_range xway_gpio_range = {"XWAY GPIO" ,static const struct of_device_id xway_match[] = {"lantiq,ase-pinctrl" , .data = &ase_pinctrl},"lantiq,danube-pinctrl" , .data = &danube_pinctrl},"lantiq,xrx100-pinctrl" , .data = &xrx100_pinctrl},"lantiq,xrx200-pinctrl" , .data = &xrx200_pinctrl},"lantiq,xrx300-pinctrl" , .data = &xrx300_pinctrl},static int pinmux_xway_probe(struct platform_device *pdev)const struct pinctrl_xway_soc *xway_soc;int ret, i;/* get and remap our register range */ if (IS_ERR(xway_info.membase[0]))return PTR_ERR(xway_info.membase[0]);if (!xway_soc)/* find out how many pads we have */ /* load our pad descriptors */ sizeof (struct pinctrl_pin_desc),if (!xway_info.pads)return -ENOMEM;for (i = 0; i < xway_chip.ngpio; i++) {char *name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "io%d" , i);if (!name)return -ENOMEM;/* setup the data needed by pinctrl */ /* register with the generic lantiq layer */ if (ret) {"Failed to register pinctrl driver\n" );return ret;/* register the gpio chip */ if (ret) {"Failed to register gpio chip\n" );return ret;/* * For DeviceTree-supported systems, the gpio core checks the * pinctrl's device node for the "gpio-ranges" property. * If it is present, it takes care of adding the pin ranges * for the driver. In this case the driver can skip ahead. * * In order to remain compatible with older, existing DeviceTree * files which don't set the "gpio-ranges" property or systems that * utilize ACPI the driver has to call gpiochip_add_pin_range(). if (!of_property_present(pdev->dev.of_node, "gpio-ranges" )) {/* finish with registering the gpio range in pinctrl */ "Init done\n" );return 0;static struct platform_driver pinmux_xway_driver = {"pinctrl-xway" ,static int __init pinmux_xway_init(void )return platform_driver_register(&pinmux_xway_driver);
Messung V0.5 C=96 H=98 G=96
¤ Dauer der Verarbeitung: 0.24 Sekunden
(vorverarbeitet)
¤ *© Formatika GbR, Deutschland
