// SPDX-License-Identifier: GPL-2.0 /* * Renesas RZ/G2L Pin Control and GPIO driver core * * Copyright (C) 2021 Renesas Electronics Corporation. #include <linux/bitfield.h>#include <linux/bitops.h>#include <linux/clk.h>#include <linux/gpio/driver.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/module.h>#include <linux/mutex.h>#include <linux/of.h>#include <linux/of_irq.h>#include <linux/platform_device.h>#include <linux/property.h>#include <linux/seq_file.h>#include <linux/spinlock.h>#include <linux/pinctrl/consumer.h>#include <linux/pinctrl/pinconf-generic.h>#include <linux/pinctrl/pinconf.h>#include <linux/pinctrl/pinctrl.h>#include <linux/pinctrl/pinmux.h>#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>#include "../core.h" #include "../pinconf.h" #include "../pinmux.h" #define DRV_NAME "pinctrl-rzg2l" /* * Use 16 lower bits [15:0] for pin identifier * Use 16 higher bits [31:16] for pin mux function #define MUX_PIN_ID_MASK GENMASK(15, 0)#define MUX_FUNC_MASK GENMASK(31, 16)/* PIN capabilities */ #define PIN_CFG_IOLH_A BIT(0)#define PIN_CFG_IOLH_B BIT(1)#define PIN_CFG_SR BIT(2)#define PIN_CFG_IEN BIT(3)#define PIN_CFG_PUPD BIT(4)#define PIN_CFG_IO_VMC_SD0 BIT(5)#define PIN_CFG_IO_VMC_SD1 BIT(6)#define PIN_CFG_IO_VMC_QSPI BIT(7)#define PIN_CFG_IO_VMC_ETH0 BIT(8)#define PIN_CFG_IO_VMC_ETH1 BIT(9)#define PIN_CFG_NF BIT(10) /* Digital noise filter */ #define PIN_CFG_IOLH_C BIT(11)#define PIN_CFG_SOFT_PS BIT(12)#define PIN_CFG_OEN BIT(13)#define PIN_CFG_NOGPIO_INT BIT(14)#define PIN_CFG_NOD BIT(15) /* N-ch Open Drain */ #define PIN_CFG_SMT BIT(16) /* Schmitt-trigger input control */ #define PIN_CFG_ELC BIT(17)#define PIN_CFG_IOLH_RZV2H BIT(18)#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ #define RZG2L_VARIABLE_CFG BIT_ULL(62) /* Variable cfg for port pins */ #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \## group | \#define RZG2L_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(A) | \#define RZG3S_MPXED_PIN_FUNCS(group) (RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \#define RZV2H_MPXED_PIN_FUNCS (RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) | \#define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | PIN_CFG_NF)#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(61, 54)#define PIN_CFG_PIN_REG_MASK GENMASK_ULL(53, 46)#define PIN_CFG_MASK GENMASK_ULL(31, 0)/* * m indicates the bitmap of supported pins, a is the register index * and f is pin configuration capabilities supported. #define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \#define RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a) \/* * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))#define RZG2L_GPIO_PORT_PACK_VARIABLE(n, a) (RZG2L_VARIABLE_CFG | \#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56)#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53)/* * p is the register index while referencing to SR/IEN/IOLH/FILxx * registers, b is the register bits (b * 8) and f is the pin * configuration capabilities supported. #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \#define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \#define VARIABLE_PIN_CFG_PIN_MASK GENMASK_ULL(54, 52)#define VARIABLE_PIN_CFG_PORT_MASK GENMASK_ULL(51, 47)#define RZG2L_VARIABLE_PIN_CFG_PACK(port, pin, cfg) \#define P(off) (0x0000 + (off))#define PM(off) (0x0100 + (off) * 2)#define PMC(off) (0x0200 + (off))#define PFC(off) (0x0400 + (off) * 4)#define PIN(off) (0x0800 + (off))#define IOLH(off) (0x1000 + (off) * 8)#define SR(off) (0x1400 + (off) * 8)#define IEN(off) (0x1800 + (off) * 8)#define PUPD(off) (0x1C00 + (off) * 8)#define ISEL(off) (0x2C00 + (off) * 8)#define NOD(off) (0x3000 + (off) * 8)#define SMT(off) (0x3400 + (off) * 8)#define SD_CH(off, ch) ((off) + (ch) * 4)#define ETH_POC(off, ch) ((off) + (ch) * 4)#define QSPI (0x3008)#define ETH_MODE (0x3018)#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ #define PWPR_B0WI BIT(7) /* Bit Write Disable */ #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ #define PWPR_REGWE_A BIT(6) /* PFC and PMC Register Write Enable on RZ/V2H(P) */ #define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */ #define PM_MASK 0x03#define PFC_MASK 0x0f#define IEN_MASK 0x01#define IOLH_MASK 0x03#define SR_MASK 0x01#define PUPD_MASK 0x03#define NOD_MASK 0x01#define SMT_MASK 0x01#define PM_INPUT 0x1#define PM_OUTPUT 0x2#define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT)#define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT)#define RZG2L_TINT_MAX_INTERRUPT 32#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))/* Custom pinconf parameters */ #define RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE (PIN_CONFIG_END + 1)static const struct pinconf_generic_params renesas_rzv2h_custom_bindings[] = {"renesas,output-impedance" , RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE, 1 },#ifdef CONFIG_DEBUG_FSstatic const struct pin_config_item renesas_rzv2h_conf_items[] = {"output-impedance" , "x" , true ),#endif /* Read/write 8 bits register */ #define RZG2L_PCTRL_REG_ACCESS8(_read, _addr, _val) \do { \if (_read) \else \while (0)/* Read/write 16 bits register */ #define RZG2L_PCTRL_REG_ACCESS16(_read, _addr, _val) \do { \if (_read) \else \while (0)/* Read/write 32 bits register */ #define RZG2L_PCTRL_REG_ACCESS32(_read, _addr, _val) \do { \if (_read) \else \while (0)/** * struct rzg2l_register_offsets - specific register offsets * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset * @eth_poc: ETH_POC register offset struct rzg2l_register_offsets {/** * enum rzg2l_iolh_index - starting indices in IOLH specific arrays * @RZG2L_IOLH_IDX_1V8: starting index for 1V8 power source * @RZG2L_IOLH_IDX_2V5: starting index for 2V5 power source * @RZG2L_IOLH_IDX_3V3: starting index for 3V3 power source * @RZG2L_IOLH_IDX_MAX: maximum index enum rzg2l_iolh_index {/* Maximum number of driver strength entries per power source. */ #define RZG2L_IOLH_MAX_DS_ENTRIES (4)/** * struct rzg2l_hwcfg - hardware configuration data structure * @regs: hardware specific register offsets * @iolh_groupa_ua: IOLH group A uA specific values * @iolh_groupb_ua: IOLH group B uA specific values * @iolh_groupc_ua: IOLH group C uA specific values * @iolh_groupb_oi: IOLH group B output impedance specific values * @tint_start_index: the start index for the TINT interrupts * @drive_strength_ua: drive strength in uA is supported (otherwise mA is supported) * @func_base: base number for port function (see register PFC) * @oen_max_pin: the maximum pin number supporting output enable * @oen_max_port: the maximum port number supporting output enable struct rzg2l_hwcfg {const struct rzg2l_register_offsets regs;bool drive_strength_ua;struct rzg2l_dedicated_configs {const char *name;struct rzg2l_pinctrl;struct rzg2l_pinctrl_data {const char * const *port_pins;const u64 *port_pin_configs;unsigned int n_ports;const struct rzg2l_dedicated_configs *dedicated_pins;unsigned int n_port_pins;unsigned int n_dedicated_pins;const struct rzg2l_hwcfg *hwcfg;const u64 *variable_pin_cfg;unsigned int n_variable_pin_cfg;unsigned int num_custom_params;const struct pinconf_generic_params *custom_params;#ifdef CONFIG_DEBUG_FSconst struct pin_config_item *custom_conf_items;#endif void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock);void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset);struct rzg2l_pinctrl *pctrl, unsigned int _pin);int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen);int (*hw_to_bias_param)(unsigned int val);int (*bias_param_to_hw)(enum pin_config_param param);/** * struct rzg2l_pinctrl_pin_settings - pin data * @power_source: power source * @drive_strength_ua: drive strength (in micro amps) struct rzg2l_pinctrl_pin_settings {/** * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) * @p: P registers cache * @pm: PM registers cache * @pmc: PMC registers cache * @pfc: PFC registers cache * @iolh: IOLH registers cache * @pupd: PUPD registers cache * @ien: IEN registers cache * @smt: SMT registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache * @eth_mode: ETH_MODE register cache * @qspi: QSPI registers cache struct rzg2l_pinctrl_reg_cache {struct rzg2l_pinctrl {struct pinctrl_dev *pctl;struct pinctrl_desc desc;struct pinctrl_pin_desc *pins;const struct rzg2l_pinctrl_data *data;void __iomem *base;struct device *dev;struct clk *clk;struct gpio_chip gpio_chip;struct pinctrl_gpio_range gpio_range;/* protect tint_slot bitmap */ unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT];/* lock read/write registers */ struct mutex mutex; /* serialize adding groups and functions */ struct rzg2l_pinctrl_pin_settings *settings;struct rzg2l_pinctrl_reg_cache *cache;struct rzg2l_pinctrl_reg_cache *dedicated_cache;static const u16 available_ps[] = { 1800, 2500, 3300 };static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,unsigned int port,unsigned int i;for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {if (FIELD_GET(VARIABLE_PIN_CFG_PORT_MASK, cfg) == port &&return (pincfg & ~RZG2L_VARIABLE_CFG) | FIELD_GET(PIN_CFG_MASK, cfg);return 0;static const u64 r9a09g047_variable_pin_cfg[] = {static const u64 r9a09g057_variable_pin_cfg[] = {#ifdef CONFIG_RISCVstatic const u64 r9a07g043f_variable_pin_cfg[] = {#endif static void rzg2l_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)static void rzv2h_pmc_writeb(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset)const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;static int rzg2l_validate_pin(struct rzg2l_pinctrl *pctrl,if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)return -EINVAL;if (off != RZG2L_PIN_CFG_TO_PORT_OFFSET(data))return -EINVAL;return 0;static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,unsigned long flags;/* Set pin to 'Non-use (Hi-Z input protection)' */ false );/* Temporarily switch to GPIO mode with PMC register */ /* Select Pin function mode with PFC register */ /* Switch to Peripheral pin function with PMC register */ true );static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev,unsigned int func_selector,unsigned int group_selector)struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;struct function_desc *func;unsigned int i, *psel_val;struct group_desc *group;const unsigned int *pins;int ret;if (!func)return -EINVAL;if (!group)return -EINVAL;for (i = 0; i < group->grp.npins; i++) {if (ret)return ret;"port:%u pin: %u off:%x PSEL:%u\n" ,return 0;static int rzg2l_map_add_config(struct pinctrl_map *map,const char *group_or_pin,enum pinctrl_map_type type,unsigned long *configs,unsigned int num_configs)unsigned long *cfgs;sizeof (*cfgs), GFP_KERNEL);if (!cfgs)return -ENOMEM;return 0;static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,struct device_node *np,struct device_node *parent,struct pinctrl_map **map,unsigned int *num_maps,unsigned int *index)struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);struct pinctrl_map *maps = *map;unsigned int nmaps = *num_maps;unsigned long *configs = NULL;unsigned int *pins, *psel_val;unsigned int num_pinmux = 0;unsigned int idx = *index;unsigned int num_pins, i;unsigned int num_configs;struct property *pinmux;struct property *prop;int ret, gsel, fsel;const char **pin_fn;const char *name;const char *pin;"pinmux" , NULL);if (pinmux)sizeof (u32);"pins" );if (ret == -EINVAL) {else if (ret < 0) {"Invalid pins list in DT\n" );return ret;else {if (!num_pinmux && !num_pins)return 0;if (num_pinmux && num_pins) {"DT node must contain either a pinmux or pins and not both\n" );return -EINVAL;if (ret < 0)return ret;if (num_pins && !num_configs) {"DT node must contain a config\n" );goto done;if (num_pinmux) {if (num_configs)if (num_pins)sizeof (*maps), GFP_KERNEL);if (!maps) {goto done;if (num_pins) {"pins" , prop, pin) {if (ret < 0)goto done;goto done;sizeof (*pins), GFP_KERNEL);sizeof (*psel_val),sizeof (*pin_fn), GFP_KERNEL);if (!pins || !psel_val || !pin_fn) {goto done;/* Collect pin locations and mux settings from DT properties */ for (i = 0; i < num_pinmux; ++i) {"pinmux" , i, &value);if (ret)goto done;if (parent) {"%pOFn.%pOFn" ,if (!name) {goto done;else {if (num_configs) {if (ret < 0)goto done;/* Register a single pin group listing all the pins we read from DT */ if (gsel < 0) {goto unlock;/* * Register a single group function where the 'data' is an array PSEL * register values read from DT. if (fsel < 0) {goto remove_group;"Parsed %pOF with %d pins\n" , np, num_pinmux);goto done;return ret;static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev,struct pinctrl_map *map,unsigned int num_maps)unsigned int i;if (!map)return ;for (i = 0; i < num_maps; ++i) {if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev,struct device_node *np,struct pinctrl_map **map,unsigned int *num_maps)struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);unsigned int index;int ret;if (ret < 0)goto done;if (*num_maps == 0) {if (ret < 0)goto done;if (*num_maps)return 0;"no mapping found in node %pOF\n" , np);return ret;static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,void __iomem *addr = pctrl->base + offset;/* handle _L/_H for 32-bit register read/write */ if (bit >= 4) {return (readl(addr) >> (bit * 8)) & mask;static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset,void __iomem *addr = pctrl->base + offset;unsigned long flags;/* handle _L/_H for 32-bit register read/write */ if (bit >= 4) {static int rzg2l_caps_to_pwr_reg(const struct rzg2l_register_offsets *regs, u32 caps)if (caps & PIN_CFG_IO_VMC_SD0)return SD_CH(regs->sd_ch, 0);if (caps & PIN_CFG_IO_VMC_SD1)return SD_CH(regs->sd_ch, 1);if (caps & PIN_CFG_IO_VMC_ETH0)return ETH_POC(regs->eth_poc, 0);if (caps & PIN_CFG_IO_VMC_ETH1)return ETH_POC(regs->eth_poc, 1);if (caps & PIN_CFG_IO_VMC_QSPI)return QSPI;return -EINVAL;static int rzg2l_get_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps)const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;const struct rzg2l_register_offsets *regs = &hwcfg->regs;int pwr_reg;if (caps & PIN_CFG_SOFT_PS)return pctrl->settings[pin].power_source;if (pwr_reg < 0)return pwr_reg;switch (val) {case PVDD_1800:return 1800;case PVDD_2500:return 2500;case PVDD_3300:return 3300;default :/* Should not happen. */ return -EINVAL;static int rzg2l_set_power_source(struct rzg2l_pinctrl *pctrl, u32 pin, u32 caps, u32 ps)const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;const struct rzg2l_register_offsets *regs = &hwcfg->regs;int pwr_reg;if (caps & PIN_CFG_SOFT_PS) {return 0;switch (ps) {case 1800:break ;case 2500:if (!(caps & (PIN_CFG_IO_VMC_ETH0 | PIN_CFG_IO_VMC_ETH1)))return -EINVAL;break ;case 3300:break ;default :return -EINVAL;if (pwr_reg < 0)return pwr_reg;return 0;static bool rzg2l_ps_is_supported(u16 ps)unsigned int i;for (i = 0; i < ARRAY_SIZE(available_ps); i++) {if (available_ps[i] == ps)return true ;return false ;static enum rzg2l_iolh_index rzg2l_ps_to_iolh_idx(u16 ps)unsigned int i;for (i = 0; i < ARRAY_SIZE(available_ps); i++) {if (available_ps[i] == ps)break ;/* * We multiply with RZG2L_IOLH_MAX_DS_ENTRIES as we have * RZG2L_IOLH_MAX_DS_ENTRIES DS values per power source return i * RZG2L_IOLH_MAX_DS_ENTRIES;static u16 rzg2l_iolh_val_to_ua(const struct rzg2l_hwcfg *hwcfg, u32 caps, u8 val)if (caps & PIN_CFG_IOLH_A)return hwcfg->iolh_groupa_ua[val];if (caps & PIN_CFG_IOLH_B)return hwcfg->iolh_groupb_ua[val];if (caps & PIN_CFG_IOLH_C)return hwcfg->iolh_groupc_ua[val];/* Should not happen. */ return 0;static int rzg2l_iolh_ua_to_val(const struct rzg2l_hwcfg *hwcfg, u32 caps,enum rzg2l_iolh_index ps_index, u16 ua)const u16 *array = NULL;unsigned int i;if (caps & PIN_CFG_IOLH_A)if (caps & PIN_CFG_IOLH_B)if (caps & PIN_CFG_IOLH_C)if (!array)return -EINVAL;for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {if (array[i] == ua)return i;return -EINVAL;static bool rzg2l_ds_is_supported(struct rzg2l_pinctrl *pctrl, u32 caps,enum rzg2l_iolh_index iolh_idx,const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;const u16 *array = NULL;unsigned int i;if (caps & PIN_CFG_IOLH_A)if (caps & PIN_CFG_IOLH_B)if (caps & PIN_CFG_IOLH_C)/* Should not happen. */ if (!array)return false ;if (!array[iolh_idx])return false ;for (i = 0; i < RZG2L_IOLH_MAX_DS_ENTRIES; i++) {if (array[iolh_idx + i] == ds)return true ;return false ;static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)if (pin > pctrl->data->hwcfg->oen_max_pin)return -EINVAL;/* * We can determine which Ethernet interface we're dealing with from * the caps. if (caps & PIN_CFG_IO_VMC_ETH0)return 0;if (caps & PIN_CFG_IO_VMC_ETH1)return 1;return -EINVAL;static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin)int bit;if (bit < 0)return 0;return !(readb(pctrl->base + ETH_MODE) & BIT(bit));static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)unsigned long flags;int bit;if (bit < 0)return bit;if (oen)else return 0;static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)if (*pin_data & RZG2L_SINGLE_PIN)return -EINVAL;if (pin > pctrl->data->hwcfg->oen_max_pin)return -EINVAL;if (port == pctrl->data->hwcfg->oen_max_port)return bit;static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)int bit;if (bit < 0)return 0;return !(readb(pctrl->base + ETH_MODE) & BIT(bit));static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)unsigned long flags;int bit;if (bit < 0)return bit;if (oen)else return 0;static int rzg2l_hw_to_bias_param(unsigned int bias)switch (bias) {case 0:return PIN_CONFIG_BIAS_DISABLE;case 1:return PIN_CONFIG_BIAS_PULL_UP;case 2:return PIN_CONFIG_BIAS_PULL_DOWN;default :break ;return -EINVAL;static int rzg2l_bias_param_to_hw(enum pin_config_param param)switch (param) {case PIN_CONFIG_BIAS_DISABLE:return 0;case PIN_CONFIG_BIAS_PULL_UP:return 1;case PIN_CONFIG_BIAS_PULL_DOWN:return 2;default :break ;return -EINVAL;static int rzv2h_hw_to_bias_param(unsigned int bias)switch (bias) {case 0:case 1:return PIN_CONFIG_BIAS_DISABLE;case 2:return PIN_CONFIG_BIAS_PULL_DOWN;case 3:return PIN_CONFIG_BIAS_PULL_UP;default :break ;return -EINVAL;static int rzv2h_bias_param_to_hw(enum pin_config_param param)switch (param) {case PIN_CONFIG_BIAS_DISABLE:return 0;case PIN_CONFIG_BIAS_PULL_DOWN:return 2;case PIN_CONFIG_BIAS_PULL_UP:return 3;default :break ;return -EINVAL;static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _pin)static const char * const pin_names[] = { "ET0_TXC_TXCLK" , "ET1_TXC_TXCLK" ,"XSPI0_RESET0N" , "XSPI0_CS0N" ,"XSPI0_CKN" , "XSPI0_CKP" };const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[_pin];unsigned int i;for (i = 0; i < ARRAY_SIZE(pin_names); i++) {if (!strcmp(pin_desc->name, pin_names[i]))return i;/* Should not happen. */ return 0;static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin)return !(readb(pctrl->base + PFC_OEN) & BIT(bit));static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen)const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;const struct rzg2l_register_offsets *regs = &hwcfg->regs;unsigned long flags;if (oen)else return 0;static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,unsigned int _pin,unsigned long *config)struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];unsigned int arg = 0;int ret;if (!pin_data)return -EINVAL;if (*pin_data & RZG2L_SINGLE_PIN) {else {if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))return -EINVAL;switch (param) {case PIN_CONFIG_INPUT_ENABLE:if (!(cfg & PIN_CFG_IEN))return -EINVAL;if (!arg)return -EINVAL;break ;case PIN_CONFIG_OUTPUT_ENABLE:if (!(cfg & PIN_CFG_OEN))return -EINVAL;if (!pctrl->data->oen_read)return -EOPNOTSUPP;if (!arg)return -EINVAL;break ;case PIN_CONFIG_POWER_SOURCE:if (ret < 0)return ret;break ;case PIN_CONFIG_SLEW_RATE:if (!(cfg & PIN_CFG_SR))return -EINVAL;break ;case PIN_CONFIG_BIAS_DISABLE:case PIN_CONFIG_BIAS_PULL_UP:case PIN_CONFIG_BIAS_PULL_DOWN:if (!(cfg & PIN_CFG_PUPD))return -EINVAL;if (ret < 0)return ret;if (ret != param)return -EINVAL;/* for PIN_CONFIG_BIAS_PULL_UP/DOWN when enabled we just return 1 */ break ;case PIN_CONFIG_DRIVE_STRENGTH: {unsigned int index;if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)return -EINVAL;/* * Drive strenght mA is supported only by group A and only * for 3V3 port source. break ;case PIN_CONFIG_DRIVE_STRENGTH_UA: {enum rzg2l_iolh_index iolh_idx;if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||return -EINVAL;if (ret < 0)return ret;break ;case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: {unsigned int index;if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])return -EINVAL;break ;case PIN_CONFIG_DRIVE_OPEN_DRAIN:case PIN_CONFIG_DRIVE_PUSH_PULL:if (!(cfg & PIN_CFG_NOD))return -EINVAL;if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL)return -EINVAL;if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN)return -EINVAL;break ;case PIN_CONFIG_INPUT_SCHMITT_ENABLE:if (!(cfg & PIN_CFG_SMT))return -EINVAL;if (!arg)return -EINVAL;break ;case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:if (!(cfg & PIN_CFG_IOLH_RZV2H))return -EINVAL;break ;default :return -ENOTSUPP;return 0;static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,unsigned int _pin,unsigned long *_configs,unsigned int num_configs)struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin];unsigned int i, arg, index;int ret;if (!pin_data)return -EINVAL;if (*pin_data & RZG2L_SINGLE_PIN) {else {if (rzg2l_validate_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit))return -EINVAL;for (i = 0; i < num_configs; i++) {switch (param) {case PIN_CONFIG_INPUT_ENABLE:if (!(cfg & PIN_CFG_IEN))return -EINVAL;break ;case PIN_CONFIG_OUTPUT_ENABLE:if (!(cfg & PIN_CFG_OEN))return -EINVAL;if (!pctrl->data->oen_write)return -EOPNOTSUPP;if (ret)return ret;break ;case PIN_CONFIG_POWER_SOURCE:break ;case PIN_CONFIG_SLEW_RATE:if (!(cfg & PIN_CFG_SR) || arg > 1)return -EINVAL;break ;case PIN_CONFIG_BIAS_DISABLE:case PIN_CONFIG_BIAS_PULL_UP:case PIN_CONFIG_BIAS_PULL_DOWN:if (!(cfg & PIN_CFG_PUPD))return -EINVAL;if (ret < 0)return ret;break ;case PIN_CONFIG_DRIVE_STRENGTH:if (!(cfg & PIN_CFG_IOLH_A) || hwcfg->drive_strength_ua)return -EINVAL;for (index = RZG2L_IOLH_IDX_3V3;if (arg == (hwcfg->iolh_groupa_ua[index] / 1000))break ;if (index == (RZG2L_IOLH_IDX_3V3 + RZG2L_IOLH_MAX_DS_ENTRIES))return -EINVAL;break ;case PIN_CONFIG_DRIVE_STRENGTH_UA:if (!(cfg & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C)) ||return -EINVAL;break ;case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS:if (!(cfg & PIN_CFG_IOLH_B) || !hwcfg->iolh_groupb_oi[0])return -EINVAL;for (index = 0; index < ARRAY_SIZE(hwcfg->iolh_groupb_oi); index++) {if (arg == hwcfg->iolh_groupb_oi[index])break ;if (index == ARRAY_SIZE(hwcfg->iolh_groupb_oi))return -EINVAL;break ;case PIN_CONFIG_DRIVE_OPEN_DRAIN:case PIN_CONFIG_DRIVE_PUSH_PULL:if (!(cfg & PIN_CFG_NOD))return -EINVAL;break ;case PIN_CONFIG_INPUT_SCHMITT_ENABLE:if (!(cfg & PIN_CFG_SMT))return -EINVAL;break ;case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:if (!(cfg & PIN_CFG_IOLH_RZV2H))return -EINVAL;if (arg > 3)return -EINVAL;break ;default :return -EOPNOTSUPP;/* Apply power source. */ if (settings.power_source != pctrl->settings[_pin].power_source) {if (!ret)return -EINVAL;/* Apply power source. */ if (ret)return ret;/* Apply drive strength. */ if (settings.drive_strength_ua != pctrl->settings[_pin].drive_strength_ua) {enum rzg2l_iolh_index iolh_idx;int val;if (!ret)return -EINVAL;/* Get register value for this PS/DS tuple. */ if (val < 0)return val;/* Apply drive strength. */ return 0;static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,unsigned int group,unsigned long *configs,unsigned int num_configs)const unsigned int *pins;unsigned int i, npins;int ret;if (ret)return ret;for (i = 0; i < npins; i++) {if (ret)return ret;return 0;static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,unsigned int group,unsigned long *config)const unsigned int *pins;unsigned int i, npins, prev_config = 0;int ret;if (ret)return ret;for (i = 0; i < npins; i++) {if (ret)return ret;/* Check config matching between to pin */ if (i && prev_config != *config)return -EOPNOTSUPP;return 0;static const struct pinctrl_ops rzg2l_pinctrl_pctlops = {static const struct pinmux_ops rzg2l_pinctrl_pmxops = {true ,static const struct pinconf_ops rzg2l_pinctrl_confops = {true ,static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset)struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];unsigned long flags;int ret;if (ret)return ret;if (ret)return ret;/* Select GPIO mode in PMC Register */ return 0;static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset,bool output)const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];unsigned long flags;static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];if (!(readb(pctrl->base + PMC(off)) & BIT(bit))) {if (reg16 == PM_OUTPUT)return GPIO_LINE_DIRECTION_OUT;return GPIO_LINE_DIRECTION_IN;static int rzg2l_gpio_direction_input(struct gpio_chip *chip,unsigned int offset)struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);false );return 0;static int rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset,int value)struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];unsigned long flags;if (value)else return 0;static int rzg2l_gpio_direction_output(struct gpio_chip *chip,unsigned int offset, int value)struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);true );return 0;static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset)struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip);const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];if (reg16 == PM_INPUT)return !!(readb(pctrl->base + PIN(off)) & BIT(bit));else if (reg16 == PM_OUTPUT)return !!(readb(pctrl->base + P(off)) & BIT(bit));else return -EINVAL;static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset)unsigned int virq;if (virq)/* * Set the GPIO as an input to ensure that the next GPIO request won't * drive the GPIO pin as an output. static const char * const rzg2l_gpio_names[] = {"P0_0" , "P0_1" , "P0_2" , "P0_3" , "P0_4" , "P0_5" , "P0_6" , "P0_7" ,"P1_0" , "P1_1" , "P1_2" , "P1_3" , "P1_4" , "P1_5" , "P1_6" , "P1_7" ,"P2_0" , "P2_1" , "P2_2" , "P2_3" , "P2_4" , "P2_5" , "P2_6" , "P2_7" ,"P3_0" , "P3_1" , "P3_2" , "P3_3" , "P3_4" , "P3_5" , "P3_6" , "P3_7" ,"P4_0" , "P4_1" , "P4_2" , "P4_3" , "P4_4" , "P4_5" , "P4_6" , "P4_7" ,"P5_0" , "P5_1" , "P5_2" , "P5_3" , "P5_4" , "P5_5" , "P5_6" , "P5_7" ,"P6_0" , "P6_1" , "P6_2" , "P6_3" , "P6_4" , "P6_5" , "P6_6" , "P6_7" ,"P7_0" , "P7_1" , "P7_2" , "P7_3" , "P7_4" , "P7_5" , "P7_6" , "P7_7" ,"P8_0" , "P8_1" , "P8_2" , "P8_3" , "P8_4" , "P8_5" , "P8_6" , "P8_7" ,"P9_0" , "P9_1" , "P9_2" , "P9_3" , "P9_4" , "P9_5" , "P9_6" , "P9_7" ,"P10_0" , "P10_1" , "P10_2" , "P10_3" , "P10_4" , "P10_5" , "P10_6" , "P10_7" ,"P11_0" , "P11_1" , "P11_2" , "P11_3" , "P11_4" , "P11_5" , "P11_6" , "P11_7" ,"P12_0" , "P12_1" , "P12_2" , "P12_3" , "P12_4" , "P12_5" , "P12_6" , "P12_7" ,"P13_0" , "P13_1" , "P13_2" , "P13_3" , "P13_4" , "P13_5" , "P13_6" , "P13_7" ,"P14_0" , "P14_1" , "P14_2" , "P14_3" , "P14_4" , "P14_5" , "P14_6" , "P14_7" ,"P15_0" , "P15_1" , "P15_2" , "P15_3" , "P15_4" , "P15_5" , "P15_6" , "P15_7" ,"P16_0" , "P16_1" , "P16_2" , "P16_3" , "P16_4" , "P16_5" , "P16_6" , "P16_7" ,"P17_0" , "P17_1" , "P17_2" , "P17_3" , "P17_4" , "P17_5" , "P17_6" , "P17_7" ,"P18_0" , "P18_1" , "P18_2" , "P18_3" , "P18_4" , "P18_5" , "P18_6" , "P18_7" ,"P19_0" , "P19_1" , "P19_2" , "P19_3" , "P19_4" , "P19_5" , "P19_6" , "P19_7" ,"P20_0" , "P20_1" , "P20_2" , "P20_3" , "P20_4" , "P20_5" , "P20_6" , "P20_7" ,"P21_0" , "P21_1" , "P21_2" , "P21_3" , "P21_4" , "P21_5" , "P21_6" , "P21_7" ,"P22_0" , "P22_1" , "P22_2" , "P22_3" , "P22_4" , "P22_5" , "P22_6" , "P22_7" ,"P23_0" , "P23_1" , "P23_2" , "P23_3" , "P23_4" , "P23_5" , "P23_6" , "P23_7" ,"P24_0" , "P24_1" , "P24_2" , "P24_3" , "P24_4" , "P24_5" , "P24_6" , "P24_7" ,"P25_0" , "P25_1" , "P25_2" , "P25_3" , "P25_4" , "P25_5" , "P25_6" , "P25_7" ,"P26_0" , "P26_1" , "P26_2" , "P26_3" , "P26_4" , "P26_5" , "P26_6" , "P26_7" ,"P27_0" , "P27_1" , "P27_2" , "P27_3" , "P27_4" , "P27_5" , "P27_6" , "P27_7" ,"P28_0" , "P28_1" , "P28_2" , "P28_3" , "P28_4" , "P28_5" , "P28_6" , "P28_7" ,"P29_0" , "P29_1" , "P29_2" , "P29_3" , "P29_4" , "P29_5" , "P29_6" , "P29_7" ,"P30_0" , "P30_1" , "P30_2" , "P30_3" , "P30_4" , "P30_5" , "P30_6" , "P30_7" ,"P31_0" , "P31_1" , "P31_2" , "P31_3" , "P31_4" , "P31_5" , "P31_6" , "P31_7" ,"P32_0" , "P32_1" , "P32_2" , "P32_3" , "P32_4" , "P32_5" , "P32_6" , "P32_7" ,"P33_0" , "P33_1" , "P33_2" , "P33_3" , "P33_4" , "P33_5" , "P33_6" , "P33_7" ,"P34_0" , "P34_1" , "P34_2" , "P34_3" , "P34_4" , "P34_5" , "P34_6" , "P34_7" ,"P35_0" , "P35_1" , "P35_2" , "P35_3" , "P35_4" , "P35_5" , "P35_6" , "P35_7" ,"P36_0" , "P36_1" , "P36_2" , "P36_3" , "P36_4" , "P36_5" , "P36_6" , "P36_7" ,"P37_0" , "P37_1" , "P37_2" , "P37_3" , "P37_4" , "P37_5" , "P37_6" , "P37_7" ,"P38_0" , "P38_1" , "P38_2" , "P38_3" , "P38_4" , "P38_5" , "P38_6" , "P38_7" ,"P39_0" , "P39_1" , "P39_2" , "P39_3" , "P39_4" , "P39_5" , "P39_6" , "P39_7" ,"P40_0" , "P40_1" , "P40_2" , "P40_3" , "P40_4" , "P40_5" , "P40_6" , "P40_7" ,"P41_0" , "P41_1" , "P41_2" , "P41_3" , "P41_4" , "P41_5" , "P41_6" , "P41_7" ,"P42_0" , "P42_1" , "P42_2" , "P42_3" , "P42_4" , "P42_5" , "P42_6" , "P42_7" ,"P43_0" , "P43_1" , "P43_2" , "P43_3" , "P43_4" , "P43_5" , "P43_6" , "P43_7" ,"P44_0" , "P44_1" , "P44_2" , "P44_3" , "P44_4" , "P44_5" , "P44_6" , "P44_7" ,"P45_0" , "P45_1" , "P45_2" , "P45_3" , "P45_4" , "P45_5" , "P45_6" , "P45_7" ,"P46_0" , "P46_1" , "P46_2" , "P46_3" , "P46_4" , "P46_5" , "P46_6" , "P46_7" ,"P47_0" , "P47_1" , "P47_2" , "P47_3" , "P47_4" , "P47_5" , "P47_6" , "P47_7" ,"P48_0" , "P48_1" , "P48_2" , "P48_3" , "P48_4" , "P48_5" , "P48_6" , "P48_7" ,static const u64 r9a07g044_gpio_configs[] = {FG_OEN),FG_OEN),static const u64 r9a07g043_gpio_configs[] = {FG_OEN),FG_OEN),#ifdef CONFIG_RISCV/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ /* P19 */ /* P20 */ /* P21 */ /* P22 */ /* P23 */ /* P24 */ /* P25 */ /* P26 */ /* P27 */ /* P28 */ #endif static const u64 r9a08g045_gpio_configs[] = {/* P0 */ /* P1 */ /* P2 */ /* P3 */ /* P4 */ /* P5 */ /* P6 */ /* P7 */ /* P8 */ /* P9 */ /* P10 */ /* P11 */ /* P12 */ /* P13 */ /* P14 */ /* P15 */ /* P16 */ /* P17 */ /* P18 */ static const char * const rzg3e_gpio_names[] = {"P00" , "P01" , "P02" , "P03" , "P04" , "P05" , "P06" , "P07" ,"P10" , "P11" , "P12" , "P13" , "P14" , "P15" , "P16" , "P17" ,"P20" , "P21" , "P22" , "P23" , "P24" , "P25" , "P26" , "P27" ,"P30" , "P31" , "P32" , "P33" , "P34" , "P35" , "P36" , "P37" ,"P40" , "P41" , "P42" , "P43" , "P44" , "P45" , "P46" , "P47" ,"P50" , "P51" , "P52" , "P53" , "P54" , "P55" , "P56" , "P57" ,"P60" , "P61" , "P62" , "P63" , "P64" , "P65" , "P66" , "P67" ,"P70" , "P71" , "P72" , "P73" , "P74" , "P75" , "P76" , "P77" ,"P80" , "P81" , "P82" , "P83" , "P84" , "P85" , "P86" , "P87" ,"" , "" , "" , "" , "" , "" , "" , "" ,"PA0" , "PA1" , "PA2" , "PA3" , "PA4" , "PA5" , "PA6" , "PA7" ,"PB0" , "PB1" , "PB2" , "PB3" , "PB4" , "PB5" , "PB6" , "PB7" ,"PC0" , "PC1" , "PC2" , "PC3" , "PC4" , "PC5" , "PC6" , "PC7" ,"PD0" , "PD1" , "PD2" , "PD3" , "PD4" , "PD5" , "PD6" , "PD7" ,"PE0" , "PE1" , "PE2" , "PE3" , "PE4" , "PE5" , "PE6" , "PE7" ,"PF0" , "PF1" , "PF2" , "PF3" , "PF4" , "PF5" , "PF6" , "PF7" ,"PG0" , "PG1" , "PG2" , "PG3" , "PG4" , "PG5" , "PG6" , "PG7" ,"PH0" , "PH1" , "PH2" , "PH3" , "PH4" , "PH5" , "PH6" , "PH7" ,"" , "" , "" , "" , "" , "" , "" , "" ,"PJ0" , "PJ1" , "PJ2" , "PJ3" , "PJ4" , "PJ5" , "PJ6" , "PJ7" ,"PK0" , "PK1" , "PK2" , "PK3" , "PK4" , "PK5" , "PK6" , "PK7" ,"PL0" , "PL1" , "PL2" , "PL3" , "PL4" , "PL5" , "PL6" , "PL7" ,"PM0" , "PM1" , "PM2" , "PM3" , "PM4" , "PM5" , "PM6" , "PM7" ,"" , "" , "" , "" , "" , "" , "" , "" ,"" , "" , "" , "" , "" , "" , "" , "" ,"" , "" , "" , "" , "" , "" , "" , "" ,"" , "" , "" , "" , "" , "" , "" , "" ,"" , "" , "" , "" , "" , "" , "" , "" ,"PS0" , "PS1" , "PS2" , "PS3" , "PS4" , "PS5" , "PS6" , "PS7" ,static const u64 r9a09g047_gpio_configs[] = {/* P0 */ /* P1 */ /* P2 */ /* P3 */ /* P4 */ /* P5 */ /* P6 */ /* P7 */ /* P8 */ /* PA */ /* PB */ /* PC */ /* PD */ /* PE */ /* PF */ /* PG */ /* PH */ /* PJ */ /* PK */ /* PL */ /* PM */ /* PS */ static const char * const rzv2h_gpio_names[] = {"P00" , "P01" , "P02" , "P03" , "P04" , "P05" , "P06" , "P07" ,"P10" , "P11" , "P12" , "P13" , "P14" , "P15" , "P16" , "P17" ,"P20" , "P21" , "P22" , "P23" , "P24" , "P25" , "P26" , "P27" ,"P30" , "P31" , "P32" , "P33" , "P34" , "P35" , "P36" , "P37" ,"P40" , "P41" , "P42" , "P43" , "P44" , "P45" , "P46" , "P47" ,"P50" , "P51" , "P52" , "P53" , "P54" , "P55" , "P56" , "P57" ,"P60" , "P61" , "P62" , "P63" , "P64" , "P65" , "P66" , "P67" ,"P70" , "P71" , "P72" , "P73" , "P74" , "P75" , "P76" , "P77" ,"P80" , "P81" , "P82" , "P83" , "P84" , "P85" , "P86" , "P87" ,"P90" , "P91" , "P92" , "P93" , "P94" , "P95" , "P96" , "P97" ,"PA0" , "PA1" , "PA2" , "PA3" , "PA4" , "PA5" , "PA6" , "PA7" ,"PB0" , "PB1" , "PB2" , "PB3" , "PB4" , "PB5" , "PB6" , "PB7" ,static const u64 r9a09g057_gpio_configs[] = {/* P0 */ /* P1 */ /* P2 */ /* P3 */ /* P4 */ /* P5 */ /* P6 */ /* P7 */ /* P8 */ /* P9 */ /* PA */ /* PB */ static const struct {struct rzg2l_dedicated_configs common[35];struct rzg2l_dedicated_configs rzg2l_pins[7];"NMI" , RZG2L_SINGLE_PIN_PACK(0x1, 0, PIN_CFG_NF) },"TMS/SWDIO" , RZG2L_SINGLE_PIN_PACK(0x2, 0,"TDO" , RZG2L_SINGLE_PIN_PACK(0x3, 0,
Messung V0.5 C=95 H=94 G=94
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