/* S4-Deep Sleep Mode is NOT available for WALL/USB power */ if (!restart && !power_supply_is_system_supplied()) {
deep_sleep = 1;
dev_info(pwrc->dev, "Enabling S4-Deep Sleep Mode");
}
ret = regmap_update_bits(pwrc->regmap, ATC2603C_PMU_SYS_CTL0,
ATC2603C_PMU_SYS_CTL0_WK_ALL, reg_val); if (ret)
dev_warn(pwrc->dev, "failed to write SYS_CTL0: %d\n", ret);
/* Update power mode */
reg_mask = ATC2603C_PMU_SYS_CTL3_EN_S2 | ATC2603C_PMU_SYS_CTL3_EN_S3;
ret = regmap_update_bits(pwrc->regmap, ATC2603C_PMU_SYS_CTL3, reg_mask,
deep_sleep ? 0 : ATC2603C_PMU_SYS_CTL3_EN_S3); if (ret) {
dev_err(pwrc->dev, "failed to write SYS_CTL3: %d\n", ret); return ret;
}
/* S4-Deep Sleep Mode is NOT available for WALL/USB power */ if (!restart && !power_supply_is_system_supplied()) {
deep_sleep = 1;
dev_info(pwrc->dev, "Enabling S4-Deep Sleep Mode");
}
ret = regmap_update_bits(pwrc->regmap, ATC2609A_PMU_SYS_CTL0,
ATC2609A_PMU_SYS_CTL0_WK_ALL, reg_val); if (ret)
dev_warn(pwrc->dev, "failed to write SYS_CTL0: %d\n", ret);
/* Update power mode */
reg_mask = ATC2609A_PMU_SYS_CTL3_EN_S2 | ATC2609A_PMU_SYS_CTL3_EN_S3;
ret = regmap_update_bits(pwrc->regmap, ATC2609A_PMU_SYS_CTL3, reg_mask,
deep_sleep ? 0 : ATC2609A_PMU_SYS_CTL3_EN_S3); if (ret) {
dev_err(pwrc->dev, "failed to write SYS_CTL3: %d\n", ret); return ret;
}
ret = regmap_update_bits(pwrc->regmap,
restart ? ATC2609A_PMU_SYS_CTL0 : ATC2609A_PMU_SYS_CTL1,
reg_mask, reg_val); if (ret) {
dev_err(pwrc->dev, "failed to write SYS_CTL%d: %d\n",
restart ? 0 : 1, ret); return ret;
}
/* Wait for trigger completion */
mdelay(200);
return 0;
}
staticint atc2603c_init(conststruct atc260x_pwrc *pwrc)
{ int ret;
/* * Delay transition from S2/S3 to S1 in order to avoid * DDR init failure in Bootloader.
*/
ret = regmap_update_bits(pwrc->regmap, ATC2603C_PMU_SYS_CTL3,
ATC2603C_PMU_SYS_CTL3_S2S3TOS1_TIMER_EN,
ATC2603C_PMU_SYS_CTL3_S2S3TOS1_TIMER_EN); if (ret)
dev_warn(pwrc->dev, "failed to write SYS_CTL3: %d\n", ret);
/* Set wakeup sources */
ret = regmap_update_bits(pwrc->regmap, ATC2603C_PMU_SYS_CTL0,
ATC2603C_PMU_SYS_CTL0_WK_ALL,
ATC2603C_PMU_SYS_CTL0_HDSW_WK_EN |
ATC2603C_PMU_SYS_CTL0_ONOFF_LONG_WK_EN); if (ret)
dev_warn(pwrc->dev, "failed to write SYS_CTL0: %d\n", ret);
return ret;
}
staticint atc2609a_init(conststruct atc260x_pwrc *pwrc)
{ int ret;
/* Set wakeup sources */
ret = regmap_update_bits(pwrc->regmap, ATC2609A_PMU_SYS_CTL0,
ATC2609A_PMU_SYS_CTL0_WK_ALL,
ATC2609A_PMU_SYS_CTL0_HDSW_WK_EN |
ATC2609A_PMU_SYS_CTL0_ONOFF_LONG_WK_EN); if (ret)
dev_warn(pwrc->dev, "failed to write SYS_CTL0: %d\n", ret);
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