ret = dma_get_slave_caps(dws->txchan, &caps); if (!ret && caps.max_burst)
max_burst = caps.max_burst; else
max_burst = DW_SPI_TX_BURST_LEVEL;
/* * Having a Rx DMA channel serviced with higher priority than a Tx DMA * channel might not be enough to provide a well balanced DMA-based * SPI transfer interface. There might still be moments when the Tx DMA * channel is occasionally handled faster than the Rx DMA channel. * That in its turn will eventually cause the SPI Rx FIFO overflow if * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's * cleared by the Rx DMA channel. In order to fix the problem the Tx * DMA activity is intentionally slowed down by limiting the SPI Tx * FIFO depth with a value twice bigger than the Tx burst length.
*/
dws->txburst = min(max_burst, def_burst);
dw_writel(dws, DW_SPI_DMATDLR, dws->txburst);
}
/* * Assuming both channels belong to the same DMA controller hence the * peripheral side address width capabilities most likely would be * the same.
*/
dws->dma_addr_widths = tx.dst_addr_widths & rx.src_addr_widths;
/* * Get pci device for DMA controller, currently it could only * be the DMA controller of Medfield
*/
dma_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL); if (!dma_dev) return -ENODEV;
/* * dws->dma_chan_busy is set before the dma transfer starts, callback for tx * channel will clear a corresponding bit.
*/ staticvoid dw_spi_dma_tx_done(void *arg)
{ struct dw_spi *dws = arg;
clear_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy); if (test_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy)) return;
/* * It's unlikely that DMA engine is still doing the data fetching, but * if it's let's give it some reasonable time. The timeout calculation * is based on the synchronous APB/SSI reference clock rate, on a * number of data entries left in the Rx FIFO, times a number of clock * periods normally needed for a single APB read/write transaction * without PREADY signal utilized (which is true for the DW APB SSI * controller).
*/
nents = dw_readl(dws, DW_SPI_RXFLR);
ns = 4U * NSEC_PER_SEC / dws->max_freq * nents; if (ns <= NSEC_PER_USEC) {
delay.unit = SPI_DELAY_UNIT_NSECS;
delay.value = ns;
} else {
us = DIV_ROUND_UP(ns, NSEC_PER_USEC);
delay.unit = SPI_DELAY_UNIT_USECS;
delay.value = clamp_val(us, 0, USHRT_MAX);
}
while (dw_spi_dma_rx_busy(dws) && retry--)
spi_delay_exec(&delay, NULL);
/* * dws->dma_chan_busy is set before the dma transfer starts, callback for rx * channel will clear a corresponding bit.
*/ staticvoid dw_spi_dma_rx_done(void *arg)
{ struct dw_spi *dws = arg;
clear_bit(DW_SPI_RX_BUSY, &dws->dma_chan_busy); if (test_bit(DW_SPI_TX_BUSY, &dws->dma_chan_busy)) return;
staticint dw_spi_dma_transfer_all(struct dw_spi *dws, struct spi_transfer *xfer)
{ int ret;
/* Submit the DMA Tx transfer */
ret = dw_spi_dma_submit_tx(dws, xfer->tx_sg.sgl, xfer->tx_sg.nents); if (ret) goto err_clear_dmac;
/* Submit the DMA Rx transfer if required */ if (xfer->rx_buf) {
ret = dw_spi_dma_submit_rx(dws, xfer->rx_sg.sgl,
xfer->rx_sg.nents); if (ret) goto err_clear_dmac;
/* rx must be started before tx due to spi instinct */
dma_async_issue_pending(dws->rxchan);
}
dma_async_issue_pending(dws->txchan);
ret = dw_spi_dma_wait(dws, xfer->len, xfer->effective_speed_hz);
err_clear_dmac:
dw_writel(dws, DW_SPI_DMACR, 0);
return ret;
}
/* * In case if at least one of the requested DMA channels doesn't support the * hardware accelerated SG list entries traverse, the DMA driver will most * likely work that around by performing the IRQ-based SG list entries * resubmission. That might and will cause a problem if the DMA Tx channel is * recharged and re-executed before the Rx DMA channel. Due to * non-deterministic IRQ-handler execution latency the DMA Tx channel will * start pushing data to the SPI bus before the Rx DMA channel is even * reinitialized with the next inbound SG list entry. By doing so the DMA Tx * channel will implicitly start filling the DW APB SSI Rx FIFO up, which while * the DMA Rx channel being recharged and re-executed will eventually be * overflown. * * In order to solve the problem we have to feed the DMA engine with SG list * entries one-by-one. It shall keep the DW APB SSI Tx and Rx FIFOs * synchronized and prevent the Rx FIFO overflow. Since in general the tx_sg * and rx_sg lists may have different number of entries of different lengths * (though total length should match) let's virtually split the SG-lists to the * set of DMA transfers, which length is a minimum of the ordered SG-entries * lengths. An ASCII-sketch of the implemented algo is following: * xfer->len * |___________| * tx_sg list: |___|____|__| * rx_sg list: |_|____|____| * DMA transfers: |_|_|__|_|__| * * Note in order to have this workaround solving the denoted problem the DMA * engine driver should properly initialize the max_sg_burst capability and set * the DMA device max segment size parameter with maximum data block size the * DMA engine supports.
*/
/* Submit DMA Tx transfer */
ret = dw_spi_dma_submit_tx(dws, &tx_tmp, 1); if (ret) break;
/* Submit DMA Rx transfer */
ret = dw_spi_dma_submit_rx(dws, &rx_tmp, 1); if (ret) break;
/* Rx must be started before Tx due to SPI instinct */
dma_async_issue_pending(dws->rxchan);
dma_async_issue_pending(dws->txchan);
/* * Here we only need to wait for the DMA transfer to be * finished since SPI controller is kept enabled during the * procedure this loop implements and there is no risk to lose * data left in the Tx/Rx FIFOs.
*/
ret = dw_spi_dma_wait(dws, len, xfer->effective_speed_hz); if (ret) break;
/* * Execute normal DMA-based transfer (which submits the Rx and Tx SG * lists directly to the DMA engine at once) if either full hardware * accelerated SG list traverse is supported by both channels, or the * Tx-only SPI transfer is requested, or the DMA engine is capable to * handle both SG lists on hardware accelerated basis.
*/ if (!dws->dma_sg_burst || !xfer->rx_buf || nents <= dws->dma_sg_burst)
ret = dw_spi_dma_transfer_all(dws, xfer); else
ret = dw_spi_dma_transfer_one(dws, xfer); if (ret) return ret;
if (dws->host->cur_msg->status == -EINPROGRESS) {
ret = dw_spi_dma_wait_tx_done(dws, xfer); if (ret) return ret;
}
if (xfer->rx_buf && dws->host->cur_msg->status == -EINPROGRESS)
ret = dw_spi_dma_wait_rx_done(dws);
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