/* * tb_eeprom_active - enable rom access * * WARNING: Always disable access after usage. Otherwise the controller will * fail to reprobe.
*/ staticint tb_eeprom_active(struct tb_switch *sw, bool enable)
{ struct tb_eeprom_ctl ctl; int res = tb_eeprom_ctl_read(sw, &ctl); if (res) return res; if (enable) {
ctl.bit_banging_enable = 1;
res = tb_eeprom_ctl_write(sw, &ctl); if (res) return res;
ctl.fl_cs = 0; return tb_eeprom_ctl_write(sw, &ctl);
} else {
ctl.fl_cs = 1;
res = tb_eeprom_ctl_write(sw, &ctl); if (res) return res;
ctl.bit_banging_enable = 0; return tb_eeprom_ctl_write(sw, &ctl);
}
}
/* * tb_eeprom_transfer - transfer one bit * * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->fl_do. * If TB_EEPROM_OUT is passed, then ctl->fl_di will be written.
*/ staticint tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl, enum tb_eeprom_transfer direction)
{ int res; if (direction == TB_EEPROM_OUT) {
res = tb_eeprom_ctl_write(sw, ctl); if (res) return res;
}
ctl->fl_sk = 1;
res = tb_eeprom_ctl_write(sw, ctl); if (res) return res; if (direction == TB_EEPROM_IN) {
res = tb_eeprom_ctl_read(sw, ctl); if (res) return res;
}
ctl->fl_sk = 0; return tb_eeprom_ctl_write(sw, ctl);
}
/* * tb_eeprom_out - write one byte to the bus
*/ staticint tb_eeprom_out(struct tb_switch *sw, u8 val)
{ struct tb_eeprom_ctl ctl; int i; int res = tb_eeprom_ctl_read(sw, &ctl); if (res) return res; for (i = 0; i < 8; i++) {
ctl.fl_di = val & 0x80;
res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT); if (res) return res;
val <<= 1;
} return 0;
}
/* * tb_eeprom_in - read one byte from the bus
*/ staticint tb_eeprom_in(struct tb_switch *sw, u8 *val)
{ struct tb_eeprom_ctl ctl; int i; int res = tb_eeprom_ctl_read(sw, &ctl); if (res) return res;
*val = 0; for (i = 0; i < 8; i++) {
*val <<= 1;
res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN); if (res) return res;
*val |= ctl.fl_do;
} return 0;
}
/* * tb_eeprom_get_drom_offset - get drom offset within eeprom
*/ staticint tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
{ struct tb_cap_plug_events cap; int res;
if (!sw->cap_plug_events) {
tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n"); return -ENODEV;
}
res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events, sizeof(cap) / 4); if (res) return res;
if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
tb_sw_warn(sw, "no NVM\n"); return -ENODEV;
}
if (cap.drom_offset > 0xffff) {
tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
cap.drom_offset); return -ENXIO;
}
*offset = cap.drom_offset; return 0;
}
/* * tb_eeprom_read_n - read count bytes from offset into val
*/ staticint tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
size_t count)
{
u16 drom_offset; int i, res;
res = tb_eeprom_get_drom_offset(sw, &drom_offset); if (res) return res;
offset += drom_offset;
res = tb_eeprom_active(sw, true); if (res) return res;
res = tb_eeprom_out(sw, 3); if (res) return res;
res = tb_eeprom_out(sw, offset >> 8); if (res) return res;
res = tb_eeprom_out(sw, offset); if (res) return res; for (i = 0; i < count; i++) {
res = tb_eeprom_in(sw, val + i); if (res) return res;
} return tb_eeprom_active(sw, false);
}
static u8 tb_crc8(u8 *data, int len)
{ int i, j;
u8 val = 0xff; for (i = 0; i < len; i++) {
val ^= data[i]; for (j = 0; j < 8; j++)
val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
} return val;
}
/** * tb_drom_read_uid_only() - Read UID directly from DROM * @sw: Router whose UID to read * @uid: UID is placed here * * Does not use the cached copy in sw->drom. Used during resume to check switch * identity.
*/ int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
{
u8 data[9];
u8 crc; int res;
/* read uid */
res = tb_eeprom_read_n(sw, 0, data, 9); if (res) return res;
switch (header->index) { case 1: /* Length includes 2 bytes header so remove it before copy */
sw->vendor_name = kstrndup(entry->data,
header->len - sizeof(*header), GFP_KERNEL); if (!sw->vendor_name) return -ENOMEM; break;
case 2:
sw->device_name = kstrndup(entry->data,
header->len - sizeof(*header), GFP_KERNEL); if (!sw->device_name) return -ENOMEM; break; case 9: { conststruct tb_drom_entry_desc *desc =
(conststruct tb_drom_entry_desc *)entry;
/* * Some DROMs list more ports than the controller actually has * so we skip those but allow the parser to continue.
*/ if (header->index > sw->config.max_port_number) {
dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n"); return 0;
}
port = &sw->ports[header->index];
port->disabled = header->port_disabled; if (port->disabled) return 0;
res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1); if (res) return res;
type &= 0xffffff;
switch (entry->type) { case TB_DROM_ENTRY_GENERIC:
res = tb_drom_parse_entry_generic(sw, entry); break; case TB_DROM_ENTRY_PORT:
res = tb_drom_parse_entry_port(sw, entry); break;
} if (res) return res;
if (tb_switch_is_usb4(sw)) {
usb4_switch_read_uid(sw, &sw->uid); if (!usb4_copy_drom(sw, &size)) return tb_drom_parse(sw, size);
} else { if (!tb_drom_copy_efi(sw, &size)) return tb_drom_parse(sw, size);
if (!tb_drom_copy_nvm(sw, &size)) return tb_drom_parse(sw, size);
tb_drom_read_uid_only(sw, &sw->uid);
}
return 0;
}
staticint tb_drom_device_read(struct tb_switch *sw)
{
u16 size; int ret;
if (tb_switch_is_usb4(sw)) {
usb4_switch_read_uid(sw, &sw->uid);
ret = usb4_copy_drom(sw, &size);
} else {
ret = tb_drom_bit_bang(sw, &size);
}
if (ret) return ret;
return tb_drom_parse(sw, size);
}
/** * tb_drom_read() - Copy DROM to sw->drom and parse it * @sw: Router whose DROM to read and parse * * This function reads router DROM and if successful parses the entries and * populates the fields in @sw accordingly. Can be called for any router * generation. * * Returns %0 in case of success and negative errno otherwise.
*/ int tb_drom_read(struct tb_switch *sw)
{ if (sw->drom) return 0;
if (!tb_route(sw)) return tb_drom_host_read(sw); return tb_drom_device_read(sw);
}
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