/* * Hold NVM authentication failure status per switch This information * needs to stay around even when the switch gets power cycled so we * keep it separately.
*/ static LIST_HEAD(nvm_auth_status_cache); static DEFINE_MUTEX(nvm_auth_status_lock);
if (tb_switch_is_usb4(sw))
ret = usb4_switch_nvm_write(sw, 0, buf, image_size); else
ret = dma_port_flash_write(sw->dma_port, 0, buf, image_size); if (ret) return ret;
sw->nvm->flushed = true; return 0;
}
staticint nvm_authenticate_host_dma_port(struct tb_switch *sw)
{ int ret = 0;
/* * Root switch NVM upgrade requires that we disconnect the * existing paths first (in case it is not in safe mode * already).
*/ if (!sw->safe_mode) {
u32 status;
ret = tb_domain_disconnect_all_paths(sw->tb); if (ret) return ret; /* * The host controller goes away pretty soon after this if * everything goes well so getting timeout is expected.
*/
ret = dma_port_flash_update_auth(sw->dma_port); if (!ret || ret == -ETIMEDOUT) return 0;
/* * Any error from update auth operation requires power * cycling of the host router.
*/
tb_sw_warn(sw, "failed to authenticate NVM, power cycling\n"); if (dma_port_flash_update_auth_status(sw->dma_port, &status) > 0)
nvm_set_auth_status(sw, status);
}
/* * From safe mode we can get out by just power cycling the * switch.
*/
dma_port_power_cycle(sw->dma_port); return ret;
}
staticint nvm_authenticate_device_dma_port(struct tb_switch *sw)
{ int ret, retries = 10;
ret = dma_port_flash_update_auth(sw->dma_port); switch (ret) { case 0: case -ETIMEDOUT: case -EACCES: case -EINVAL: /* Power cycle is required */ break; default: return ret;
}
/* * Poll here for the authentication status. It takes some time * for the device to respond (we get timeout for a while). Once * we get response the device needs to be power cycled in order * to the new NVM to be taken into use.
*/ do {
u32 status;
ret = dma_port_flash_update_auth_status(sw->dma_port, &status); if (ret < 0 && ret != -ETIMEDOUT) return ret; if (ret > 0) { if (status) {
tb_sw_warn(sw, "failed to authenticate NVM\n");
nvm_set_auth_status(sw, status);
}
tb_sw_info(sw, "power cycling the switch now\n");
dma_port_power_cycle(sw->dma_port); return 0;
}
/* * During host router NVM upgrade we should not allow root port to * go into D3cold because some root ports cannot trigger PME * itself. To be on the safe side keep the root port in D0 during * the whole upgrade process.
*/
root_port = pcie_find_root_port(sw->tb->nhi->pdev); if (root_port)
pm_runtime_get_noresume(&root_port->dev);
}
root_port = pcie_find_root_port(sw->tb->nhi->pdev); if (root_port)
pm_runtime_put(&root_port->dev);
}
staticinlinebool nvm_readable(struct tb_switch *sw)
{ if (tb_switch_is_usb4(sw)) { /* * USB4 devices must support NVM operations but it is * optional for hosts. Therefore we query the NVM sector * size here and if it is supported assume NVM * operations are implemented.
*/ return usb4_switch_nvm_sector_size(sw) > 0;
}
/* Thunderbolt 2 and 3 devices support NVM through DMA port */ return !!sw->dma_port;
}
staticint nvm_authenticate(struct tb_switch *sw, bool auth_only)
{ int ret;
if (tb_switch_is_usb4(sw)) { if (auth_only) {
ret = usb4_switch_nvm_set_offset(sw, 0); if (ret) return ret;
}
sw->nvm->authenticating = true; return usb4_switch_nvm_authenticate(sw);
} if (auth_only) return -EOPNOTSUPP;
sw->nvm->authenticating = true; if (!tb_route(sw)) {
nvm_authenticate_start_dma_port(sw);
ret = nvm_authenticate_host_dma_port(sw);
} else {
ret = nvm_authenticate_device_dma_port(sw);
}
return ret;
}
/** * tb_switch_nvm_read() - Read router NVM * @sw: Router whose NVM to read * @address: Start address on the NVM * @buf: Buffer where the read data is copied * @size: Size of the buffer in bytes * * Reads from router NVM and returns the requested data in @buf. Locking * is up to the caller. Returns %0 in success and negative errno in case * of failure.
*/ int tb_switch_nvm_read(struct tb_switch *sw, unsignedint address, void *buf,
size_t size)
{ if (tb_switch_is_usb4(sw)) return usb4_switch_nvm_read(sw, address, buf, size); return dma_port_flash_read(sw->dma_port, address, buf, size);
}
if (!mutex_trylock(&sw->tb->lock)) return restart_syscall();
/* * Since writing the NVM image might require some special steps, * for example when CSS headers are written, we cache the image * locally here and handle the special cases when the user asks * us to authenticate the image.
*/
ret = tb_nvm_write_buf(nvm, offset, val, bytes);
mutex_unlock(&sw->tb->lock);
return ret;
}
staticint tb_switch_nvm_add(struct tb_switch *sw)
{ struct tb_nvm *nvm; int ret;
if (!nvm_readable(sw)) return 0;
nvm = tb_nvm_alloc(&sw->dev); if (IS_ERR(nvm)) {
ret = PTR_ERR(nvm) == -EOPNOTSUPP ? 0 : PTR_ERR(nvm); goto err_nvm;
}
ret = tb_nvm_read_version(nvm); if (ret) goto err_nvm;
/* * If the switch is in safe-mode the only accessible portion of * the NVM is the non-active one where userspace is expected to * write new functional NVM.
*/ if (!sw->safe_mode) {
ret = tb_nvm_add_active(nvm, nvm_read); if (ret) goto err_nvm;
tb_sw_dbg(sw, "NVM version %x.%x\n", nvm->major, nvm->minor);
}
if (!sw->no_nvm_upgrade) {
ret = tb_nvm_add_non_active(nvm, nvm_write); if (ret) goto err_nvm;
}
tb_dbg(tb, " Port %d: %x:%x (Revision: %d, TB Version: %d, Type: %s (%#x))\n",
regs->port_number, regs->vendor_id, regs->device_id,
regs->revision, regs->thunderbolt_version, tb_port_type(regs),
regs->type);
tb_dbg(tb, " Max hop id (in/out): %d/%d\n",
regs->max_in_hop_id, regs->max_out_hop_id);
tb_dbg(tb, " Max counters: %d\n", regs->max_counters);
tb_dbg(tb, " NFC Credits: %#x\n", regs->nfc_credits);
tb_dbg(tb, " Credits (total/control): %u/%u\n", port->total_credits,
port->ctl_credits);
}
/** * tb_port_state() - get connectedness state of a port * @port: the port to check * * The port must have a TB_CAP_PHY (i.e. it should be a real port). * * Return: Returns an enum tb_port_state on success or an error code on failure.
*/ int tb_port_state(struct tb_port *port)
{ struct tb_cap_phy phy; int res; if (port->cap_phy == 0) {
tb_port_WARN(port, "does not have a PHY\n"); return -EINVAL;
}
res = tb_port_read(port, &phy, TB_CFG_PORT, port->cap_phy, 2); if (res) return res; return phy.state;
}
/** * tb_wait_for_port() - wait for a port to become ready * @port: Port to wait * @wait_if_unplugged: Wait also when port is unplugged * * Wait up to 1 second for a port to reach state TB_PORT_UP. If * wait_if_unplugged is set then we also wait if the port is in state * TB_PORT_UNPLUGGED (it takes a while for the device to be registered after * switch resume). Otherwise we only wait if a device is registered but the link * has not yet been established. * * Return: Returns an error code on failure. Returns 0 if the port is not * connected or failed to reach state TB_PORT_UP within one second. Returns 1 * if the port is connected and in state TB_PORT_UP.
*/ int tb_wait_for_port(struct tb_port *port, bool wait_if_unplugged)
{ int retries = 10; int state; if (!port->cap_phy) {
tb_port_WARN(port, "does not have PHY\n"); return -EINVAL;
} if (tb_is_upstream_port(port)) {
tb_port_WARN(port, "is the upstream port\n"); return -EINVAL;
}
while (retries--) {
state = tb_port_state(port); switch (state) { case TB_PORT_DISABLED:
tb_port_dbg(port, "is disabled (state: 0)\n"); return 0;
case TB_PORT_UNPLUGGED: if (wait_if_unplugged) { /* used during resume */
tb_port_dbg(port, "is unplugged (state: 7), retrying...\n");
msleep(100); break;
}
tb_port_dbg(port, "is unplugged (state: 7)\n"); return 0;
case TB_PORT_UP: case TB_PORT_TX_CL0S: case TB_PORT_RX_CL0S: case TB_PORT_CL1: case TB_PORT_CL2:
tb_port_dbg(port, "is connected, link is up (state: %d)\n", state); return 1;
default: if (state < 0) return state;
/* * After plug-in the state is TB_PORT_CONNECTING. Give it some * time.
*/
tb_port_dbg(port, "is connected, link is not up (state: %d), retrying...\n",
state);
msleep(100);
}
}
tb_port_warn(port, "failed to reach state TB_PORT_UP. Ignoring port...\n"); return 0;
}
/** * tb_port_add_nfc_credits() - add/remove non flow controlled credits to port * @port: Port to add/remove NFC credits * @credits: Credits to add/remove * * Change the number of NFC credits allocated to @port by @credits. To remove * NFC credits pass a negative amount of credits. * * Return: Returns 0 on success or an error code on failure.
*/ int tb_port_add_nfc_credits(struct tb_port *port, int credits)
{
u32 nfc_credits;
if (credits == 0 || port->sw->is_unplugged) return 0;
/* * USB4 restricts programming NFC buffers to lane adapters only * so skip other ports.
*/ if (tb_switch_is_usb4(port->sw) && !tb_port_is_null(port)) return 0;
/** * tb_port_clear_counter() - clear a counter in TB_CFG_COUNTER * @port: Port whose counters to clear * @counter: Counter index to clear * * Return: Returns 0 on success or an error code on failure.
*/ int tb_port_clear_counter(struct tb_port *port, int counter)
{
u32 zero[3] = { 0, 0, 0 };
tb_port_dbg(port, "clearing counter %d\n", counter); return tb_port_write(port, zero, TB_CFG_COUNTERS, 3 * counter, 3);
}
/** * tb_port_unlock() - Unlock downstream port * @port: Port to unlock * * Needed for USB4 but can be called for any CIO/USB4 ports. Makes the * downstream router accessible for CM.
*/ int tb_port_unlock(struct tb_port *port)
{ if (tb_switch_is_icm(port->sw)) return 0; if (!tb_port_is_null(port)) return -EINVAL; if (tb_switch_is_usb4(port->sw)) return usb4_port_unlock(port); return 0;
}
/** * tb_port_enable() - Enable lane adapter * @port: Port to enable (can be %NULL) * * This is used for lane 0 and 1 adapters to enable it.
*/ int tb_port_enable(struct tb_port *port)
{ return __tb_port_enable(port, true);
}
/** * tb_port_disable() - Disable lane adapter * @port: Port to disable (can be %NULL) * * This is used for lane 0 and 1 adapters to disable it.
*/ int tb_port_disable(struct tb_port *port)
{ return __tb_port_enable(port, false);
}
/* * tb_init_port() - initialize a port * * This is a helper method for tb_switch_alloc. Does not check or initialize * any downstream switches. * * Return: Returns 0 on success or an error code on failure.
*/ staticint tb_init_port(struct tb_port *port)
{ int res; int cap;
INIT_LIST_HEAD(&port->list);
/* Control adapter does not have configuration space */ if (!port->port) return 0;
res = tb_port_read(port, &port->config, TB_CFG_PORT, 0, 8); if (res) { if (res == -ENODEV) {
tb_dbg(port->sw->tb, " Port %d: not implemented\n",
port->port);
port->disabled = true; return 0;
} return res;
}
/* Port 0 is the switch itself and has no PHY. */ if (port->config.type == TB_TYPE_PORT) {
cap = tb_port_find_cap(port, TB_PORT_CAP_PHY);
if (cap > 0)
port->cap_phy = cap; else
tb_port_WARN(port, "non switch port without a PHY\n");
cap = tb_port_find_cap(port, TB_PORT_CAP_USB4); if (cap > 0)
port->cap_usb4 = cap;
/* * USB4 ports the buffers allocated for the control path * can be read from the path config space. Legacy * devices we use hard-coded value.
*/ if (port->cap_usb4) { struct tb_regs_hop hop;
if (!tb_port_read(port, &hop, TB_CFG_HOPS, 0, 2))
port->ctl_credits = hop.initial_credits;
} if (!port->ctl_credits)
port->ctl_credits = 2;
} else {
cap = tb_port_find_cap(port, TB_PORT_CAP_ADAP); if (cap > 0)
port->cap_adap = cap;
}
staticint tb_port_alloc_hopid(struct tb_port *port, bool in, int min_hopid, int max_hopid)
{ int port_max_hopid; struct ida *ida;
if (in) {
port_max_hopid = port->config.max_in_hop_id;
ida = &port->in_hopids;
} else {
port_max_hopid = port->config.max_out_hop_id;
ida = &port->out_hopids;
}
/* * NHI can use HopIDs 1-max for other adapters HopIDs 0-7 are * reserved.
*/ if (!tb_port_is_nhi(port) && min_hopid < TB_PATH_MIN_HOPID)
min_hopid = TB_PATH_MIN_HOPID;
/** * tb_port_alloc_in_hopid() - Allocate input HopID from port * @port: Port to allocate HopID for * @min_hopid: Minimum acceptable input HopID * @max_hopid: Maximum acceptable input HopID * * Return: HopID between @min_hopid and @max_hopid or negative errno in * case of error.
*/ int tb_port_alloc_in_hopid(struct tb_port *port, int min_hopid, int max_hopid)
{ return tb_port_alloc_hopid(port, true, min_hopid, max_hopid);
}
/** * tb_port_alloc_out_hopid() - Allocate output HopID from port * @port: Port to allocate HopID for * @min_hopid: Minimum acceptable output HopID * @max_hopid: Maximum acceptable output HopID * * Return: HopID between @min_hopid and @max_hopid or negative errno in * case of error.
*/ int tb_port_alloc_out_hopid(struct tb_port *port, int min_hopid, int max_hopid)
{ return tb_port_alloc_hopid(port, false, min_hopid, max_hopid);
}
/** * tb_port_release_in_hopid() - Release allocated input HopID from port * @port: Port whose HopID to release * @hopid: HopID to release
*/ void tb_port_release_in_hopid(struct tb_port *port, int hopid)
{
ida_free(&port->in_hopids, hopid);
}
/** * tb_port_release_out_hopid() - Release allocated output HopID from port * @port: Port whose HopID to release * @hopid: HopID to release
*/ void tb_port_release_out_hopid(struct tb_port *port, int hopid)
{
ida_free(&port->out_hopids, hopid);
}
/** * tb_next_port_on_path() - Return next port for given port on a path * @start: Start port of the walk * @end: End port of the walk * @prev: Previous port (%NULL if this is the first) * * This function can be used to walk from one port to another if they * are connected through zero or more switches. If the @prev is dual * link port, the function follows that link and returns another end on * that same link. * * If the @end port has been reached, return %NULL. * * Domain tb->lock must be held when this function is called.
*/ struct tb_port *tb_next_port_on_path(struct tb_port *start, struct tb_port *end, struct tb_port *prev)
{ struct tb_port *next;
if (!prev) return start;
if (prev->sw == end->sw) { if (prev == end) return NULL; return end;
}
if (tb_switch_is_reachable(prev->sw, end->sw)) {
next = tb_port_at(tb_route(end->sw), prev->sw); /* Walk down the topology if next == prev */ if (prev->remote &&
(next == prev || next->dual_link_port == prev))
next = prev->remote;
} else { if (tb_is_upstream_port(prev)) {
next = prev->remote;
} else {
next = tb_upstream_port(prev->sw); /* * Keep the same link if prev and next are both * dual link ports.
*/ if (next->dual_link_port &&
next->link_nr != prev->link_nr) {
next = next->dual_link_port;
}
}
}
return next != prev ? next : NULL;
}
/** * tb_port_get_link_speed() - Get current link speed * @port: Port to check (USB4 or CIO) * * Returns link speed in Gb/s or negative errno in case of failure.
*/ int tb_port_get_link_speed(struct tb_port *port)
{
u32 val, speed; int ret;
if (!port->cap_phy) return -EINVAL;
ret = tb_port_read(port, &val, TB_CFG_PORT,
port->cap_phy + LANE_ADP_CS_1, 1); if (ret) return ret;
switch (speed) { case LANE_ADP_CS_1_CURRENT_SPEED_GEN4: return 40; case LANE_ADP_CS_1_CURRENT_SPEED_GEN3: return 20; default: return 10;
}
}
/** * tb_port_get_link_generation() - Returns link generation * @port: Lane adapter * * Returns link generation as number or negative errno in case of * failure. Does not distinguish between Thunderbolt 1 and Thunderbolt 2 * links so for those always returns 2.
*/ int tb_port_get_link_generation(struct tb_port *port)
{ int ret;
ret = tb_port_get_link_speed(port); if (ret < 0) return ret;
switch (ret) { case 40: return 4; case 20: return 3; default: return 2;
}
}
/** * tb_port_get_link_width() - Get current link width * @port: Port to check (USB4 or CIO) * * Returns link width. Return the link width as encoded in &enum * tb_link_width or negative errno in case of failure.
*/ int tb_port_get_link_width(struct tb_port *port)
{
u32 val; int ret;
if (!port->cap_phy) return -EINVAL;
ret = tb_port_read(port, &val, TB_CFG_PORT,
port->cap_phy + LANE_ADP_CS_1, 1); if (ret) return ret;
/* Matches the values in enum tb_link_width */ return (val & LANE_ADP_CS_1_CURRENT_WIDTH_MASK) >>
LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT;
}
/** * tb_port_width_supported() - Is the given link width supported * @port: Port to check * @width: Widths to check (bitmask) * * Can be called to any lane adapter. Checks if given @width is * supported by the hardware and returns %true if it is.
*/ bool tb_port_width_supported(struct tb_port *port, unsignedint width)
{
u32 phy, widths; int ret;
if (!port->cap_phy) returnfalse;
if (width & (TB_LINK_WIDTH_ASYM_TX | TB_LINK_WIDTH_ASYM_RX)) { if (tb_port_get_link_generation(port) < 4 ||
!usb4_port_asym_supported(port)) returnfalse;
}
ret = tb_port_read(port, &phy, TB_CFG_PORT,
port->cap_phy + LANE_ADP_CS_0, 1); if (ret) returnfalse;
/* * The field encoding is the same as &enum tb_link_width (which is * passed to @width).
*/
widths = FIELD_GET(LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK, phy); return widths & width;
}
/** * tb_port_set_link_width() - Set target link width of the lane adapter * @port: Lane adapter * @width: Target link width * * Sets the target link width of the lane adapter to @width. Does not * enable/disable lane bonding. For that call tb_port_set_lane_bonding(). * * Return: %0 in case of success and negative errno in case of error
*/ int tb_port_set_link_width(struct tb_port *port, enum tb_link_width width)
{
u32 val; int ret;
if (!port->cap_phy) return -EINVAL;
ret = tb_port_read(port, &val, TB_CFG_PORT,
port->cap_phy + LANE_ADP_CS_1, 1); if (ret) return ret;
val &= ~LANE_ADP_CS_1_TARGET_WIDTH_MASK; switch (width) { case TB_LINK_WIDTH_SINGLE: /* Gen 4 link cannot be single */ if (tb_port_get_link_generation(port) >= 4) return -EOPNOTSUPP;
val |= LANE_ADP_CS_1_TARGET_WIDTH_SINGLE <<
LANE_ADP_CS_1_TARGET_WIDTH_SHIFT; break;
case TB_LINK_WIDTH_DUAL: if (tb_port_get_link_generation(port) >= 4) return usb4_port_asym_set_link_width(port, width);
val |= LANE_ADP_CS_1_TARGET_WIDTH_DUAL <<
LANE_ADP_CS_1_TARGET_WIDTH_SHIFT; break;
case TB_LINK_WIDTH_ASYM_TX: case TB_LINK_WIDTH_ASYM_RX: return usb4_port_asym_set_link_width(port, width);
/** * tb_port_set_lane_bonding() - Enable/disable lane bonding * @port: Lane adapter * @bonding: enable/disable bonding * * Enables or disables lane bonding. This should be called after target * link width has been set (tb_port_set_link_width()). Note in most * cases one should use tb_port_lane_bonding_enable() instead to enable * lane bonding. * * Return: %0 in case of success and negative errno in case of error
*/ staticint tb_port_set_lane_bonding(struct tb_port *port, bool bonding)
{
u32 val; int ret;
if (!port->cap_phy) return -EINVAL;
ret = tb_port_read(port, &val, TB_CFG_PORT,
port->cap_phy + LANE_ADP_CS_1, 1); if (ret) return ret;
if (bonding)
val |= LANE_ADP_CS_1_LB; else
val &= ~LANE_ADP_CS_1_LB;
/** * tb_port_lane_bonding_enable() - Enable bonding on port * @port: port to enable * * Enable bonding by setting the link width of the port and the other * port in case of dual link port. Does not wait for the link to * actually reach the bonded state so caller needs to call * tb_port_wait_for_link_width() before enabling any paths through the * link to make sure the link is in expected state. * * Return: %0 in case of success and negative errno in case of error
*/ int tb_port_lane_bonding_enable(struct tb_port *port)
{ enum tb_link_width width; int ret;
/* * Enable lane bonding for both links if not already enabled by * for example the boot firmware.
*/
width = tb_port_get_link_width(port); if (width == TB_LINK_WIDTH_SINGLE) {
ret = tb_port_set_link_width(port, TB_LINK_WIDTH_DUAL); if (ret) goto err_lane0;
}
width = tb_port_get_link_width(port->dual_link_port); if (width == TB_LINK_WIDTH_SINGLE) {
ret = tb_port_set_link_width(port->dual_link_port,
TB_LINK_WIDTH_DUAL); if (ret) goto err_lane1;
}
/* * Only set bonding if the link was not already bonded. This * avoids the lane adapter to re-enter bonding state.
*/ if (width == TB_LINK_WIDTH_SINGLE && !tb_is_upstream_port(port)) {
ret = tb_port_set_lane_bonding(port, true); if (ret) goto err_lane1;
}
/* * When lane 0 bonding is set it will affect lane 1 too so * update both.
*/
port->bonded = true;
port->dual_link_port->bonded = true;
/** * tb_port_lane_bonding_disable() - Disable bonding on port * @port: port to disable * * Disable bonding by setting the link width of the port and the * other port in case of dual link port.
*/ void tb_port_lane_bonding_disable(struct tb_port *port)
{
tb_port_set_lane_bonding(port, false);
tb_port_set_link_width(port->dual_link_port, TB_LINK_WIDTH_SINGLE);
tb_port_set_link_width(port, TB_LINK_WIDTH_SINGLE);
port->dual_link_port->bonded = false;
port->bonded = false;
}
/** * tb_port_wait_for_link_width() - Wait until link reaches specific width * @port: Port to wait for * @width: Expected link width (bitmask) * @timeout_msec: Timeout in ms how long to wait * * Should be used after both ends of the link have been bonded (or * bonding has been disabled) to wait until the link actually reaches * the expected state. Returns %-ETIMEDOUT if the width was not reached * within the given timeout, %0 if it did. Can be passed a mask of * expected widths and succeeds if any of the widths is reached.
*/ int tb_port_wait_for_link_width(struct tb_port *port, unsignedint width, int timeout_msec)
{
ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); int ret;
/* Gen 4 link does not support single lane */ if ((width & TB_LINK_WIDTH_SINGLE) &&
tb_port_get_link_generation(port) >= 4) return -EOPNOTSUPP;
do {
ret = tb_port_get_link_width(port); if (ret < 0) { /* * Sometimes we get port locked error when * polling the lanes so we can ignore it and * retry.
*/ if (ret != -EACCES) return ret;
} elseif (ret & width) { return 0;
}
usleep_range(1000, 2000);
} while (ktime_before(ktime_get(), timeout));
return -ETIMEDOUT;
}
staticint tb_port_do_update_credits(struct tb_port *port)
{
u32 nfc_credits; int ret;
ret = tb_port_read(port, &nfc_credits, TB_CFG_PORT, ADP_CS_4, 1); if (ret) return ret;
if (nfc_credits != port->config.nfc_credits) {
u32 total;
total = (nfc_credits & ADP_CS_4_TOTAL_BUFFERS_MASK) >>
ADP_CS_4_TOTAL_BUFFERS_SHIFT;
/** * tb_port_update_credits() - Re-read port total credits * @port: Port to update * * After the link is bonded (or bonding was disabled) the port total * credits may change, so this function needs to be called to re-read * the credits. Updates also the second lane adapter.
*/ int tb_port_update_credits(struct tb_port *port)
{ int ret;
ret = tb_port_do_update_credits(port); if (ret) return ret;
if (!port->dual_link_port) return 0; return tb_port_do_update_credits(port->dual_link_port);
}
staticint tb_port_start_lane_initialization(struct tb_port *port)
{ int ret;
if (tb_switch_is_usb4(port->sw)) return 0;
ret = tb_lc_start_lane_initialization(port); return ret == -EINVAL ? 0 : ret;
}
/* * Returns true if the port had something (router, XDomain) connected * before suspend.
*/ staticbool tb_port_resume(struct tb_port *port)
{ bool has_remote = tb_port_has_remote(port);
if (port->usb4) {
usb4_port_device_resume(port->usb4);
} elseif (!has_remote) { /* * For disconnected downstream lane adapters start lane * initialization now so we detect future connects. * * For XDomain start the lane initialzation now so the * link gets re-established. * * This is only needed for non-USB4 ports.
*/ if (!tb_is_upstream_port(port) || port->xdomain)
tb_port_start_lane_initialization(port);
}
return has_remote || port->xdomain;
}
/** * tb_port_is_enabled() - Is the adapter port enabled * @port: Port to check
*/ bool tb_port_is_enabled(struct tb_port *port)
{ switch (port->config.type) { case TB_TYPE_PCIE_UP: case TB_TYPE_PCIE_DOWN: return tb_pci_port_is_enabled(port);
case TB_TYPE_DP_HDMI_IN: case TB_TYPE_DP_HDMI_OUT: return tb_dp_port_is_enabled(port);
case TB_TYPE_USB3_UP: case TB_TYPE_USB3_DOWN: return tb_usb3_port_is_enabled(port);
default: returnfalse;
}
}
/** * tb_usb3_port_is_enabled() - Is the USB3 adapter port enabled * @port: USB3 adapter port to check
*/ bool tb_usb3_port_is_enabled(struct tb_port *port)
{
u32 data;
if (tb_port_read(port, &data, TB_CFG_PORT,
port->cap_adap + ADP_USB3_CS_0, 1)) returnfalse;
return !!(data & ADP_USB3_CS_0_PE);
}
/** * tb_usb3_port_enable() - Enable USB3 adapter port * @port: USB3 adapter port to enable * @enable: Enable/disable the USB3 adapter
*/ int tb_usb3_port_enable(struct tb_port *port, bool enable)
{
u32 word = enable ? (ADP_USB3_CS_0_PE | ADP_USB3_CS_0_V)
: ADP_USB3_CS_0_V;
/** * tb_pci_port_is_enabled() - Is the PCIe adapter port enabled * @port: PCIe port to check
*/ bool tb_pci_port_is_enabled(struct tb_port *port)
{
u32 data;
if (tb_port_read(port, &data, TB_CFG_PORT,
port->cap_adap + ADP_PCIE_CS_0, 1)) returnfalse;
return !!(data & ADP_PCIE_CS_0_PE);
}
/** * tb_pci_port_enable() - Enable PCIe adapter port * @port: PCIe port to enable * @enable: Enable/disable the PCIe adapter
*/ int tb_pci_port_enable(struct tb_port *port, bool enable)
{
u32 word = enable ? ADP_PCIE_CS_0_PE : 0x0; if (!port->cap_adap) return -ENXIO; return tb_port_write(port, &word, TB_CFG_PORT,
port->cap_adap + ADP_PCIE_CS_0, 1);
}
/** * tb_dp_port_hpd_is_active() - Is HPD already active * @port: DP out port to check * * Checks if the DP OUT adapter port has HPD bit already set.
*/ int tb_dp_port_hpd_is_active(struct tb_port *port)
{
u32 data; int ret;
ret = tb_port_read(port, &data, TB_CFG_PORT,
port->cap_adap + ADP_DP_CS_2, 1); if (ret) return ret;
return !!(data & ADP_DP_CS_2_HPD);
}
/** * tb_dp_port_hpd_clear() - Clear HPD from DP IN port * @port: Port to clear HPD * * If the DP IN port has HPD set, this function can be used to clear it.
*/ int tb_dp_port_hpd_clear(struct tb_port *port)
{
u32 data; int ret;
ret = tb_port_read(port, &data, TB_CFG_PORT,
port->cap_adap + ADP_DP_CS_3, 1); if (ret) return ret;
/** * tb_dp_port_set_hops() - Set video/aux Hop IDs for DP port * @port: DP IN/OUT port to set hops * @video: Video Hop ID * @aux_tx: AUX TX Hop ID * @aux_rx: AUX RX Hop ID * * Programs specified Hop IDs for DP IN/OUT port. Can be called for USB4 * router DP adapters too but does not program the values as the fields * are read-only.
*/ int tb_dp_port_set_hops(struct tb_port *port, unsignedint video, unsignedint aux_tx, unsignedint aux_rx)
{
u32 data[2]; int ret;
if (tb_switch_is_usb4(port->sw)) return 0;
ret = tb_port_read(port, data, TB_CFG_PORT,
port->cap_adap + ADP_DP_CS_0, ARRAY_SIZE(data)); if (ret) return ret;
/** * tb_dp_port_enable() - Enables/disables DP paths of a port * @port: DP IN/OUT port * @enable: Enable/disable DP path * * Once Hop IDs are programmed DP paths can be enabled or disabled by * calling this function.
*/ int tb_dp_port_enable(struct tb_port *port, bool enable)
{
u32 data[2]; int ret;
ret = tb_port_read(port, data, TB_CFG_PORT,
port->cap_adap + ADP_DP_CS_0, ARRAY_SIZE(data)); if (ret) return ret;
/* * For lane adapters we issue downstream port * reset and clear up path config spaces. * * For protocol adapters we disable the path and * clear path config space one by one (from 8 to * Max Input HopID of the adapter).
*/ if (tb_port_is_null(port) && !tb_is_upstream_port(port)) {
ret = tb_port_reset(port); if (ret) return ret;
} elseif (tb_port_is_usb3_down(port) ||
tb_port_is_usb3_up(port)) {
tb_usb3_port_enable(port, false);
} elseif (tb_port_is_dpin(port) ||
tb_port_is_dpout(port)) {
tb_dp_port_enable(port, false);
} elseif (tb_port_is_pcie_down(port) ||
tb_port_is_pcie_up(port)) {
tb_pci_port_enable(port, false);
} else { continue;
}
/* Cleanup path config space of protocol adapter */ for (i = TB_PATH_MIN_HOPID;
i <= port->config.max_in_hop_id; i++) {
ret = tb_path_deactivate_hop(port, i); if (ret) return ret;
}
}
} else { struct tb_cfg_result res;
/* Thunderbolt 1 uses the "reset" config space packet */
res.err = tb_sw_write(sw, ((u32 *) &sw->config) + 2,
TB_CFG_SWITCH, 2, 2); if (res.err) return res.err;
res = tb_cfg_reset(sw->tb->ctl, tb_route(sw)); if (res.err > 0) return -EIO; elseif (res.err < 0) return res.err;
}
staticbool tb_switch_enumerated(struct tb_switch *sw)
{
u32 val; int ret;
/* * Read directly from the hardware because we use this also * during system sleep where sw->config.enabled is already set * by us.
*/
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_3, 1); if (ret) returnfalse;
return !!(val & ROUTER_CS_3_V);
}
/** * tb_switch_reset() - Perform reset to the router * @sw: Router to reset * * Issues reset to the router @sw. Can be used for any router. For host * routers, resets all the downstream ports and cleans up path config * spaces accordingly. For device routers issues downstream port reset * through the parent router, so as side effect there will be unplug * soon after this is finished. * * If the router is not enumerated does nothing. * * Returns %0 on success or negative errno in case of failure.
*/ int tb_switch_reset(struct tb_switch *sw)
{ int ret;
/* * We cannot access the port config spaces unless the router is * already enumerated. If the router is not enumerated it is * equal to being reset so we can skip that here.
*/ if (!tb_switch_enumerated(sw)) return 0;
tb_sw_dbg(sw, "resetting\n");
if (tb_route(sw))
ret = tb_switch_reset_device(sw); else
ret = tb_switch_reset_host(sw);
if (ret)
tb_sw_warn(sw, "failed to reset\n");
return ret;
}
/** * tb_switch_wait_for_bit() - Wait for specified value of bits in offset * @sw: Router to read the offset value from * @offset: Offset in the router config space to read from * @bit: Bit mask in the offset to wait for * @value: Value of the bits to wait for * @timeout_msec: Timeout in ms how long to wait * * Wait till the specified bits in specified offset reach specified value. * Returns %0 in case of success, %-ETIMEDOUT if the @value was not reached * within the given timeout or a negative errno in case of failure.
*/ int tb_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit,
u32 value, int timeout_msec)
{
ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
do {
u32 val; int ret;
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1); if (ret) return ret;
if ((val & bit) == value) return 0;
usleep_range(50, 100);
} while (ktime_before(ktime_get(), timeout));
return -ETIMEDOUT;
}
/* * tb_plug_events_active() - enable/disable plug events on a switch * * Also configures a sane plug_events_delay of 255ms. * * Return: Returns 0 on success or an error code on failure.
*/ staticint tb_plug_events_active(struct tb_switch *sw, bool active)
{
u32 data; int res;
if (tb_switch_is_icm(sw) || tb_switch_is_usb4(sw)) return 0;
sw->config.plug_events_delay = 0xff;
res = tb_sw_write(sw, ((u32 *) &sw->config) + 4, TB_CFG_SWITCH, 4, 1); if (res) return res;
res = tb_sw_read(sw, &data, TB_CFG_SWITCH, sw->cap_plug_events + 1, 1); if (res) return res;
if (active) {
data = data & 0xFFFFFF83; switch (sw->config.device_id) { case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE: case PCI_DEVICE_ID_INTEL_EAGLE_RIDGE: case PCI_DEVICE_ID_INTEL_PORT_RIDGE: break; default: /* * Skip Alpine Ridge, it needs to have vendor * specific USB hotplug event enabled for the * internal xHCI to work.
*/ if (!tb_switch_is_alpine_ridge(sw))
data |= TB_PLUG_EVENTS_USB_DISABLE;
}
} else {
data = data | 0x7c;
} return tb_sw_write(sw, &data, TB_CFG_SWITCH,
sw->cap_plug_events + 1, 1);
}
staticint tb_switch_set_authorized(struct tb_switch *sw, unsignedint val)
{ char envp_string[13]; int ret = -EINVAL; char *envp[] = { envp_string, NULL };
if (!mutex_trylock(&sw->tb->lock)) return restart_syscall();
if (!!sw->authorized == !!val) goto unlock;
switch (val) { /* Disapprove switch */ case 0: if (tb_route(sw)) {
ret = disapprove_switch(&sw->dev, NULL); goto unlock;
} break;
/* Approve switch */ case 1: if (sw->key)
ret = tb_domain_approve_switch_key(sw->tb, sw); else
ret = tb_domain_approve_switch(sw->tb, sw); break;
/* Challenge switch */ case 2: if (sw->key)
ret = tb_domain_challenge_switch_key(sw->tb, sw); break;
default: break;
}
if (!ret) {
sw->authorized = val; /* * Notify status change to the userspace, informing the new * value of /sys/bus/thunderbolt/devices/.../authorized.
*/
sprintf(envp_string, "AUTHORIZED=%u", sw->authorized);
kobject_uevent_env(&sw->dev.kobj, KOBJ_CHANGE, envp);
}
/* * Currently all lanes must run at the same speed but we expose here * both directions to allow possible asymmetric links in the future.
*/ static DEVICE_ATTR(rx_speed, 0444, speed_show, NULL); static DEVICE_ATTR(tx_speed, 0444, speed_show, NULL);
if (!mutex_trylock(&sw->tb->lock)) {
ret = restart_syscall(); goto exit_rpm;
}
if (sw->no_nvm_upgrade) {
ret = -EOPNOTSUPP; goto exit_unlock;
}
/* If NVMem devices are not yet added */ if (!sw->nvm) {
ret = -EAGAIN; goto exit_unlock;
}
ret = kstrtoint(buf, 10, &val); if (ret) goto exit_unlock;
/* Always clear the authentication status */
nvm_clear_auth_status(sw);
if (val > 0) { if (val == AUTHENTICATE_ONLY) { if (disconnect)
ret = -EINVAL; else
ret = nvm_authenticate(sw, true);
} else { if (!sw->nvm->flushed) { if (!sw->nvm->buf) {
ret = -EINVAL; goto exit_unlock;
}
ret = nvm_validate_and_write(sw); if (ret || val == WRITE_ONLY) goto exit_unlock;
} if (val == WRITE_AND_AUTHENTICATE) { if (disconnect)
ret = tb_lc_force_power(sw); else
ret = nvm_authenticate(sw, false);
}
}
}
if (tb_switch_is_usb4(sw)) { if (add_uevent_var(env, "USB4_VERSION=%u.0",
usb4_switch_version(sw))) return -ENOMEM;
}
if (!tb_route(sw)) {
type = "host";
} else { conststruct tb_port *port; bool hub = false;
/* Device is hub if it has any downstream ports */
tb_switch_for_each_port(sw, port) { if (!port->disabled && !tb_is_upstream_port(port) &&
tb_port_is_null(port)) {
hub = true; break;
}
}
type = hub ? "hub" : "device";
}
if (add_uevent_var(env, "USB4_TYPE=%s", type)) return -ENOMEM; return 0;
}
/* * Currently only need to provide the callbacks. Everything else is handled * in the connection manager.
*/ staticint __maybe_unused tb_switch_runtime_suspend(struct device *dev)
{ struct tb_switch *sw = tb_to_switch(dev); conststruct tb_cm_ops *cm_ops = sw->tb->cm_ops;
if (cm_ops->runtime_suspend_switch) return cm_ops->runtime_suspend_switch(sw);
staticint tb_switch_get_generation(struct tb_switch *sw)
{ if (tb_switch_is_usb4(sw)) return 4;
if (sw->config.vendor_id == PCI_VENDOR_ID_INTEL) { switch (sw->config.device_id) { case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE: case PCI_DEVICE_ID_INTEL_EAGLE_RIDGE: case PCI_DEVICE_ID_INTEL_LIGHT_PEAK: case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C: case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C: case PCI_DEVICE_ID_INTEL_PORT_RIDGE: case PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_BRIDGE: case PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_BRIDGE: return 1;
case PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE: case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE: case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE: return 2;
case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE: case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE: case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE: case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE: case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE: case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE: case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE: case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE: case PCI_DEVICE_ID_INTEL_ICL_NHI0: case PCI_DEVICE_ID_INTEL_ICL_NHI1: return 3;
}
}
/* * For unknown switches assume generation to be 1 to be on the * safe side.
*/
tb_sw_warn(sw, "unsupported switch device id %#x\n",
sw->config.device_id); return 1;
}
staticbool tb_switch_exceeds_max_depth(conststruct tb_switch *sw, int depth)
{ int max_depth;
/** * tb_switch_alloc() - allocate a switch * @tb: Pointer to the owning domain * @parent: Parent device for this switch * @route: Route string for this switch * * Allocates and initializes a switch. Will not upload configuration to * the switch. For that you need to call tb_switch_configure() * separately. The returned switch should be released by calling * tb_switch_put(). * * Return: Pointer to the allocated switch or ERR_PTR() in case of * failure.
*/ struct tb_switch *tb_switch_alloc(struct tb *tb, struct device *parent,
u64 route)
{ struct tb_switch *sw; int upstream_port; int i, ret, depth;
/* Unlock the downstream port so we can access the switch below */ if (route) { struct tb_switch *parent_sw = tb_to_switch(parent); struct tb_port *down;
down = tb_port_at(route, parent_sw);
tb_port_unlock(down);
}
depth = tb_route_length(route);
upstream_port = tb_cfg_get_upstream_port(tb->ctl, route); if (upstream_port < 0) return ERR_PTR(upstream_port);
sw = kzalloc(sizeof(*sw), GFP_KERNEL); if (!sw) return ERR_PTR(-ENOMEM);
sw->tb = tb;
ret = tb_cfg_read(tb->ctl, &sw->config, route, 0, TB_CFG_SWITCH, 0, 5); if (ret) goto err_free_sw_ports;
/* Make sure we do not exceed maximum topology limit */ if (tb_switch_exceeds_max_depth(sw, depth)) {
ret = -EADDRNOTAVAIL; goto err_free_sw_ports;
}
/* initialize ports */
sw->ports = kcalloc(sw->config.max_port_number + 1, sizeof(*sw->ports),
GFP_KERNEL); if (!sw->ports) {
ret = -ENOMEM; goto err_free_sw_ports;
}
for (i = 0; i <= sw->config.max_port_number; i++) { /* minimum setup for tb_find_cap and tb_drom_read to work */
sw->ports[i].sw = sw;
sw->ports[i].port = i;
/* Control port does not need HopID allocation */ if (i) {
ida_init(&sw->ports[i].in_hopids);
ida_init(&sw->ports[i].out_hopids);
}
}
ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_PLUG_EVENTS); if (ret > 0)
sw->cap_plug_events = ret;
ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_TIME2); if (ret > 0)
sw->cap_vsec_tmu = ret;
ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_LINK_CONTROLLER); if (ret > 0)
sw->cap_lc = ret;
ret = tb_switch_find_vse_cap(sw, TB_VSE_CAP_CP_LP); if (ret > 0)
sw->cap_lp = ret;
/* Root switch is always authorized */ if (!route)
sw->authorized = true;
/** * tb_switch_alloc_safe_mode() - allocate a switch that is in safe mode * @tb: Pointer to the owning domain * @parent: Parent device for this switch * @route: Route string for this switch * * This creates a switch in safe mode. This means the switch pretty much * lacks all capabilities except DMA configuration port before it is * flashed with a valid NVM firmware. * * The returned switch must be released by calling tb_switch_put(). * * Return: Pointer to the allocated switch or ERR_PTR() in case of failure
*/ struct tb_switch *
tb_switch_alloc_safe_mode(struct tb *tb, struct device *parent, u64 route)
{ struct tb_switch *sw;
sw = kzalloc(sizeof(*sw), GFP_KERNEL); if (!sw) return ERR_PTR(-ENOMEM);
/** * tb_switch_configure() - Uploads configuration to the switch * @sw: Switch to configure * * Call this function before the switch is added to the system. It will * upload configuration to the switch and makes it available for the * connection manager to use. Can be called to the switch again after * resume from low power states to re-initialize it. * * Return: %0 in case of success and negative errno in case of failure
*/ int tb_switch_configure(struct tb_switch *sw)
{ struct tb *tb = sw->tb;
u64 route; int ret;
route = tb_route(sw);
tb_dbg(tb, "%s Switch at %#llx (depth: %d, up port: %d)\n",
sw->config.enabled ? "restoring" : "initializing", route,
tb_route_length(route), sw->config.upstream_port_number);
sw->config.enabled = 1;
if (tb_switch_is_usb4(sw)) { /* * For USB4 devices, we need to program the CM version * accordingly so that it knows to expose all the * additional capabilities. Program it according to USB4 * version to avoid changing existing (v1) routers behaviour.
*/ if (usb4_switch_version(sw) < 2)
sw->config.cmuv = ROUTER_CS_4_CMUV_V1; else
sw->config.cmuv = ROUTER_CS_4_CMUV_V2;
sw->config.plug_events_delay = 0xa;
/* Enumerate the switch */
ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH,
ROUTER_CS_1, 4); if (ret) return ret;
ret = usb4_switch_setup(sw);
} else { if (sw->config.vendor_id != PCI_VENDOR_ID_INTEL)
tb_sw_warn(sw, "unknown switch vendor id %#x\n",
sw->config.vendor_id);
/* Enumerate the switch */
ret = tb_sw_write(sw, (u32 *)&sw->config + 1, TB_CFG_SWITCH,
ROUTER_CS_1, 3);
} if (ret) return ret;
return tb_plug_events_active(sw, true);
}
/** * tb_switch_configuration_valid() - Set the tunneling configuration to be valid * @sw: Router to configure * * Needs to be called before any tunnels can be setup through the * router. Can be called to any router. * * Returns %0 in success and negative errno otherwise.
*/ int tb_switch_configuration_valid(struct tb_switch *sw)
{ if (tb_switch_is_usb4(sw)) return usb4_switch_configuration_valid(sw); return 0;
}
if (tb_switch_is_usb4(sw)) {
ret = usb4_switch_read_uid(sw, &sw->uid); if (ret) return ret;
uid = true;
} else { /* * The newer controllers include fused UUID as part of * link controller specific registers
*/
ret = tb_lc_read_uuid(sw, uuid); if (ret) { if (ret != -EINVAL) return ret;
uid = true;
}
}
if (uid) { /* * ICM generates UUID based on UID and fills the upper * two words with ones. This is not strictly following * UUID format but we want to be compatible with it so * we do the same here.
*/
uuid[0] = sw->uid & 0xffffffff;
uuid[1] = (sw->uid >> 32) & 0xffffffff;
uuid[2] = 0xffffffff;
uuid[3] = 0xffffffff;
}
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