// SPDX-License-Identifier: GPL-2.0 /* * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) * * Copyright (C) 2002 - 2011 Paul Mundt * Copyright (C) 2015 Glider bvba * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). * * based off of the old drivers/char/sh-sci.c by: * * Copyright (C) 1999, 2000 Niibe Yutaka * Copyright (C) 2000 Sugioka Toshinobu * Modified to support multiple serial ports. Stuart Menefy (May 2000). * Modified to support SecureEdge. David McCullough (2002) * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). * Removed SH7300 support (Jul 2007). #undef DEBUG#include <linux/clk.h>#include <linux/console.h>#include <linux/ctype.h>#include <linux/cpufreq.h>#include <linux/delay.h>#include <linux/dmaengine.h>#include <linux/dma-mapping.h>#include <linux/err.h>#include <linux/errno.h>#include <linux/init.h>#include <linux/interrupt.h>#include <linux/ioport.h>#include <linux/ktime.h>#include <linux/major.h>#include <linux/minmax.h>#include <linux/module.h>#include <linux/mm.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/pm_runtime.h>#include <linux/reset.h>#include <linux/scatterlist.h>#include <linux/serial.h>#include <linux/serial_sci.h>#include <linux/sh_dma.h>#include <linux/slab.h>#include <linux/string.h>#include <linux/sysrq.h>#include <linux/timer.h>#include <linux/tty.h>#include <linux/tty_flip.h>#ifdef CONFIG_SUPERH#include <asm /sh_bios.h>#include <asm /platform_early.h>#endif #include "rsci.h" #include "serial_mctrl_gpio.h" #include "sh-sci.h" #include "sh-sci-common.h" #define SCIx_IRQ_IS_MUXED(port) \#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \/* Iterate over all supported sampling rates, from high to low */ #define for_each_sr(_sr, _port) \for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \if ((_port)->sampling_rate_mask & SCI_SR((_sr)))#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS#define SCI_PUBLIC_PORT_ID(port) (((port) & BIT(7)) ? PORT_GENERIC : (port))static struct sci_port sci_ports[SCI_NPORTS];static unsigned long sci_ports_in_use;static struct uart_driver sci_uart_driver;static bool sci_uart_earlycon;static bool sci_uart_earlycon_dev_probing;static const struct sci_port_params_bits sci_sci_port_params_bits = {static const struct sci_port_params_bits sci_scif_port_params_bits = {static const struct sci_common_regs sci_common_regs = {struct sci_suspend_regs {static size_t sci_suspend_regs_size(void )return sizeof (struct sci_suspend_regs);static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {/* * Common SCI definitions, dependent on the port's regshift * value. /* * Common definitions for legacy IrDA ports. /* * Common SCIFA definitions. /* * Common SCIFB definitions. /* * Common SH-2(A) SCIF definitions for ports with FIFO data * count registers. /* * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T1. * It looks like a normal SCIF with FIFO data, but with a * compressed address space. Also, the break out of interrupts * are different: ERI/BRI, RXI, TXI, TEI, DRI. /* * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC * with below differences, * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI, * TEI-DRI, RXI-EDGE and TXI-EDGE. * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode. * - SCFCR register does not have SCFCR_MCE bit. * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO. /* * Common SH-3 SCIF definitions. /* * Common SH-4(A) SCIF(B) definitions. /* * Common SCIF definitions for ports with a Baud Rate Generator for * External Clock (BRG). /* * Common HSCIF definitions. /* * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR * register. /* * Common SH-4(A) SCIF(B) definitions for ports with FIFO data * count registers. /* aliased to SCFDR */ /* * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR * registers. #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])/* * The "offset" here is rather misleading, in that it refers to an enum * value relative to the port mapping rather than the fixed offset * itself, which needs to be manually retrieved from the platform's * register map for the given port. static unsigned int sci_serial_in(struct uart_port *p, int offset)const struct plat_sci_reg *reg = sci_getreg(p, offset);if (reg->size == 8)return ioread8(p->membase + (reg->offset << p->regshift));else if (reg->size == 16)return ioread16(p->membase + (reg->offset << p->regshift));else "Invalid register access\n" );return 0;static void sci_serial_out(struct uart_port *p, int offset, int value)const struct plat_sci_reg *reg = sci_getreg(p, offset);if (reg->size == 8)else if (reg->size == 16)else "Invalid register access\n" );void sci_port_enable(struct sci_port *sci_port)unsigned int i;if (!sci_port->port.dev)return ;for (i = 0; i < SCI_NUM_CLKS; i++) {"SH_SCI" );void sci_port_disable(struct sci_port *sci_port)unsigned int i;if (!sci_port->port.dev)return ;for (i = SCI_NUM_CLKS; i-- > 0; )"SH_SCI" );static inline unsigned long port_rx_irq_mask(struct uart_port *port)/* * Not all ports (such as SCIFA) will support REIE. Rather than * special-casing the port type, we check the port initialization * IRQ enable mask to see whether the IRQ is desired at all. If * it's unset, it's logically inferred that there's no point in * testing for it. return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);static void sci_start_tx(struct uart_port *port)struct sci_port *s = to_sci_port(port);unsigned short ctrl;#ifdef CONFIG_SERIAL_SH_SCI_DMAif (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {new , scr = sci_serial_in(port, SCSCR);if (s->chan_tx)new = scr | SCSCR_TDRQE;else new = scr & ~SCSCR_TDRQE;if (new != scr)new );if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)/* Switch irq from SCIF to DMA */ #endif if (!s->chan_tx || s->regtype == SCIx_RZ_SCIFA_REGTYPE ||/* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ /* * For SCI, TE (transmit enable) must be set after setting TIE * (transmit interrupt enable) or in the same instruction to start * the transmit process. if (s->type == PORT_SCI)static void sci_stop_tx(struct uart_port *port)struct sci_port *s = to_sci_port(port);unsigned short ctrl;/* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)#ifdef CONFIG_SERIAL_SH_SCI_DMAif (s->chan_tx &&#endif static void sci_start_rx(struct uart_port *port)struct sci_port *s = to_sci_port(port);unsigned short ctrl;if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)static void sci_stop_rx(struct uart_port *port)struct sci_port *s = to_sci_port(port);unsigned short ctrl;if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)struct sci_port *s = to_sci_port(port);if (s->type == PORT_SCI) {/* Just store the mask */ else if (s->params->overrun_mask == SCIFA_ORER) {/* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ /* Only clear the status bits we want to clear */ else {/* Store the mask, clear parity/framing errors */ #if defined (CONFIG_CONSOLE_POLL) || defined (CONFIG_SERIAL_SH_SCI_CONSOLE) || \defined (CONFIG_SERIAL_SH_SCI_EARLYCON)#ifdef CONFIG_CONSOLE_POLLstatic int sci_poll_get_char(struct uart_port *port)unsigned short status;struct sci_port *s = to_sci_port(port);int c;do {if (status & SCxSR_ERRORS(port)) {continue ;break ;while (1);if (!(status & SCxSR_RDxF(port)))return NO_POLL_CHAR;/* Dummy read */ return c;#endif static void sci_poll_put_char(struct uart_port *port, unsigned char c)struct sci_port *s = to_sci_port(port);const struct sci_common_regs *regs = s->params->common_regs;unsigned int status;do {while (!(status & SCxSR_TDxE(port)));#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || static void sci_init_pins(struct uart_port *port, unsigned int cflag)struct sci_port *s = to_sci_port(port);/* * Use port-specific handler if provided. if (s->cfg->ops && s->cfg->ops->init_pins) {return ;if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {/* Enable RXD and TXD pin functions */ if (s->has_rtscts) {/* RTS# is output, active low, unless autorts */ if (!(port->mctrl & TIOCM_RTS)) {else if (!s->autorts) {else {/* Enable RTS# pin function */ /* Enable CTS# pin function */ else if (sci_getreg(port, SCSPTR)->size && s->regtype != SCIx_RZV2H_SCIF_REGTYPE) {/* RTS# is always output; and active low, unless autorts */ if (!(port->mctrl & TIOCM_RTS))else if (!s->autorts)/* CTS# and SCK are inputs */ static int sci_txfill(struct uart_port *port)struct sci_port *s = to_sci_port(port);unsigned int fifo_mask = (s->params->fifosize << 1) - 1;const struct plat_sci_reg *reg;if (reg->size)return sci_serial_in(port, SCTFDR) & fifo_mask;if (reg->size)return sci_serial_in(port, SCFDR) >> 8;return !(sci_serial_in(port, SCxSR) & SCI_TDRE);static int sci_txroom(struct uart_port *port)return port->fifosize - sci_txfill(port);static int sci_rxfill(struct uart_port *port)struct sci_port *s = to_sci_port(port);unsigned int fifo_mask = (s->params->fifosize << 1) - 1;const struct plat_sci_reg *reg;if (reg->size)return sci_serial_in(port, SCRFDR) & fifo_mask;if (reg->size)return sci_serial_in(port, SCFDR) & fifo_mask;return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;/* ********************************************************************** * * the interrupt related routines * static void sci_transmit_chars(struct uart_port *port)struct tty_port *tport = &port->state->port;unsigned int stopped = uart_tx_stopped(port);struct sci_port *s = to_sci_port(port);unsigned short status;unsigned short ctrl;int count;if (!(status & SCxSR_TDxE(port))) {if (kfifo_is_empty(&tport->xmit_fifo))else return ;do {unsigned char c;if (port->x_char) {else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {if (s->type == PORT_SCI &&return ;break ;true ;while (--count > 0);if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)if (kfifo_is_empty(&tport->xmit_fifo)) {if (s->type == PORT_SCI) {static void sci_receive_chars(struct uart_port *port)struct tty_port *tport = &port->state->port;struct sci_port *s = to_sci_port(port);int i, count, copied = 0;unsigned short status;unsigned char flag;if (!(status & SCxSR_RDxF(port)))return ;while (1) {/* Don't copy more bytes than there is room for in the buffer */ /* If for any reason we can't copy more data, we're done! */ if (count == 0)break ;if (s->type == PORT_SCI) {char c = sci_serial_in(port, SCxRDR);if (uart_handle_sysrq_char(port, c))else else {for (i = 0; i < count; i++) {char c;if (s->type == PORT_SCIF ||else {if (uart_handle_sysrq_char(port, c)) {continue ;/* Store data and status */ if (status & SCxSR_FER(port)) {else if (status & SCxSR_PER(port)) {else /* dummy read */ if (copied) {/* Tell the rest of the system the news. New characters! */ else {/* TTY buffers full; read from RX reg to prevent lockup */ /* dummy read */ static int sci_handle_errors(struct uart_port *port)int copied = 0;struct sci_port *s = to_sci_port(port);const struct sci_common_regs *regs = s->params->common_regs;unsigned int status = s->ops->read_reg(port, regs->status);struct tty_port *tport = &port->state->port;/* Handle overruns */ if (status & s->params->overrun_mask) {/* overrun error */ if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))if (status & SCxSR_FER(port)) {/* frame error */ if (tty_insert_flip_char(tport, 0, TTY_FRAME))if (status & SCxSR_PER(port)) {/* parity error */ if (tty_insert_flip_char(tport, 0, TTY_PARITY))if (copied)return copied;static int sci_handle_fifo_overrun(struct uart_port *port)struct tty_port *tport = &port->state->port;struct sci_port *s = to_sci_port(port);const struct plat_sci_reg *reg;int copied = 0;if (s->type != SCI_PORT_RSCI) {if (!reg->size)return 0;if (status & s->params->overrun_mask) {return copied;static int sci_handle_breaks(struct uart_port *port)int copied = 0;unsigned short status = sci_serial_in(port, SCxSR);struct tty_port *tport = &port->state->port;if (uart_handle_break(port))return 0;if (status & SCxSR_BRK(port)) {/* Notify of BREAK */ if (tty_insert_flip_char(tport, 0, TTY_BREAK))if (copied)return copied;static int scif_set_rtrg(struct uart_port *port, int rx_trig)struct sci_port *s = to_sci_port(port);unsigned int bits;if (rx_trig >= port->fifosize)if (rx_trig < 1)/* HSCIF can be set to an arbitrary level. */ if (sci_getreg(port, HSRTRGR)->size) {return rx_trig;switch (s->type) {case PORT_SCIF:if (rx_trig < 4) {else if (rx_trig < 8) {else if (rx_trig < 14) {else {break ;case PORT_SCIFA:case PORT_SCIFB:if (rx_trig < 16) {else if (rx_trig < 32) {else if (rx_trig < 48) {else {break ;default :"unknown FIFO configuration" );return 1;return rx_trig;static int scif_rtrg_enabled(struct uart_port *port)if (sci_getreg(port, HSRTRGR)->size)return sci_serial_in(port, HSRTRGR) != 0;else return (sci_serial_in(port, SCFCR) &static void rx_fifo_timer_fn(struct timer_list *t)struct sci_port *s = timer_container_of(s, t, rx_fifo_timer);struct uart_port *port = &s->port;"Rx timed out\n" );static ssize_t rx_fifo_trigger_show(struct device *dev,struct device_attribute *attr, char *buf)struct uart_port *port = dev_get_drvdata(dev);struct sci_port *sci = to_sci_port(port);return sprintf(buf, "%d\n" , sci->rx_trigger);static ssize_t rx_fifo_trigger_store(struct device *dev,struct device_attribute *attr,const char *buf, size_t count)struct uart_port *port = dev_get_drvdata(dev);struct sci_port *sci = to_sci_port(port);int ret;long r;if (ret)return ret;if (sci->type == PORT_SCIFA || sci->type == PORT_SCIFB)return count;static DEVICE_ATTR_RW(rx_fifo_trigger);static ssize_t rx_fifo_timeout_show(struct device *dev,struct device_attribute *attr,char *buf)struct uart_port *port = dev_get_drvdata(dev);struct sci_port *sci = to_sci_port(port);int v;if (sci->type == PORT_HSCIF)else return sprintf(buf, "%d\n" , v);static ssize_t rx_fifo_timeout_store(struct device *dev,struct device_attribute *attr,const char *buf,struct uart_port *port = dev_get_drvdata(dev);struct sci_port *sci = to_sci_port(port);int ret;long r;if (ret)return ret;if (sci->type == PORT_HSCIF) {if (r < 0 || r > 3)return -EINVAL;else {if (r > 0)return count;static DEVICE_ATTR_RW(rx_fifo_timeout);#ifdef CONFIG_SERIAL_SH_SCI_DMAstatic void sci_dma_tx_complete(void *arg)struct sci_port *s = arg;struct uart_port *port = &s->port;struct tty_port *tport = &port->state->port;unsigned long flags;"%s(%d)\n" , __func__, port->line);if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)true ;if (!kfifo_is_empty(&tport->xmit_fifo)) {else {if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {/* Switch irq from DMA to SCIF */ /* Locking: called with port lock held */ static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)struct uart_port *port = &s->port;struct tty_port *tport = &port->state->port;int copied;if (copied < count)return copied;static int sci_dma_rx_find_active(struct sci_port *s)unsigned int i;for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)if (s->active_rx == s->cookie_rx[i])return i;return -1;/* Must only be called with uart_port_lock taken */ static void sci_dma_rx_chan_invalidate(struct sci_port *s)unsigned int i;for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)static void sci_dma_rx_release(struct sci_port *s)struct dma_chan *chan = s->chan_rx_saved;struct uart_port *port = &s->port;unsigned long flags;static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)long sec = usec / 1000000;long nsec = (usec % 1000000) * 1000;static void sci_dma_rx_reenable_irq(struct sci_port *s)struct uart_port *port = &s->port;/* Direct new serial port interrupts back to CPU */ if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||if (s->regtype == SCIx_RZ_SCIFA_REGTYPE)else static void sci_dma_rx_complete(void *arg)struct sci_port *s = arg;struct dma_chan *chan = s->chan_rx;struct uart_port *port = &s->port;struct dma_async_tx_descriptor *desc;unsigned long flags;int active, count = 0;"%s(%d) active cookie %d\n" , __func__, port->line,if (active >= 0)if (count)if (!desc)goto fail;if (dma_submit_error(s->cookie_rx[active]))goto fail;"%s: cookie %d #%d, new active cookie %d\n" ,return ;/* Switch to PIO */ "Failed submitting Rx DMA descriptor\n" );static void sci_dma_tx_release(struct sci_port *s)struct dma_chan *chan = s->chan_tx_saved;static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)struct dma_chan *chan = s->chan_rx;struct uart_port *port = &s->port;unsigned long flags;int i;for (i = 0; i < 2; i++) {struct scatterlist *sg = &s->sg_rx[i];struct dma_async_tx_descriptor *desc;if (!desc)goto fail;if (dma_submit_error(s->cookie_rx[i]))goto fail;return 0;/* Switch to PIO */ if (!port_lock_held)if (i)if (!port_lock_held)return -EAGAIN;static void sci_dma_tx_work_fn(struct work_struct *work)struct sci_port *s = container_of(work, struct sci_port, work_tx);struct dma_async_tx_descriptor *desc;struct dma_chan *chan = s->chan_tx;struct uart_port *port = &s->port;struct tty_port *tport = &port->state->port;unsigned long flags;unsigned int tail;/* * DMA is idle now. * Port xmit buffer is already mapped, and it is one page... Just adjust * offsets and lengths. Since it is a circular buffer, we have to * transmit till the end, and then the rest. Take the port lock to get a * consistent xmit buffer state. if (!s->tx_dma_len) {/* Transmit buffer has been flushed */ return ;if (!desc) {"Failed preparing Tx DMA descriptor\n" );goto switch_to_pio;if (dma_submit_error(s->cookie_tx)) {"Failed submitting Tx DMA descriptor\n" );goto switch_to_pio;"%s: %p: %u, cookie %d\n" ,return ;return ;static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)struct sci_port *s = container_of(t, struct sci_port, rx_timer);struct dma_chan *chan = s->chan_rx;struct uart_port *port = &s->port;struct dma_tx_state state;enum dma_status status;unsigned long flags;unsigned int read;int active, count;"DMA Rx timed out\n" );if (active < 0) {return HRTIMER_NORESTART;if (status == DMA_COMPLETE) {"Cookie %d #%d has already completed\n" ,/* Let packet complete handler take care of the packet */ return HRTIMER_NORESTART;/* * sometimes DMA transfer doesn't stop even if it is stopped and * data keeps on coming until transaction is complete so check * for DMA_COMPLETE again * Let packet complete handler take care of the packet if (status == DMA_COMPLETE) {"Transaction complete after DMA engine was stopped" );return HRTIMER_NORESTART;/* Handle incomplete DMA receive */ if (read) {if (count)if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||true );return HRTIMER_NORESTART;static struct dma_chan *sci_request_dma_chan(struct uart_port *port,enum dma_transfer_direction dir)struct dma_chan *chan;struct dma_slave_config cfg;int ret;"tx" : "rx" );if (IS_ERR(chan)) {"dma_request_chan failed\n" );return NULL;sizeof (cfg));if (ret) {"dmaengine_slave_config failed %d\n" , ret);return NULL;return chan;static void sci_request_dma(struct uart_port *port)struct sci_port *s = to_sci_port(port);struct tty_port *tport = &port->state->port;struct dma_chan *chan;"%s: port %d\n" , __func__, port->line);/* * DMA on console may interfere with Kernel log messages which use * plain putchar(). So, simply don't use it with a console. if (uart_console(port))return ;if (!port->dev->of_node)return ;/* * Don't request a dma channel if no channel was specified * in the device tree. if (!of_property_present(port->dev->of_node, "dmas" ))return ;"%s: TX: got channel %p\n" , __func__, chan);if (chan) {/* UART circular tx buffer is an aligned page. */ if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {"Failed mapping Tx DMA descriptor\n" );else {"%s: mapped %lu@%p to %pad\n" ,"%s: RX: got channel %p\n" , __func__, chan);if (chan) {unsigned int i;void *buf;if (!buf) {"Failed to allocate Rx dma buffer, using PIO\n" );return ;for (i = 0; i < 2; i++) {struct scatterlist *sg = &s->sg_rx[i];if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||false );static void sci_free_dma(struct uart_port *port)struct sci_port *s = to_sci_port(port);if (s->chan_tx_saved)if (s->chan_rx_saved)static void sci_flush_buffer(struct uart_port *port)struct sci_port *s = to_sci_port(port);/* * In uart_flush_buffer(), the xmit circular buffer has just been * cleared, so we have to reset tx_dma_len accordingly, and stop any * pending transfers if (s->chan_tx) {static void sci_dma_check_tx_occurred(struct sci_port *s)struct dma_tx_state state;enum dma_status status;if (!s->chan_tx)return ;if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)true ;#else /* !CONFIG_SERIAL_SH_SCI_DMA */ static inline void sci_request_dma(struct uart_port *port)static inline void sci_free_dma(struct uart_port *port)static void sci_dma_check_tx_occurred(struct sci_port *s)#define sci_flush_buffer NULL#endif /* !CONFIG_SERIAL_SH_SCI_DMA */ static irqreturn_t sci_rx_interrupt(int irq, void *ptr)struct uart_port *port = ptr;struct sci_port *s = to_sci_port(port);#ifdef CONFIG_SERIAL_SH_SCI_DMAif (s->chan_rx) {/* Disable future Rx interrupts */ if (s->type == PORT_SCIFA || s->type == PORT_SCIFB ||if (s->regtype == SCIx_RZ_SCIFA_REGTYPE) {else {else {if (sci_dma_rx_submit(s, false ) < 0)goto handle_pio;/* Clear current interrupt */ "Rx IRQ %lu: setup t-out in %u us\n" ,return IRQ_HANDLED;#endif if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {if (!s->ops->rtrg_enabled(port))/* I think sci_receive_chars has to be called irrespective * of whether the I_IXOFF is set, otherwise, how is the interrupt * to be disabled? return IRQ_HANDLED;static irqreturn_t sci_tx_interrupt(int irq, void *ptr)struct uart_port *port = ptr;unsigned long flags;struct sci_port *s = to_sci_port(port);return IRQ_HANDLED;static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)struct uart_port *port = ptr;struct sci_port *s = to_sci_port(port);const struct sci_common_regs *regs = s->params->common_regs;unsigned long flags;if (s->type != PORT_SCI && s->type != SCI_PORT_RSCI)return sci_tx_interrupt(irq, ptr);return IRQ_HANDLED;static irqreturn_t sci_br_interrupt(int irq, void *ptr)struct uart_port *port = ptr;struct sci_port *s = to_sci_port(port);/* Handle BREAKs */ /* drop invalid character received before break was detected */ return IRQ_HANDLED;static irqreturn_t sci_er_interrupt(int irq, void *ptr)struct uart_port *port = ptr;struct sci_port *s = to_sci_port(port);if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {/* Break and Error interrupts are muxed */ unsigned short ssr_status = sci_serial_in(port, SCxSR);/* Break Interrupt */ if (ssr_status & SCxSR_BRK(port))/* Break only? */ if (!(ssr_status & SCxSR_ERRORS(port)))return IRQ_HANDLED;/* Handle errors */ if (s->type == PORT_SCI) {if (sci_handle_errors(port)) {/* discard character in rx buffer */ else {if (!s->chan_rx)/* Kick the transmission */ if (!s->chan_tx)return IRQ_HANDLED;static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;struct uart_port *port = ptr;struct sci_port *s = to_sci_port(port);if (s->params->overrun_reg == SCxSR)else if (sci_getreg(port, s->params->overrun_reg)->size)/* Tx Interrupt */ if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&/* * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / * DR flags if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&/* Error Interrupt */ if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)/* Break Interrupt */ if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&/* Overrun Interrupt */ if (orer_status & s->params->overrun_mask) {return ret;static const struct sci_irq_desc {const char *desc;/* * Split out handlers, the default case. "rx err" ,"rx full" ,"tx empty" ,"break" ,"rx ready" ,"tx end" ,/* * Special muxed handler. "mux" ,static int sci_request_irq(struct sci_port *port)struct uart_port *up = &port->port;int i, j, w, ret = 0;for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {const struct sci_irq_desc *desc;int irq;/* Check if already registered (muxed) */ for (w = 0; w < i; w++)if (port->irqs[w] == port->irqs[i])if (w > i)continue ;if (SCIx_IRQ_IS_MUXED(port)) {else {/* * Certain port types won't support all of the * available interrupt sources. if (unlikely(irq < 0))continue ;"%s:%s" ,if (!port->irqstr[j]) {goto out_nomem;if (unlikely(ret)) {"Can't allocate %s IRQ\n" , desc->desc);goto out_noirq;return 0;while (--i >= 0)while (--j >= 0)return ret;static void sci_free_irq(struct sci_port *port)int i, j;/* * Intentionally in reverse order so we iterate over the muxed * IRQ first. for (i = 0; i < SCIx_NR_IRQS; i++) {int irq = port->irqs[i];/* * Certain port types won't support all of the available * interrupt sources. if (unlikely(irq < 0))continue ;/* Check if already freed (irq was muxed) */ for (j = 0; j < i; j++)if (port->irqs[j] == irq)if (j > i)continue ;if (SCIx_IRQ_IS_MUXED(port)) {/* If there's only one IRQ, we're done. */ return ;static unsigned int sci_tx_empty(struct uart_port *port)unsigned short status = sci_serial_in(port, SCxSR);unsigned short in_tx_fifo = sci_txfill(port);struct sci_port *s = to_sci_port(port);if (!s->tx_occurred)return TIOCSER_TEMT;return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;static void sci_set_rts(struct uart_port *port, bool state)struct sci_port *s = to_sci_port(port);if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {/* Active low */ if (state)else /* RTS# is output */ else if (sci_getreg(port, SCSPTR)->size) {/* Active low */ if (state)else static bool sci_get_cts(struct uart_port *port)struct sci_port *s = to_sci_port(port);if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {/* Active low */ return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);else if (sci_getreg(port, SCSPTR)->size) {/* Active low */ return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);return true ;/* * Modem control is a bit of a mixed bag for SCI(F) ports. Generally * CTS/RTS is supported in hardware by at least one port and controlled * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently * handled via the ->init_pins() op, which is a bit of a one-way street, * lacking any ability to defer pin control -- this will later be * converted over to the GPIO framework). * * Other modes (such as loopback) are supported generically on certain * port types, but not others. For these it's sufficient to test for the * existence of the support register and simply ignore the port type. static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)struct sci_port *s = to_sci_port(port);if (mctrl & TIOCM_LOOP) {const struct plat_sci_reg *reg;/* * Standard loopback mode for SCFCR ports. if (reg->size)if (!s->has_rtscts)return ;if (!(mctrl & TIOCM_RTS)) {/* Disable Auto RTS */ if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)/* Clear RTS */ else if (s->autorts) {if (s->type == PORT_SCIFA || s->type == PORT_SCIFB) {/* Enable RTS# pin function */ /* Enable Auto RTS */ if (s->regtype != SCIx_RZV2H_SCIF_REGTYPE)else {/* Set RTS */ static unsigned int sci_get_mctrl(struct uart_port *port)struct sci_port *s = to_sci_port(port);struct mctrl_gpios *gpios = s->gpios;unsigned int mctrl = 0;/* * CTS/RTS is handled in hardware when supported, while nothing * else is wired up. if (s->autorts) {if (sci_get_cts(port))else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))return mctrl;static void sci_enable_ms(struct uart_port *port)static void sci_break_ctl(struct uart_port *port, int break_state)unsigned short scscr, scsptr;unsigned long flags;/* check whether the port has SCSPTR */ if (!sci_getreg(port, SCSPTR)->size) {/* * Not supported by hardware. Most parts couple break and rx * interrupts together, with break detection always enabled. return ;if (break_state == -1) {else {static void sci_shutdown_complete(struct uart_port *port)struct sci_port *s = to_sci_port(port);int sci_startup(struct uart_port *port)struct sci_port *s = to_sci_port(port);int ret;"%s(%d)\n" , __func__, port->line);false ;if (unlikely(ret < 0)) {return ret;return 0;"SH_SCI" );void sci_shutdown(struct uart_port *port)struct sci_port *s = to_sci_port(port);unsigned long flags;"%s(%d)\n" , __func__, port->line);false ;#ifdef CONFIG_SERIAL_SH_SCI_DMAif (s->chan_rx_saved) {"%s(%d) deleting rx_timer\n" , __func__,#endif if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)"SH_SCI" );static int sci_sck_calc(struct sci_port *s, unsigned int bps,unsigned int *srr)unsigned long freq = s->clk_rates[SCI_SCK];int err, min_err = INT_MAX;unsigned int sr;if (s->type != PORT_HSCIF)if (abs(err) >= abs(min_err))continue ;if (!err)break ;"SCK: %u%+d bps using SR %u\n" , bps, min_err,return min_err;static int sci_brg_calc(struct sci_port *s, unsigned int bps,unsigned long freq, unsigned int *dlr,unsigned int *srr)int err, min_err = INT_MAX;unsigned int sr, dl;if (s->type != PORT_HSCIF)if (abs(err) >= abs(min_err))continue ;if (!err)break ;"BRG: %u%+d bps using DL %u SR %u\n" , bps,return min_err;/* calculate sample rate, BRR, and clock select */ static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,unsigned int *brr, unsigned int *srr,unsigned int *cks)unsigned long freq = s->clk_rates[SCI_FCK];unsigned int sr, br, prediv, scrate, c;int err, min_err = INT_MAX;if (s->type != PORT_HSCIF)/* * Find the combination of sample rate and clock select with the * smallest deviation from the desired baud rate. * Prefer high sample rates to maximise the receive margin. * * M: Receive margin (%) * N: Ratio of bit rate to clock (N = sampling rate) * D: Clock duty (D = 0 to 1.0) * L: Frame length (L = 9 to 12) * F: Absolute value of clock frequency deviation * * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - * (|D - 0.5| / N * (1 + F))| * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. for (c = 0; c <= 3; c++) {/* integerized formulas from HSCIF documentation */ /* * We need to calculate: * * br = freq / (prediv * bps) clamped to [1..256] * err = freq / (br * prediv) - bps * * Watch out for overflow when calculating the desired * sampling clock rate! if (bps > UINT_MAX / prediv)break ;if (abs(err) >= abs(min_err))continue ;if (!err)goto found;"BRR: %u%+d bps using N %u SR %u cks %u\n" , bps,return min_err;static void sci_reset(struct uart_port *port)const struct plat_sci_reg *reg;unsigned int status;struct sci_port *s = to_sci_port(port);/* TE=0, RE=0, CKE1=0 */ if (reg->size)if (sci_getreg(port, SCLSR)->size) {if (s->rx_trigger > 1) {if (s->rx_fifo_timeout) {else {if (s->type == PORT_SCIFA ||else static void sci_set_termios(struct uart_port *port, struct ktermios *termios,const struct ktermios *old)unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;struct sci_port *s = to_sci_port(port);const struct plat_sci_reg *reg;int min_err = INT_MAX, err;unsigned long max_freq = 0;int best_clk = -1;unsigned long flags;if ((termios->c_cflag & CSIZE) == CS7) {else {if (termios->c_cflag & PARENB)if (termios->c_cflag & PARODD)if (termios->c_cflag & CSTOPB)/* * earlyprintk comes here early on with port->uartclk set to zero. * the clock framework is not up and running at this point so here * we assume that 115200 is the maximum baud rate. please note that * the baud rate is not programmed during earlyprintk - it is assumed * that the previous boot loader has enabled required clocks and * setup the baud rate generator hardware for us already. if (!port->uartclk) {goto done;for (i = 0; i < SCI_NUM_CLKS; i++)if (!baud)goto done;/* * There can be multiple sources for the sampling clock. Find the one * that gives us the smallest deviation from the desired baud rate. /* Optional Undivided External Clock */ if (s->clk_rates[SCI_SCK] && s->type != PORT_SCIFA &&if (abs(err) < abs(min_err)) {if (!err)goto done;/* Optional BRG Frequency Divided External Clock */ if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {if (abs(err) < abs(min_err)) {if (!err)goto done;/* Optional BRG Frequency Divided Internal Clock */ if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {if (abs(err) < abs(min_err)) {if (!min_err)goto done;/* Divided Functional Clock using standard Bit Rate Register */ if (abs(err) < abs(min_err)) {if (best_clk >= 0)"Using clk %pC for %u%+d bps\n" ,/* * Program the optional External Baud Rate Generator (BRG) first. * It controls the mux to select (H)SCK or frequency divided clock. if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {/* byte size and parity */ if (sci_getreg(port, SEMR)->size)if (best_clk >= 0) {if (s->type == PORT_SCIFA || s->type == PORT_SCIFB)switch (srr + 1) {case 5: smr_val |= SCSMR_SRC_5; break ;case 7: smr_val |= SCSMR_SRC_7; break ;case 11: smr_val |= SCSMR_SRC_11; break ;case 13: smr_val |= SCSMR_SRC_13; break ;case 16: smr_val |= SCSMR_SRC_16; break ;case 17: smr_val |= SCSMR_SRC_17; break ;case 19: smr_val |= SCSMR_SRC_19; break ;case 27: smr_val |= SCSMR_SRC_27; break ;
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