/* * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on * the host controller implementation. * * To facilitate the strongest possible byte-order checking from "sparse" * and so on, we use __leXX unless that's not practical.
*/ #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC typedef __u32 __bitwise __hc32; typedef __u16 __bitwise __hc16; #else #define __hc32 __le32 #define __hc16 __le16 #endif
/* statistics can be kept for tuning/monitoring */ #ifdef CONFIG_DYNAMIC_DEBUG #define EHCI_STATS #endif
/* termination of urbs from core */ unsignedlong complete; unsignedlong unlink;
};
/* * Scheduling and budgeting information for periodic transfers, for both * high-speed devices and full/low-speed devices lying behind a TT.
*/ struct ehci_per_sched { struct usb_device *udev; /* access to the TT */ struct usb_host_endpoint *ep; struct list_head ps_list; /* node on ehci_tt's ps_list */
u16 tt_usecs; /* time on the FS/LS bus */
u16 cs_mask; /* C-mask and S-mask bytes */
u16 period; /* actual period in frames */
u16 phase; /* actual phase, frame part */
u8 bw_phase; /* same, for bandwidth
reservation */
u8 phase_uf; /* uframe part of the phase */
u8 usecs, c_usecs; /* times on the HS bus */
u8 bw_uperiod; /* period in microframes, for
bandwidth reservation */
u8 bw_period; /* same, in frames */
}; #define NO_FRAME 29999 /* frame not assigned yet */
/* ehci_hcd->lock guards shared data against other CPUs: * ehci_hcd: async, unlink, periodic (and shadow), ... * usb_host_endpoint: hcpriv * ehci_qh: qh_next, qtd_list * ehci_qtd: qtd_list * * Also, hold this lock when talking to HC registers or * when updating hw_* fields in shared qh/qtd/... structures.
*/
#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
/* * ehci_rh_state values of EHCI_RH_RUNNING or above mean that the * controller may be doing DMA. Lower values mean there's no DMA.
*/ enum ehci_rh_state {
EHCI_RH_HALTED,
EHCI_RH_SUSPENDED,
EHCI_RH_RUNNING,
EHCI_RH_STOPPING
};
/* * Timer events, ordered by increasing delay length. * Always update event_delays_ns[] and event_handlers[] (defined in * ehci-timer.c) in parallel with this list.
*/ enum ehci_hrtimer_event {
EHCI_HRTIMER_POLL_ASS, /* Poll for async schedule off */
EHCI_HRTIMER_POLL_PSS, /* Poll for periodic schedule off */
EHCI_HRTIMER_POLL_DEAD, /* Wait for dead controller to stop */
EHCI_HRTIMER_UNLINK_INTR, /* Wait for interrupt QH unlink */
EHCI_HRTIMER_FREE_ITDS, /* Wait for unused iTDs and siTDs */
EHCI_HRTIMER_ACTIVE_UNLINK, /* Wait while unlinking an active QH */
EHCI_HRTIMER_START_UNLINK_INTR, /* Unlink empty interrupt QHs */
EHCI_HRTIMER_ASYNC_UNLINKS, /* Unlink empty async QHs */
EHCI_HRTIMER_IAA_WATCHDOG, /* Handle lost IAA interrupts */
EHCI_HRTIMER_DISABLE_PERIODIC, /* Wait to disable periodic sched */
EHCI_HRTIMER_DISABLE_ASYNC, /* Wait to disable async sched */
EHCI_HRTIMER_IO_WATCHDOG, /* Check for missing IRQs */
EHCI_HRTIMER_NUM_EVENTS /* Must come last */
}; #define EHCI_HRTIMER_NO_EVENT 99
struct ehci_hcd { /* one per controller */ /* timing support */ enum ehci_hrtimer_event next_hrtimer_event; unsigned enabled_hrtimer_events;
ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS]; struct hrtimer hrtimer;
int PSS_poll_count; int ASS_poll_count; int died_poll_count;
/* glue to PCI and HCD framework */ struct ehci_caps __iomem *caps; struct ehci_regs __iomem *regs; struct ehci_dbg_port __iomem *debug;
/* general schedule support */ bool scanning:1; bool need_rescan:1; bool intr_unlinking:1; bool iaa_in_progress:1; bool async_unlinking:1; bool shutdown:1; struct ehci_qh *qh_scan_next;
/* async schedule support */ struct ehci_qh *async; struct ehci_qh *dummy; /* For AMD quirk use */ struct list_head async_unlink; struct list_head async_idle; unsigned async_unlink_cycle; unsigned async_count; /* async activity count */
__hc32 old_current; /* Test for QH becoming */
__hc32 old_token; /* inactive during unlink */
/* periodic schedule support */ #define DEFAULT_I_TDPS 1024 /* some HCs can do less */ unsigned periodic_size;
__hc32 *periodic; /* hw periodic table */
dma_addr_t periodic_dma; struct list_head intr_qh_list; unsigned i_thresh; /* uframes HC might cache */
union ehci_shadow *pshadow; /* mirror hw periodic table */ struct list_head intr_unlink_wait; struct list_head intr_unlink; unsigned intr_unlink_wait_cycle; unsigned intr_unlink_cycle; unsigned now_frame; /* frame from HC hardware */ unsigned last_iso_frame; /* last frame scanned for iso */ unsigned intr_count; /* intr activity count */ unsigned isoc_count; /* isoc activity count */ unsigned periodic_count; /* periodic activity count */ unsigned uframe_periodic_max; /* max periodic time per uframe */
/* list of itds & sitds completed while now_frame was still active */ struct list_head cached_itd_list; struct ehci_itd *last_itd_to_free; struct list_head cached_sitd_list; struct ehci_sitd *last_sitd_to_free;
/* per root hub port */ unsignedlong reset_done[EHCI_MAX_ROOT_PORTS];
/* bit vectors (one bit per port) */ unsignedlong bus_suspended; /* which ports were
already suspended at the start of a bus suspend */ unsignedlong companion_ports; /* which ports are
dedicated to the companion controller */ unsignedlong owned_ports; /* which ports are
owned by the companion during a bus suspend */ unsignedlong port_c_suspend; /* which ports have
the change-suspend feature turned on */ unsignedlong suspended_ports; /* which ports are
suspended */ unsignedlong resuming_ports; /* which ports have
started to resume */
/* per-HC memory pools (could be per-bus, but ...) */ struct dma_pool *qh_pool; /* qh per active urb */ struct dma_pool *qtd_pool; /* one or more per qh */ struct dma_pool *itd_pool; /* itd per iso urb */ struct dma_pool *sitd_pool; /* sitd per split iso urb */
/* type tag from {qh,itd,sitd,fstn}->hw_next */ #define Q_NEXT_TYPE(ehci, dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
/* * Now the following defines are not converted using the * cpu_to_le32() macro anymore, since we have to support * "dynamic" switching between be and le support, so that the driver * can be used on one system with SoC EHCI controller using big-endian * descriptors as well as a normal little-endian PCI EHCI controller.
*/ /* values for that type tag */ #define Q_TYPE_ITD (0 << 1) #define Q_TYPE_QH (1 << 1) #define Q_TYPE_SITD (2 << 1) #define Q_TYPE_FSTN (3 << 1)
/* next async queue entry, or pointer to interrupt/periodic QH */ #define QH_NEXT(ehci, dma) \
(cpu_to_hc32(ehci, (((u32) dma) & ~0x01f) | Q_TYPE_QH))
/* for periodic/async schedules and qtd lists, mark end of list */ #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
/* * Entries in periodic shadow table are pointers to one of four kinds * of data structure. That's dictated by the hardware; a type tag is * encoded in the low bits of the hardware's periodic schedule. Use * Q_NEXT_TYPE to get the tag. * * For entries in the async schedule, the type tag always says "qh".
*/ union ehci_shadow { struct ehci_qh *qh; /* Q_TYPE_QH */ struct ehci_itd *itd; /* Q_TYPE_ITD */ struct ehci_sitd *sitd; /* Q_TYPE_SITD */ struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
__hc32 *hw_next; /* (all types) */ void *ptr;
};
/* * EHCI Specification 0.95 Section 3.6 * QH: describes control/bulk/interrupt endpoints * See Fig 3-7 "Queue Head Structure Layout". * * These appear in both the async and (for interrupt) periodic schedules.
*/
/* first part defined by EHCI spec */ struct ehci_qh_hw {
__hc32 hw_next; /* see EHCI 3.6.1 */
__hc32 hw_info1; /* see EHCI 3.6.2 */ #define QH_CONTROL_EP (1 << 27) /* FS/LS control endpoint */ #define QH_HEAD (1 << 15) /* Head of async reclamation list */ #define QH_TOGGLE_CTL (1 << 14) /* Data toggle control */ #define QH_HIGH_SPEED (2 << 12) /* Endpoint speed */ #define QH_LOW_SPEED (1 << 12) #define QH_FULL_SPEED (0 << 12) #define QH_INACTIVATE (1 << 7) /* Inactivate on next transaction */
__hc32 hw_info2; /* see EHCI 3.6.2 */ #define QH_SMASK 0x000000ff #define QH_CMASK 0x0000ff00 #define QH_HUBADDR 0x007f0000 #define QH_HUBPORT 0x3f800000 #define QH_MULT 0xc0000000
__hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
/* qtd overlay (hardware parts of a struct ehci_qtd) */
__hc32 hw_qtd_next;
__hc32 hw_alt_next;
__hc32 hw_token;
__hc32 hw_buf[5];
__hc32 hw_buf_hi[5];
} __aligned(32);
struct ehci_qh { struct ehci_qh_hw *hw; /* Must come first */ /* the rest is HCD-private */
dma_addr_t qh_dma; /* address of qh */ union ehci_shadow qh_next; /* ptr to qh; or periodic */ struct list_head qtd_list; /* sw qtd list */ struct list_head intr_node; /* list of intr QHs */ struct ehci_qtd *dummy; struct list_head unlink_node; struct ehci_per_sched ps; /* scheduling info */
unsigned unlink_cycle;
u8 qh_state; #define QH_STATE_LINKED 1 /* HC sees this */ #define QH_STATE_UNLINK 2 /* HC may still see this */ #define QH_STATE_IDLE 3 /* HC doesn't see this */ #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on unlink q */ #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
u8 unlink_reason; #define QH_UNLINK_HALTED 0x01 /* Halt flag is set */ #define QH_UNLINK_SHORT_READ 0x02 /* Recover from a short read */ #define QH_UNLINK_DUMMY_OVERLAY 0x04 /* QH overlayed the dummy TD */ #define QH_UNLINK_SHUTDOWN 0x08 /* The HC isn't running */ #define QH_UNLINK_QUEUE_EMPTY 0x10 /* Reached end of the queue */ #define QH_UNLINK_REQUESTED 0x20 /* Disable, reset, or dequeue */
u8 gap_uf; /* uframes split/csplit gap */
unsigned is_out:1; /* bulk or intr OUT */ unsigned clearing_tt:1; /* Clear-TT-Buf in progress */ unsigned dequeue_during_giveback:1; unsigned should_be_inactive:1;
};
/* description of one iso transaction (up to 3 KB data if highspeed) */ struct ehci_iso_packet { /* These will be copied to iTD when scheduling */
u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
__hc32 transaction; /* itd->hw_transaction[i] |= */
u8 cross; /* buf crosses pages */ /* for full speed OUT splits */
u32 buf1;
};
/* temporary schedule data for packets from iso urbs (both speeds) * each packet is one logical usb transaction to the device (not TT), * beginning at stream->next_uframe
*/ struct ehci_iso_sched { struct list_head td_list; unsigned span; unsigned first_packet; struct ehci_iso_packet packet[];
};
/* * ehci_iso_stream - groups all (s)itds for this endpoint. * acts like a qh would, if EHCI had them for ISO.
*/ struct ehci_iso_stream { /* first field matches ehci_qh, but is NULL */ struct ehci_qh_hw *hw;
u8 bEndpointAddress;
u8 highspeed; struct list_head td_list; /* queued itds/sitds */ struct list_head free_list; /* list of unused itds/sitds */
/* output of (re)scheduling */ struct ehci_per_sched ps; /* scheduling info */ unsigned next_uframe;
__hc32 splits;
/* the rest is derived from the endpoint descriptor, * including the extra info for hw_bufp[0..2]
*/
u16 uperiod; /* period in uframes */
u16 maxp; unsigned bandwidth;
/* This is used to initialize iTD's hw_bufp fields */
__hc32 buf0;
__hc32 buf1;
__hc32 buf2;
/* this is used to initialize sITD's tt info */
__hc32 address;
};
__hc32 hw_bufp[7]; /* see EHCI 3.3.3 */
__hc32 hw_bufp_hi[7]; /* Appendix B */
/* the rest is HCD-private */
dma_addr_t itd_dma; /* for this itd */ union ehci_shadow itd_next; /* ptr to periodic q entry */
struct urb *urb; struct ehci_iso_stream *stream; /* endpoint's queue */ struct list_head itd_list; /* list of stream's itds */
/* any/all hw_transactions here may be used by that urb */ unsigned frame; /* where scheduled */ unsigned pg; unsigned index[8]; /* in urb->iso_frame_desc */
} __aligned(32);
/* * EHCI Specification 0.96 Section 3.7 * Periodic Frame Span Traversal Node (FSTN) * * Manages split interrupt transactions (using TT) that span frame boundaries * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN * makes the HC jump (back) to a QH to scan for fs/ls QH completions until * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
*/ struct ehci_fstn {
__hc32 hw_next; /* any periodic q entry */
__hc32 hw_prev; /* qh or EHCI_LIST_END */
/* the rest is HCD-private */
dma_addr_t fstn_dma; union ehci_shadow fstn_next; /* ptr to periodic q entry */
} __aligned(32);
/* * USB-2.0 Specification Sections 11.14 and 11.18 * Scheduling and budgeting split transactions using TTs * * A hub can have a single TT for all its ports, or multiple TTs (one for each * port). The bandwidth and budgeting information for the full/low-speed bus * below each TT is self-contained and independent of the other TTs or the * high-speed bus. * * "Bandwidth" refers to the number of microseconds on the FS/LS bus allocated * to an interrupt or isochronous endpoint for each frame. "Budget" refers to * the best-case estimate of the number of full-speed bytes allocated to an * endpoint for each microframe within an allocated frame. * * Removal of an endpoint invalidates a TT's budget. Instead of trying to * keep an up-to-date record, we recompute the budget when it is needed.
*/
struct list_head tt_list; /* List of all ehci_tt's */ struct list_head ps_list; /* Items using this TT */ struct usb_tt *usb_tt; int tt_port; /* TT port number */
};
/* * Some EHCI controllers have a Transaction Translator built into the * root hub. This is a non-standard feature. Each controller will need * to add code to the following inline functions, and call them as * needed (mostly in root hub code).
*/
#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
/* Returns the speed of a device attached to a port on the root hub. */ staticinlineunsignedint
ehci_port_speed(struct ehci_hcd *ehci, unsignedint portsc)
{ if (ehci_is_TDI(ehci)) { switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) { case 0: return 0; case 1: return USB_PORT_STAT_LOW_SPEED; case 2: default: return USB_PORT_STAT_HIGH_SPEED;
}
} return USB_PORT_STAT_HIGH_SPEED;
}
#ifdef CONFIG_PPC_83xx /* Some Freescale processors have an erratum in which the TT * port number in the queue head was 0..N-1 instead of 1..N.
*/ #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug) #else #define ehci_has_fsl_portno_bug(e) (0) #endif
#define PORTSC_FSL_PFSC 24 /* Port Force Full-Speed Connect */
#ifdefined(CONFIG_PPC_85xx) /* Some Freescale processors have an erratum (USB A-005275) in which * incoming packets get corrupted in HS mode
*/ #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata) #else #define ehci_has_fsl_hs_errata(e) (0) #endif
/* * Some Freescale/NXP processors have an erratum (USB A-005697) * in which we need to wait for 10ms for bus to enter suspend mode * after setting SUSP bit.
*/ #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
/* * Some Freescale/NXP processors using ChipIdea IP have a bug in which * disabling the port (PE is cleared) does not cause PEC to be asserted * when frame babble is detected.
*/ #define ehci_has_ci_pec_bug(e, portsc) \
((e)->has_ci_pec_bug && ((e)->command & CMD_PSE) \
&& !(portsc & PORT_PEC) && !(portsc & PORT_PE))
/* * While most USB host controllers implement their registers in * little-endian format, a minority (celleb companion chip) implement * them in big endian format. * * This attempts to support either format at compile time without a * runtime penalty, or both formats with the additional overhead * of checking a flag bit. * * ehci_big_endian_capbase is a special quirk for controllers that * implement the HC capability registers as separate registers and not * as fields of a 32-bit register.
*/
/* * On certain ppc-44x SoC there is a HW issue, that could only worked around with * explicit suspend/operate of OHCI. This function hereby makes sense only on that arch. * Other common bits are dependent on has_amcc_usb23 quirk flag.
*/ #ifdef CONFIG_44x staticinlinevoid set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
{
u32 hc_control;
/* * The AMCC 440EPx not only implements its EHCI registers in big-endian * format, but also its DMA data structures (descriptors). * * EHCI controllers accessed through PCI work normally (little-endian * everywhere), so we won't bother supporting a BE-only mode for now.
*/ #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
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