// SPDX-License-Identifier: GPL-2.0 /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 2008 Cavium Networks * * Some parts of the code were originally released under BSD license: * * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights * reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following * disclaimer in the documentation and/or other materials provided * with the distribution. * * * Neither the name of Cavium Networks nor the names of * its contributors may be used to endorse or promote products * derived from this software without specific prior written * permission. * * This Software, including technical data, may be subject to U.S. export * control laws, including the U.S. Export Administration Act and its associated * regulations, and may be subject to export or import regulations in other * countries. * * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
*/
/** * enum cvmx_usb_speed - the possible USB device speeds * * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
*/ enum cvmx_usb_speed {
CVMX_USB_SPEED_HIGH = 0,
CVMX_USB_SPEED_FULL = 1,
CVMX_USB_SPEED_LOW = 2,
};
/** * enum cvmx_usb_transfer - the possible USB transfer types * * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status * transfers * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low * priority periodic transfers * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority * transfers * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority * periodic transfers
*/ enum cvmx_usb_transfer {
CVMX_USB_TRANSFER_CONTROL = 0,
CVMX_USB_TRANSFER_ISOCHRONOUS = 1,
CVMX_USB_TRANSFER_BULK = 2,
CVMX_USB_TRANSFER_INTERRUPT = 3,
};
/** * enum cvmx_usb_direction - the transfer directions * * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
*/ enum cvmx_usb_direction {
CVMX_USB_DIRECTION_OUT,
CVMX_USB_DIRECTION_IN,
};
/** * enum cvmx_usb_status - possible callback function status codes * * @CVMX_USB_STATUS_OK: The transaction / operation finished without * any errors * @CVMX_USB_STATUS_SHORT: FIXME: This is currently not implemented * @CVMX_USB_STATUS_CANCEL: The transaction was canceled while in flight * by a user call to cvmx_usb_cancel * @CVMX_USB_STATUS_ERROR: The transaction aborted with an unexpected * error status * @CVMX_USB_STATUS_STALL: The transaction received a USB STALL response * from the device * @CVMX_USB_STATUS_XACTERR: The transaction failed with an error from the * device even after a number of retries * @CVMX_USB_STATUS_DATATGLERR: The transaction failed with a data toggle * error even after a number of retries * @CVMX_USB_STATUS_BABBLEERR: The transaction failed with a babble error * @CVMX_USB_STATUS_FRAMEERR: The transaction failed with a frame error * even after a number of retries
*/ enum cvmx_usb_status {
CVMX_USB_STATUS_OK,
CVMX_USB_STATUS_SHORT,
CVMX_USB_STATUS_CANCEL,
CVMX_USB_STATUS_ERROR,
CVMX_USB_STATUS_STALL,
CVMX_USB_STATUS_XACTERR,
CVMX_USB_STATUS_DATATGLERR,
CVMX_USB_STATUS_BABBLEERR,
CVMX_USB_STATUS_FRAMEERR,
};
/** * struct cvmx_usb_port_status - the USB port status information * * @port_enabled: 1 = Usb port is enabled, 0 = disabled * @port_over_current: 1 = Over current detected, 0 = Over current not * detected. Octeon doesn't support over current detection. * @port_powered: 1 = Port power is being supplied to the device, 0 = * power is off. Octeon doesn't support turning port power * off. * @port_speed: Current port speed. * @connected: 1 = A device is connected to the port, 0 = No device is * connected. * @connect_change: 1 = Device connected state changed since the last set * status call.
*/ struct cvmx_usb_port_status {
u32 reserved : 25;
u32 port_enabled : 1;
u32 port_over_current : 1;
u32 port_powered : 1; enum cvmx_usb_speed port_speed : 2;
u32 connected : 1;
u32 connect_change : 1;
};
/** * struct cvmx_usb_iso_packet - descriptor for Isochronous packets * * @offset: This is the offset in bytes into the main buffer where this data * is stored. * @length: This is the length in bytes of the data. * @status: This is the status of this individual packet transfer.
*/ struct cvmx_usb_iso_packet { int offset; int length; enum cvmx_usb_status status;
};
/** * enum cvmx_usb_initialize_flags - flags used by the initialization function * * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal * as clock source at USB_XO and * USB_XI. * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V * board clock source at USB_XO. * USB_XI should be tied to GND. * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or * crystal * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for * data transfer use for the USB
*/ enum cvmx_usb_initialize_flags {
CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1 << 0,
CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1 << 1,
CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK = 3 << 3,
CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1 << 3,
CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2 << 3,
CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3 << 3, /* Bits 3-4 used to encode the clock frequency */
CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1 << 5,
};
/** * enum cvmx_usb_pipe_flags - internal flags for a pipe. * * @CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is * actively using hardware. * @CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high speed * pipe is in the ping state.
*/ enum cvmx_usb_pipe_flags {
CVMX_USB_PIPE_FLAGS_SCHEDULED = 1 << 17,
CVMX_USB_PIPE_FLAGS_NEED_PING = 1 << 18,
};
/* Maximum number of times to retry failed transactions */ #define MAX_RETRIES 3
/* Maximum number of hardware channels supported by the USB block */ #define MAX_CHANNELS 8
/* * The low level hardware can transfer a maximum of this number of bytes in each * transfer. The field is 19 bits wide
*/ #define MAX_TRANSFER_BYTES ((1 << 19) - 1)
/* * The low level hardware can transfer a maximum of this number of packets in * each transfer. The field is 10 bits wide
*/ #define MAX_TRANSFER_PACKETS ((1 << 10) - 1)
/** * Logical transactions may take numerous low level * transactions, especially when splits are concerned. This * enum represents all of the possible stages a transaction can * be in. Note that split completes are always even. This is so * the NAK handler can backup to the previous low level * transaction with a simple clearing of bit 0.
*/ enum cvmx_usb_stage {
CVMX_USB_STAGE_NON_CONTROL,
CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
CVMX_USB_STAGE_SETUP,
CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
CVMX_USB_STAGE_DATA,
CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
CVMX_USB_STAGE_STATUS,
CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
};
/** * struct cvmx_usb_transaction - describes each pending USB transaction * regardless of type. These are linked together * to form a list of pending requests for a pipe. * * @node: List node for transactions in the pipe. * @type: Type of transaction, duplicated of the pipe. * @flags: State flags for this transaction. * @buffer: User's physical buffer address to read/write. * @buffer_length: Size of the user's buffer in bytes. * @control_header: For control transactions, physical address of the 8 * byte standard header. * @iso_start_frame: For ISO transactions, the starting frame number. * @iso_number_packets: For ISO transactions, the number of packets in the * request. * @iso_packets: For ISO transactions, the sub packets in the request. * @actual_bytes: Actual bytes transfer for this transaction. * @stage: For control transactions, the current stage. * @urb: URB.
*/ struct cvmx_usb_transaction { struct list_head node; enum cvmx_usb_transfer type;
u64 buffer; int buffer_length;
u64 control_header; int iso_start_frame; int iso_number_packets; struct cvmx_usb_iso_packet *iso_packets; int xfersize; int pktcnt; int retries; int actual_bytes; enum cvmx_usb_stage stage; struct urb *urb;
};
/** * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon * and some USB device. It contains a list of pending * request to the device. * * @node: List node for pipe list * @next: Pipe after this one in the list * @transactions: List of pending transactions * @interval: For periodic pipes, the interval between packets in * frames * @next_tx_frame: The next frame this pipe is allowed to transmit on * @flags: State flags for this pipe * @device_speed: Speed of device connected to this pipe * @transfer_type: Type of transaction supported by this pipe * @transfer_dir: IN or OUT. Ignored for Control * @multi_count: Max packet in a row for the device * @max_packet: The device's maximum packet size in bytes * @device_addr: USB device address at other end of pipe * @endpoint_num: USB endpoint number at other end of pipe * @hub_device_addr: Hub address this device is connected to * @hub_port: Hub port this device is connected to * @pid_toggle: This toggles between 0/1 on every packet send to track * the data pid needed * @channel: Hardware DMA channel for this pipe * @split_sc_frame: The low order bits of the frame number the split * complete should be sent on
*/ struct cvmx_usb_pipe { struct list_head node; struct list_head transactions;
u64 interval;
u64 next_tx_frame; enum cvmx_usb_pipe_flags flags; enum cvmx_usb_speed device_speed; enum cvmx_usb_transfer transfer_type; enum cvmx_usb_direction transfer_dir; int multi_count;
u16 max_packet;
u8 device_addr;
u8 endpoint_num;
u8 hub_device_addr;
u8 hub_port;
u8 pid_toggle;
u8 channel;
s8 split_sc_frame;
};
struct cvmx_usb_tx_fifo { struct { int channel; int size;
u64 address;
} entry[MAX_CHANNELS + 1]; int head; int tail;
};
/** * struct octeon_hcd - the state of the USB block * * lock: Serialization lock. * init_flags: Flags passed to initialize. * index: Which USB block this is for. * idle_hardware_channels: Bit set for every idle hardware channel. * usbcx_hprt: Stored port status so we don't need to read a CSR to * determine splits. * pipe_for_channel: Map channels to pipes. * pipe: Storage for pipes. * indent: Used by debug output to indent functions. * port_status: Last port status used for change notification. * idle_pipes: List of open pipes that have no transactions. * active_pipes: Active pipes indexed by transfer type. * frame_number: Increments every SOF interrupt for time keeping. * active_split: Points to the current active split, or NULL.
*/ struct octeon_hcd {
spinlock_t lock; /* serialization lock */ int init_flags; int index; int idle_hardware_channels; union cvmx_usbcx_hprt usbcx_hprt; struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS]; int indent; struct cvmx_usb_port_status port_status; struct list_head idle_pipes; struct list_head active_pipes[4];
u64 frame_number; struct cvmx_usb_transaction *active_split; struct cvmx_usb_tx_fifo periodic; struct cvmx_usb_tx_fifo nonperiodic;
};
/* * This macro logically sets a single field in a CSR. It does the sequence * read, modify, and write
*/ #define USB_SET_FIELD32(address, _union, field, value) \ do { \ union _union c; \
\
c.u32 = cvmx_usb_read_csr32(usb, address); \
c.s.field = value; \
cvmx_usb_write_csr32(usb, address, c.u32); \
} while (0)
/* Returns the IO address to push/pop stuff data from the FIFOs */ #define USB_FIFO_ADDRESS(channel, usb_index) \
(CVMX_USBCX_GOTGCTL(usb_index) + ((channel) + 1) * 0x1000)
/** * struct octeon_temp_buffer - a bounce buffer for USB transfers * @orig_buffer: the original buffer passed by the USB stack * @data: the newly allocated temporary buffer (excluding meta-data) * * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If * the buffer is too short, we need to allocate a temporary one, and this struct * represents it.
*/ struct octeon_temp_buffer { void *orig_buffer;
u8 data[];
};
/** * Read a USB 32bit CSR. It performs the necessary address swizzle * for 32bit CSRs and logs the value in a readable format if * debugging is on. * * @usb: USB block this access is for * @address: 64bit address to read * * Returns: Result of the read
*/ staticinline u32 cvmx_usb_read_csr32(struct octeon_hcd *usb, u64 address)
{ return cvmx_read64_uint32(address ^ 4);
}
/** * Write a USB 32bit CSR. It performs the necessary address * swizzle for 32bit CSRs and logs the value in a readable format * if debugging is on. * * @usb: USB block this access is for * @address: 64bit address to write * @value: Value to write
*/ staticinlinevoid cvmx_usb_write_csr32(struct octeon_hcd *usb,
u64 address, u32 value)
{
cvmx_write64_uint32(address ^ 4, value);
cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
}
/** * Return non zero if this pipe connects to a non HIGH speed * device through a high speed hub. * * @usb: USB block this access is for * @pipe: Pipe to check * * Returns: Non zero if we need to do split transactions
*/ staticinlineint cvmx_usb_pipe_needs_split(struct octeon_hcd *usb, struct cvmx_usb_pipe *pipe)
{ return pipe->device_speed != CVMX_USB_SPEED_HIGH &&
usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH;
}
/** * Trivial utility function to return the correct PID for a pipe * * @pipe: pipe to check * * Returns: PID for pipe
*/ staticinlineint cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe)
{ if (pipe->pid_toggle) return 2; /* Data1 */ return 0; /* Data0 */
}
/* Loops through register until txfflsh or rxfflsh become zero.*/ staticint cvmx_wait_tx_rx(struct octeon_hcd *usb, int fflsh_type)
{ int result;
u64 address = CVMX_USBCX_GRSTCTL(usb->index);
u64 done = cvmx_get_cycle() + 100 *
(u64)octeon_get_clock_rate / 1000000; union cvmx_usbcx_grstctl c;
while (1) {
c.u32 = cvmx_usb_read_csr32(usb, address); if (fflsh_type == 0 && c.s.txfflsh == 0) {
result = 0; break;
} elseif (fflsh_type == 1 && c.s.rxfflsh == 0) {
result = 0; break;
} elseif (cvmx_get_cycle() > done) {
result = -1; break;
}
__delay(100);
} return result;
}
staticvoid cvmx_fifo_setup(struct octeon_hcd *usb)
{ union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3; union cvmx_usbcx_gnptxfsiz npsiz; union cvmx_usbcx_hptxfsiz psiz;
/* * Program the USBC_GRXFSIZ register to select the size of the receive * FIFO (25%).
*/
USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), cvmx_usbcx_grxfsiz,
rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4);
/* * Program the USBC_GNPTXFSIZ register to select the size and the start * address of the non-periodic transmit FIFO for nonperiodic * transactions (50%).
*/
npsiz.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
npsiz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
npsiz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), npsiz.u32);
/* * Program the USBC_HPTXFSIZ register to select the size and start * address of the periodic transmit FIFO for periodic transactions * (25%).
*/
psiz.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index));
psiz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
psiz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), psiz.u32);
/** * Shutdown a USB port after a call to cvmx_usb_initialize(). * The port should be disabled with all pipes closed when this * function is called. * * @usb: USB device state populated by cvmx_usb_initialize(). * * Returns: 0 or a negative error code.
*/ staticint cvmx_usb_shutdown(struct octeon_hcd *usb)
{ union cvmx_usbnx_clk_ctl usbn_clk_ctl;
/* Make sure all pipes are closed */ if (!list_empty(&usb->idle_pipes) ||
!list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS]) ||
!list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT]) ||
!list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_CONTROL]) ||
!list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_BULK])) return -EBUSY;
/* Disable the clocks and put them in power on reset */
usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index));
usbn_clk_ctl.s.enable = 1;
usbn_clk_ctl.s.por = 1;
usbn_clk_ctl.s.hclk_rst = 1;
usbn_clk_ctl.s.prst = 0;
usbn_clk_ctl.s.hrst = 0;
cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); return 0;
}
/** * Initialize a USB port for use. This must be called before any * other access to the Octeon USB port is made. The port starts * off in the disabled state. * * @dev: Pointer to struct device for logging purposes. * @usb: Pointer to struct octeon_hcd. * * Returns: 0 or a negative error code.
*/ staticint cvmx_usb_initialize(struct device *dev, struct octeon_hcd *usb)
{ int channel; int divisor; int retries = 0; union cvmx_usbcx_hcfg usbcx_hcfg; union cvmx_usbnx_clk_ctl usbn_clk_ctl; union cvmx_usbcx_gintsts usbc_gintsts; union cvmx_usbcx_gahbcfg usbcx_gahbcfg; union cvmx_usbcx_gintmsk usbcx_gintmsk; union cvmx_usbcx_gusbcfg usbcx_gusbcfg; union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status;
retry: /* * Power On Reset and PHY Initialization * * 1. Wait for DCOK to assert (nothing to do) * * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
*/
usbn_clk_ctl.u64 = cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb->index));
usbn_clk_ctl.s.por = 1;
usbn_clk_ctl.s.hrst = 0;
usbn_clk_ctl.s.prst = 0;
usbn_clk_ctl.s.hclk_rst = 0;
usbn_clk_ctl.s.enable = 0; /* * 2b. Select the USB reference clock/crystal parameters by writing * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
*/ if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) { /* * The USB port uses 12/24/48MHz 2.5V board clock * source at USB_XO. USB_XI should be tied to GND. * Most Octeon evaluation boards require this setting
*/ if (OCTEON_IS_MODEL(OCTEON_CN3XXX) ||
OCTEON_IS_MODEL(OCTEON_CN56XX) ||
OCTEON_IS_MODEL(OCTEON_CN50XX)) /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
usbn_clk_ctl.s.p_rtype = 2; /* p_rclk=1 & p_xenbn=0 */ else /* From CN52XX manual */
usbn_clk_ctl.s.p_rtype = 1;
switch (usb->init_flags &
CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) { case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
usbn_clk_ctl.s.p_c_sel = 0; break; case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
usbn_clk_ctl.s.p_c_sel = 1; break; case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
usbn_clk_ctl.s.p_c_sel = 2; break;
}
} else { /* * The USB port uses a 12MHz crystal as clock source * at USB_XO and USB_XI
*/ if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) /* From CN31XX,CN30XX manual */
usbn_clk_ctl.s.p_rtype = 3; /* p_rclk=1 & p_xenbn=1 */ else /* From CN56XX,CN52XX,CN50XX manuals. */
usbn_clk_ctl.s.p_rtype = 0;
usbn_clk_ctl.s.p_c_sel = 0;
} /* * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down * such that USB is as close as possible to 125Mhz
*/
divisor = DIV_ROUND_UP(octeon_get_clock_rate(), 125000000); /* Lower than 4 doesn't seem to work properly */ if (divisor < 4)
divisor = 4;
usbn_clk_ctl.s.divide = divisor;
usbn_clk_ctl.s.divide2 = 0;
cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
/* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
usbn_clk_ctl.s.hclk_rst = 1;
cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
__delay(64); /* * 3. Program the power-on reset field in the USBN clock-control * register: * USBN_CLK_CTL[POR] = 0
*/
usbn_clk_ctl.s.por = 0;
cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); /* 4. Wait 1 ms for PHY clock to start */
mdelay(1); /* * 5. Program the Reset input from automatic test equipment field in the * USBP control and status register: * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
*/
usbn_usbp_ctl_status.u64 =
cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index));
usbn_usbp_ctl_status.s.ate_reset = 1;
cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
usbn_usbp_ctl_status.u64); /* 6. Wait 10 cycles */
__delay(10); /* * 7. Clear ATE_RESET field in the USBN clock-control register: * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
*/
usbn_usbp_ctl_status.s.ate_reset = 0;
cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
usbn_usbp_ctl_status.u64); /* * 8. Program the PHY reset field in the USBN clock-control register: * USBN_CLK_CTL[PRST] = 1
*/
usbn_clk_ctl.s.prst = 1;
cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); /* * 9. Program the USBP control and status register to select host or * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for * device
*/
usbn_usbp_ctl_status.s.hst_mode = 0;
cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
usbn_usbp_ctl_status.u64); /* 10. Wait 1 us */
udelay(1); /* * 11. Program the hreset_n field in the USBN clock-control register: * USBN_CLK_CTL[HRST] = 1
*/
usbn_clk_ctl.s.hrst = 1;
cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64); /* 12. Proceed to USB core initialization */
usbn_clk_ctl.s.enable = 1;
cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
udelay(1);
/* * 3. Program the following fields in USBC_GUSBCFG register. * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
*/
usbcx_gusbcfg.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_GUSBCFG(usb->index));
usbcx_gusbcfg.s.toutcal = 0;
usbcx_gusbcfg.s.ddrsel = 0;
usbcx_gusbcfg.s.usbtrdtim = 0x5;
usbcx_gusbcfg.s.phylpwrclksel = 0;
cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
usbcx_gusbcfg.u32);
/* * 4. The software must unmask the following bits in the USBC_GINTMSK * register. * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
*/
usbcx_gintmsk.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_GINTMSK(usb->index));
usbcx_gintmsk.s.otgintmsk = 1;
usbcx_gintmsk.s.modemismsk = 1;
usbcx_gintmsk.s.hchintmsk = 1;
usbcx_gintmsk.s.sofmsk = 0; /* We need RX FIFO interrupts if we don't have DMA */ if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
usbcx_gintmsk.s.rxflvlmsk = 1;
cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
usbcx_gintmsk.u32);
/* * Disable all channel interrupts. We'll enable them per channel later.
*/ for (channel = 0; channel < 8; channel++)
cvmx_usb_write_csr32(usb,
CVMX_USBCX_HCINTMSKX(channel, usb->index),
0);
/* * Host Port Initialization * * 1. Program the host-port interrupt-mask field to unmask, * USBC_GINTMSK[PRTINT] = 1
*/
USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
cvmx_usbcx_gintmsk, prtintmsk, 1);
USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
cvmx_usbcx_gintmsk, disconnintmsk, 1);
/* * 2. Program the USBC_HCFG register to select full-speed host * or high-speed host.
*/
usbcx_hcfg.u32 = cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index));
usbcx_hcfg.s.fslssupp = 0;
usbcx_hcfg.s.fslspclksel = 0;
cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32);
cvmx_fifo_setup(usb);
/* * If the controller is getting port events right after the reset, it * means the initialization failed. Try resetting the controller again * in such case. This is seen to happen after cold boot on DSR-1000N.
*/
usbc_gintsts.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_GINTSTS(usb->index));
cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index),
usbc_gintsts.u32);
dev_dbg(dev, "gintsts after reset: 0x%x\n", (int)usbc_gintsts.u32); if (!usbc_gintsts.s.disconnint && !usbc_gintsts.s.prtint) return 0; if (retries++ >= 5) return -EAGAIN;
dev_info(dev, "controller reset failed (gintsts=0x%x) - retrying\n",
(int)usbc_gintsts.u32);
msleep(50);
cvmx_usb_shutdown(usb);
msleep(50); goto retry;
}
/** * Reset a USB port. After this call succeeds, the USB port is * online and servicing requests. * * @usb: USB device state populated by cvmx_usb_initialize().
*/ staticvoid cvmx_usb_reset_port(struct octeon_hcd *usb)
{
usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_HPRT(usb->index));
/* Program the port reset bit to start the reset process */
USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt,
prtrst, 1);
/* * Wait at least 50ms (high speed), or 10ms (full speed) for the reset * process to complete.
*/
mdelay(50);
/* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt,
prtrst, 0);
/* * Read the port speed field to get the enumerated speed, * USBC_HPRT[PRTSPD].
*/
usb->usbcx_hprt.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_HPRT(usb->index));
}
/** * Disable a USB port. After this call the USB port will not * generate data transfers and will not generate events. * Transactions in process will fail and call their * associated callbacks. * * @usb: USB device state populated by cvmx_usb_initialize(). * * Returns: 0 or a negative error code.
*/ staticint cvmx_usb_disable(struct octeon_hcd *usb)
{ /* Disable the port */
USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt,
prtena, 1); return 0;
}
/** * Get the current state of the USB port. Use this call to * determine if the usb port has anything connected, is enabled, * or has some sort of error condition. The return value of this * call has "changed" bits to signal of the value of some fields * have changed between calls. * * @usb: USB device state populated by cvmx_usb_initialize(). * * Returns: Port status information
*/ staticstruct cvmx_usb_port_status cvmx_usb_get_status(struct octeon_hcd *usb)
{ union cvmx_usbcx_hprt usbc_hprt; struct cvmx_usb_port_status result;
/** * Open a virtual pipe between the host and a USB device. A pipe * must be opened before data can be transferred between a device * and Octeon. * * @usb: USB device state populated by cvmx_usb_initialize(). * @device_addr: * USB device address to open the pipe to * (0-127). * @endpoint_num: * USB endpoint number to open the pipe to * (0-15). * @device_speed: * The speed of the device the pipe is going * to. This must match the device's speed, * which may be different than the port speed. * @max_packet: The maximum packet length the device can * transmit/receive (low speed=0-8, full * speed=0-1023, high speed=0-1024). This value * comes from the standard endpoint descriptor * field wMaxPacketSize bits <10:0>. * @transfer_type: * The type of transfer this pipe is for. * @transfer_dir: * The direction the pipe is in. This is not * used for control pipes. * @interval: For ISOCHRONOUS and INTERRUPT transfers, * this is how often the transfer is scheduled * for. All other transfers should specify * zero. The units are in frames (8000/sec at * high speed, 1000/sec for full speed). * @multi_count: * For high speed devices, this is the maximum * allowed number of packet per microframe. * Specify zero for non high speed devices. This * value comes from the standard endpoint descriptor * field wMaxPacketSize bits <12:11>. * @hub_device_addr: * Hub device address this device is connected * to. Devices connected directly to Octeon * use zero. This is only used when the device * is full/low speed behind a high speed hub. * The address will be of the high speed hub, * not and full speed hubs after it. * @hub_port: Which port on the hub the device is * connected. Use zero for devices connected * directly to Octeon. Like hub_device_addr, * this is only used for full/low speed * devices behind a high speed hub. * * Returns: A non-NULL value is a pipe. NULL means an error.
*/ staticstruct cvmx_usb_pipe *cvmx_usb_open_pipe(struct octeon_hcd *usb, int device_addr, int endpoint_num, enum cvmx_usb_speed
device_speed, int max_packet, enum cvmx_usb_transfer
transfer_type, enum cvmx_usb_direction
transfer_dir, int interval, int multi_count, int hub_device_addr, int hub_port)
{ struct cvmx_usb_pipe *pipe;
/* * All pipes use interval to rate limit NAK processing. Force an * interval if one wasn't supplied
*/ if (!interval)
interval = 1; if (cvmx_usb_pipe_needs_split(usb, pipe)) {
pipe->interval = interval * 8; /* Force start splits to be schedule on uFrame 0 */
pipe->next_tx_frame = ((usb->frame_number + 7) & ~7) +
pipe->interval;
} else {
pipe->interval = interval;
pipe->next_tx_frame = usb->frame_number + pipe->interval;
}
pipe->multi_count = multi_count;
pipe->hub_device_addr = hub_device_addr;
pipe->hub_port = hub_port;
pipe->pid_toggle = 0;
pipe->split_sc_frame = -1;
list_add_tail(&pipe->node, &usb->idle_pipes);
/* * We don't need to tell the hardware about this pipe yet since * it doesn't have any submitted requests
*/
return pipe;
}
/** * Poll the RX FIFOs and remove data as needed. This function is only used * in non DMA mode. It is very important that this function be called quickly * enough to prevent FIFO overflow. * * @usb: USB device state populated by cvmx_usb_initialize().
*/ staticvoid cvmx_usb_poll_rx_fifo(struct octeon_hcd *usb)
{ union cvmx_usbcx_grxstsph rx_status; int channel; int bytes;
u64 address;
u32 *ptr;
rx_status.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_GRXSTSPH(usb->index)); /* Only read data if IN data is there */ if (rx_status.s.pktsts != 2) return; /* Check if no data is available */ if (!rx_status.s.bcnt) return;
channel = rx_status.s.chnum;
bytes = rx_status.s.bcnt; if (!bytes) return;
/* Get where the DMA engine would have written this data */
address = cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index) +
channel * 8);
/* Loop writing the FIFO data for this packet into memory */ while (bytes > 0) {
*ptr++ = cvmx_usb_read_csr32(usb,
USB_FIFO_ADDRESS(channel, usb->index));
bytes -= 4;
}
CVMX_SYNCW;
}
/** * Fill the TX hardware fifo with data out of the software * fifos * * @usb: USB device state populated by cvmx_usb_initialize(). * @fifo: Software fifo to use * @available: Amount of space in the hardware fifo * * Returns: Non zero if the hardware fifo was too small and needs * to be serviced again.
*/ staticint cvmx_usb_fill_tx_hw(struct octeon_hcd *usb, struct cvmx_usb_tx_fifo *fifo, int available)
{ /* * We're done either when there isn't anymore space or the software FIFO * is empty
*/ while (available && (fifo->head != fifo->tail)) { int i = fifo->tail; const u32 *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
u64 csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel,
usb->index) ^ 4; int words = available;
/* Limit the amount of data to what the SW fifo has */ if (fifo->entry[i].size <= available) {
words = fifo->entry[i].size;
fifo->tail++; if (fifo->tail > MAX_CHANNELS)
fifo->tail = 0;
}
/* Update the next locations and counts */
available -= words;
fifo->entry[i].address += words * 4;
fifo->entry[i].size -= words;
/* * Write the HW fifo data. The read every three writes is due * to an errata on CN3XXX chips
*/ while (words > 3) {
cvmx_write64_uint32(csr_address, *ptr++);
cvmx_write64_uint32(csr_address, *ptr++);
cvmx_write64_uint32(csr_address, *ptr++);
cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
words -= 3;
}
cvmx_write64_uint32(csr_address, *ptr++); if (--words) {
cvmx_write64_uint32(csr_address, *ptr++); if (--words)
cvmx_write64_uint32(csr_address, *ptr++);
}
cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
} return fifo->head != fifo->tail;
}
/** * Check the hardware FIFOs and fill them as needed * * @usb: USB device state populated by cvmx_usb_initialize().
*/ staticvoid cvmx_usb_poll_tx_fifo(struct octeon_hcd *usb)
{ if (usb->periodic.head != usb->periodic.tail) { union cvmx_usbcx_hptxsts tx_status;
/** * Fill the TX FIFO with an outgoing packet * * @usb: USB device state populated by cvmx_usb_initialize(). * @channel: Channel number to get packet from
*/ staticvoid cvmx_usb_fill_tx_fifo(struct octeon_hcd *usb, int channel)
{ union cvmx_usbcx_hccharx hcchar; union cvmx_usbcx_hcspltx usbc_hcsplt; union cvmx_usbcx_hctsizx usbc_hctsiz; struct cvmx_usb_tx_fifo *fifo;
/* We only need to fill data on outbound channels */
hcchar.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_HCCHARX(channel, usb->index)); if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT) return;
/* OUT Splits only have data on the start and not the complete */
usbc_hcsplt.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_HCSPLTX(channel, usb->index)); if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt) return;
/* * Find out how many bytes we need to fill and convert it into 32bit * words.
*/
usbc_hctsiz.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_HCTSIZX(channel, usb->index)); if (!usbc_hctsiz.s.xfersize) return;
/** * Perform channel specific setup for Control transactions. All * the generic stuff will already have been done in cvmx_usb_start_channel(). * * @usb: USB device state populated by cvmx_usb_initialize(). * @channel: Channel to setup * @pipe: Pipe for control transaction
*/ staticvoid cvmx_usb_start_channel_control(struct octeon_hcd *usb, int channel, struct cvmx_usb_pipe *pipe)
{ struct usb_hcd *hcd = octeon_to_hcd(usb); struct device *dev = hcd->self.controller; struct cvmx_usb_transaction *transaction =
list_first_entry(&pipe->transactions, typeof(*transaction),
node); struct usb_ctrlrequest *header =
cvmx_phys_to_ptr(transaction->control_header); int bytes_to_transfer = transaction->buffer_length -
transaction->actual_bytes; int packets_to_transfer; union cvmx_usbcx_hctsizx usbc_hctsiz;
switch (transaction->stage) { case CVMX_USB_STAGE_NON_CONTROL: case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
dev_err(dev, "%s: ERROR - Non control stage\n", __func__); break; case CVMX_USB_STAGE_SETUP:
usbc_hctsiz.s.pid = 3; /* Setup */
bytes_to_transfer = sizeof(*header); /* All Control operations start with a setup going OUT */
USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
cvmx_usbcx_hccharx, epdir,
CVMX_USB_DIRECTION_OUT); /* * Setup send the control header instead of the buffer data. The * buffer data will be used in the next stage
*/
cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) +
channel * 8,
transaction->control_header); break; case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
usbc_hctsiz.s.pid = 3; /* Setup */
bytes_to_transfer = 0; /* All Control operations start with a setup going OUT */
USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
cvmx_usbcx_hccharx, epdir,
CVMX_USB_DIRECTION_OUT);
/* * Make sure the transfer never exceeds the byte limit of the hardware. * Further bytes will be sent as continued transactions
*/ if (bytes_to_transfer > MAX_TRANSFER_BYTES) { /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
bytes_to_transfer *= pipe->max_packet;
}
/* * Calculate the number of packets to transfer. If the length is zero * we still need to transfer one packet
*/
packets_to_transfer = DIV_ROUND_UP(bytes_to_transfer,
pipe->max_packet); if (packets_to_transfer == 0) {
packets_to_transfer = 1;
} elseif ((packets_to_transfer > 1) &&
(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) { /* * Limit to one packet when not using DMA. Channels must be * restarted between every packet for IN transactions, so there * is no reason to do multiple packets in a row
*/
packets_to_transfer = 1;
bytes_to_transfer = packets_to_transfer * pipe->max_packet;
} elseif (packets_to_transfer > MAX_TRANSFER_PACKETS) { /* * Limit the number of packet and data transferred to what the * hardware can handle
*/
packets_to_transfer = MAX_TRANSFER_PACKETS;
bytes_to_transfer = packets_to_transfer * pipe->max_packet;
}
/** * Start a channel to perform the pipe's head transaction * * @usb: USB device state populated by cvmx_usb_initialize(). * @channel: Channel to setup * @pipe: Pipe to start
*/ staticvoid cvmx_usb_start_channel(struct octeon_hcd *usb, int channel, struct cvmx_usb_pipe *pipe)
{ struct cvmx_usb_transaction *transaction =
list_first_entry(&pipe->transactions, typeof(*transaction),
node);
/* Make sure all writes to the DMA region get flushed */
CVMX_SYNCW;
/* Attach the channel to the pipe */
usb->pipe_for_channel[channel] = pipe;
pipe->channel = channel;
pipe->flags |= CVMX_USB_PIPE_FLAGS_SCHEDULED;
/* Mark this channel as in use */
usb->idle_hardware_channels &= ~(1 << channel);
/* Enable the channel interrupt bits */
{ union cvmx_usbcx_hcintx usbc_hcint; union cvmx_usbcx_hcintmskx usbc_hcintmsk; union cvmx_usbcx_haintmsk usbc_haintmsk;
/* Clear all channel status bits */
usbc_hcint.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_HCINTX(channel, usb->index));
/* Setup both the size of the transfer and the SPLIT characteristics */
{ union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0}; union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0}; int packets_to_transfer; int bytes_to_transfer = transaction->buffer_length -
transaction->actual_bytes;
/* * ISOCHRONOUS transactions store each individual transfer size * in the packet structure, not the global buffer_length
*/ if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
bytes_to_transfer =
transaction->iso_packets[0].length -
transaction->actual_bytes;
/* * We need to do split transactions when we are talking to non * high speed devices that are behind a high speed hub
*/ if (cvmx_usb_pipe_needs_split(usb, pipe)) { /* * On the start split phase (stage is even) record the * frame number we will need to send the split complete. * We only store the lower two bits since the time ahead * can only be two frames
*/ if ((transaction->stage & 1) == 0) { if (transaction->type == CVMX_USB_TRANSFER_BULK)
pipe->split_sc_frame =
(usb->frame_number + 1) & 0x7f; else
pipe->split_sc_frame =
(usb->frame_number + 2) & 0x7f;
} else {
pipe->split_sc_frame = -1;
}
/* * SPLIT transactions can only ever transmit one data * packet so limit the transfer size to the max packet * size
*/ if (bytes_to_transfer > pipe->max_packet)
bytes_to_transfer = pipe->max_packet;
/* * ISOCHRONOUS OUT splits are unique in that they limit * data transfers to 188 byte chunks representing the * begin/middle/end of the data or all
*/ if (!usbc_hcsplt.s.compsplt &&
(pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
(pipe->transfer_type ==
CVMX_USB_TRANSFER_ISOCHRONOUS)) { /* * Clear the split complete frame number as * there isn't going to be a split complete
*/
pipe->split_sc_frame = -1; /* * See if we've started this transfer and sent * data
*/ if (transaction->actual_bytes == 0) { /* * Nothing sent yet, this is either a * begin or the entire payload
*/ if (bytes_to_transfer <= 188) /* Entire payload in one go */
usbc_hcsplt.s.xactpos = 3; else /* First part of payload */
usbc_hcsplt.s.xactpos = 2;
} else { /* * Continuing the previous data, we must * either be in the middle or at the end
*/ if (bytes_to_transfer <= 188) /* End of payload */
usbc_hcsplt.s.xactpos = 1; else /* Middle of payload */
usbc_hcsplt.s.xactpos = 0;
} /* * Again, the transfer size is limited to 188 * bytes
*/ if (bytes_to_transfer > 188)
bytes_to_transfer = 188;
}
}
/* * Make sure the transfer never exceeds the byte limit of the * hardware. Further bytes will be sent as continued * transactions
*/ if (bytes_to_transfer > MAX_TRANSFER_BYTES) { /* * Round MAX_TRANSFER_BYTES to a multiple of out packet * size
*/
bytes_to_transfer = MAX_TRANSFER_BYTES /
pipe->max_packet;
bytes_to_transfer *= pipe->max_packet;
}
/* * Calculate the number of packets to transfer. If the length is * zero we still need to transfer one packet
*/
packets_to_transfer =
DIV_ROUND_UP(bytes_to_transfer, pipe->max_packet); if (packets_to_transfer == 0) {
packets_to_transfer = 1;
} elseif ((packets_to_transfer > 1) &&
(usb->init_flags &
CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) { /* * Limit to one packet when not using DMA. Channels must * be restarted between every packet for IN * transactions, so there is no reason to do multiple * packets in a row
*/
packets_to_transfer = 1;
bytes_to_transfer = packets_to_transfer *
pipe->max_packet;
} elseif (packets_to_transfer > MAX_TRANSFER_PACKETS) { /* * Limit the number of packet and data transferred to * what the hardware can handle
*/
packets_to_transfer = MAX_TRANSFER_PACKETS;
bytes_to_transfer = packets_to_transfer *
pipe->max_packet;
}
/* Update the DATA0/DATA1 toggle */
usbc_hctsiz.s.pid = cvmx_usb_get_data_pid(pipe); /* * High speed pipes may need a hardware ping before they start
*/ if (pipe->flags & CVMX_USB_PIPE_FLAGS_NEED_PING)
usbc_hctsiz.s.dopng = 1;
/* Setup the Host Channel Characteristics Register */
{ union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0};
/* * Set the startframe odd/even properly. This is only used for * periodic
*/
usbc_hcchar.s.oddfrm = usb->frame_number & 1;
/* * Set the number of back to back packets allowed by this * endpoint. Split transactions interpret "ec" as the number of * immediate retries of failure. These retries happen too * quickly, so we disable these entirely for splits
*/ if (cvmx_usb_pipe_needs_split(usb, pipe))
usbc_hcchar.s.ec = 1; elseif (pipe->multi_count < 1)
usbc_hcchar.s.ec = 1; elseif (pipe->multi_count > 3)
usbc_hcchar.s.ec = 3; else
usbc_hcchar.s.ec = pipe->multi_count;
/* Set the rest of the endpoint specific settings */
usbc_hcchar.s.devaddr = pipe->device_addr;
usbc_hcchar.s.eptype = transaction->type;
usbc_hcchar.s.lspddev =
(pipe->device_speed == CVMX_USB_SPEED_LOW);
usbc_hcchar.s.epdir = pipe->transfer_dir;
usbc_hcchar.s.epnum = pipe->endpoint_num;
usbc_hcchar.s.mps = pipe->max_packet;
cvmx_usb_write_csr32(usb,
CVMX_USBCX_HCCHARX(channel, usb->index),
usbc_hcchar.u32);
}
/* Do transaction type specific fixups as needed */ switch (transaction->type) { case CVMX_USB_TRANSFER_CONTROL:
cvmx_usb_start_channel_control(usb, channel, pipe); break; case CVMX_USB_TRANSFER_BULK: case CVMX_USB_TRANSFER_INTERRUPT: break; case CVMX_USB_TRANSFER_ISOCHRONOUS: if (!cvmx_usb_pipe_needs_split(usb, pipe)) { /* * ISO transactions require different PIDs depending on * direction and how many packets are needed
*/ if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) { if (pipe->multi_count < 2) /* Need DATA0 */
USB_SET_FIELD32(
CVMX_USBCX_HCTSIZX(channel,
usb->index),
cvmx_usbcx_hctsizx, pid, 0); else/* Need MDATA */
USB_SET_FIELD32(
CVMX_USBCX_HCTSIZX(channel,
usb->index),
cvmx_usbcx_hctsizx, pid, 3);
}
} break;
}
{ union cvmx_usbcx_hctsizx usbc_hctsiz = { .u32 =
cvmx_usb_read_csr32(usb,
CVMX_USBCX_HCTSIZX(channel,
usb->index))
};
transaction->xfersize = usbc_hctsiz.s.xfersize;
transaction->pktcnt = usbc_hctsiz.s.pktcnt;
} /* Remember when we start a split transaction */ if (cvmx_usb_pipe_needs_split(usb, pipe))
usb->active_split = transaction;
USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
cvmx_usbcx_hccharx, chena, 1); if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
cvmx_usb_fill_tx_fifo(usb, channel);
}
/** * Find a pipe that is ready to be scheduled to hardware. * @usb: USB device state populated by cvmx_usb_initialize(). * @xfer_type: Transfer type * * Returns: Pipe or NULL if none are ready
*/ staticstruct cvmx_usb_pipe *cvmx_usb_find_ready_pipe(struct octeon_hcd *usb, enum cvmx_usb_transfer xfer_type)
{ struct list_head *list = usb->active_pipes + xfer_type;
u64 current_frame = usb->frame_number; struct cvmx_usb_pipe *pipe;
/* Find a pipe needing service. */ if (is_sof) { /* * Only process periodic pipes on SOF interrupts. This way we * are sure that the periodic data is sent in the beginning of * the frame.
*/
pipe = cvmx_usb_find_ready_pipe(usb,
CVMX_USB_TRANSFER_ISOCHRONOUS); if (pipe) return pipe;
pipe = cvmx_usb_find_ready_pipe(usb,
CVMX_USB_TRANSFER_INTERRUPT); if (pipe) return pipe;
}
pipe = cvmx_usb_find_ready_pipe(usb, CVMX_USB_TRANSFER_CONTROL); if (pipe) return pipe; return cvmx_usb_find_ready_pipe(usb, CVMX_USB_TRANSFER_BULK);
}
/** * Called whenever a pipe might need to be scheduled to the * hardware. * * @usb: USB device state populated by cvmx_usb_initialize(). * @is_sof: True if this schedule was called on a SOF interrupt.
*/ staticvoid cvmx_usb_schedule(struct octeon_hcd *usb, int is_sof)
{ int channel; struct cvmx_usb_pipe *pipe; int need_sof; enum cvmx_usb_transfer ttype;
if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) { /* * Without DMA we need to be careful to not schedule something * at the end of a frame and cause an overrun.
*/ union cvmx_usbcx_hfnum hfnum = {
.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_HFNUM(usb->index))
};
union cvmx_usbcx_hfir hfir = {
.u32 = cvmx_usb_read_csr32(usb,
CVMX_USBCX_HFIR(usb->index))
};
if (hfnum.s.frrem < hfir.s.frint / 4) goto done;
}
while (usb->idle_hardware_channels) { /* Find an idle channel */
channel = __fls(usb->idle_hardware_channels); if (unlikely(channel > 7)) break;
pipe = cvmx_usb_next_pipe(usb, is_sof); if (!pipe) break;
cvmx_usb_start_channel(usb, channel, pipe);
}
done: /* * Only enable SOF interrupts when we have transactions pending in the * future that might need to be scheduled
*/
need_sof = 0; for (ttype = CVMX_USB_TRANSFER_CONTROL;
ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
list_for_each_entry(pipe, &usb->active_pipes[ttype], node) { if (pipe->next_tx_frame > usb->frame_number) {
need_sof = 1; break;
}
}
}
USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
cvmx_usbcx_gintmsk, sofmsk, need_sof);
}
/* For Isochronous transactions we need to update the URB packet status * list from data in our private copy
*/ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { int i; /* * The pointer to the private list is stored in the setup_packet * field.
*/ struct cvmx_usb_iso_packet *iso_packet =
(struct cvmx_usb_iso_packet *)urb->setup_packet; /* Recalculate the transfer size by adding up each packet */
urb->actual_length = 0; for (i = 0; i < urb->number_of_packets; i++) { if (iso_packet[i].status == CVMX_USB_STATUS_OK) {
urb->iso_frame_desc[i].status = 0;
urb->iso_frame_desc[i].actual_length =
iso_packet[i].length;
urb->actual_length +=
urb->iso_frame_desc[i].actual_length;
} else {
dev_dbg(dev, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
i, urb->number_of_packets,
iso_packet[i].status, pipe,
transaction, iso_packet[i].length);
urb->iso_frame_desc[i].status = -EREMOTEIO;
}
} /* Free the private list now that we don't need it anymore */
kfree(iso_packet);
urb->setup_packet = NULL;
}
switch (status) { case CVMX_USB_STATUS_OK:
urb->status = 0; break; case CVMX_USB_STATUS_CANCEL: if (urb->status == 0)
urb->status = -ENOENT; break; case CVMX_USB_STATUS_STALL:
dev_dbg(dev, "status=stall pipe=%p transaction=%p size=%d\n",
pipe, transaction, bytes_transferred);
urb->status = -EPIPE; break; case CVMX_USB_STATUS_BABBLEERR:
dev_dbg(dev, "status=babble pipe=%p transaction=%p size=%d\n",
pipe, transaction, bytes_transferred);
urb->status = -EPIPE; break; case CVMX_USB_STATUS_SHORT:
dev_dbg(dev, "status=short pipe=%p transaction=%p size=%d\n",
pipe, transaction, bytes_transferred);
urb->status = -EREMOTEIO; break; case CVMX_USB_STATUS_ERROR: case CVMX_USB_STATUS_XACTERR: case CVMX_USB_STATUS_DATATGLERR: case CVMX_USB_STATUS_FRAMEERR:
dev_dbg(dev, "status=%d pipe=%p transaction=%p size=%d\n",
status, pipe, transaction, bytes_transferred);
urb->status = -EPROTO; break;
}
usb_hcd_unlink_urb_from_ep(octeon_to_hcd(usb), urb);
spin_unlock(&usb->lock);
usb_hcd_giveback_urb(octeon_to_hcd(usb), urb, urb->status);
spin_lock(&usb->lock);
}
/** * Signal the completion of a transaction and free it. The * transaction will be removed from the pipe transaction list. * * @usb: USB device state populated by cvmx_usb_initialize(). * @pipe: Pipe the transaction is on * @transaction: * Transaction that completed * @complete_code: * Completion code
*/ staticvoid cvmx_usb_complete(struct octeon_hcd *usb, struct cvmx_usb_pipe *pipe, struct cvmx_usb_transaction *transaction, enum cvmx_usb_status complete_code)
{ /* If this was a split then clear our split in progress marker */ if (usb->active_split == transaction)
usb->active_split = NULL;
/* * Isochronous transactions need extra processing as they might not be * done after a single data transfer
*/ if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) { /* Update the number of bytes transferred in this ISO packet */
transaction->iso_packets[0].length = transaction->actual_bytes;
transaction->iso_packets[0].status = complete_code;
/* * If there are more ISOs pending and we succeeded, schedule the * next one
*/ if ((transaction->iso_number_packets > 1) &&
(complete_code == CVMX_USB_STATUS_OK)) { /* No bytes transferred for this packet as of yet */
transaction->actual_bytes = 0; /* One less ISO waiting to transfer */
transaction->iso_number_packets--; /* Increment to the next location in our packet array */
transaction->iso_packets++;
transaction->stage = CVMX_USB_STAGE_NON_CONTROL; return;
}
}
/* Remove the transaction from the pipe list */
--> --------------------
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