/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */ staticint link_quirk;
module_param(link_quirk, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
staticunsignedlonglong quirks;
module_param(quirks, ullong, S_IRUGO);
MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
xhci_for_each_ring_seg(ring->first_seg, seg) { if (seg == td->start_seg) returntrue;
}
returnfalse;
}
/* * xhci_handshake - spin reading hc until handshake completes or fails * @ptr: address of hc register to be read * @mask: bits to look at in result of read * @done: value of those bits when handshake succeeds * @usec: timeout in microseconds * * Returns negative errno, or zero on success * * Success happens when the "mask" bits have the specified value (hardware * handshake done). There are two failure modes: "usec" have passed (major * hardware flakeout), or the register reads as all-ones (hardware removed).
*/ int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us)
{
u32 result; int ret;
ret = readl_poll_timeout_atomic(ptr, result,
(result & mask) == done ||
result == U32_MAX,
1, timeout_us); if (result == U32_MAX) /* card removed */ return -ENODEV;
return ret;
}
/* * Disable interrupts and begin the xHCI halting process.
*/ void xhci_quiesce(struct xhci_hcd *xhci)
{
u32 halted;
u32 cmd;
u32 mask;
/* * Force HC into halt state. * * Disable any IRQs and clear the run/stop bit. * HC will complete any current and actively pipelined transactions, and * should halt within 16 ms of the run/stop bit being cleared. * Read HC Halted bit in the status register to see when the HC is finished.
*/ int xhci_halt(struct xhci_hcd *xhci)
{ int ret;
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
xhci_quiesce(xhci);
ret = xhci_handshake(&xhci->op_regs->status,
STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC); if (ret) { if (!(xhci->xhc_state & XHCI_STATE_DYING))
xhci_warn(xhci, "Host halt failed, %d\n", ret); return ret;
}
/* * Wait for the HCHalted Status bit to be 0 to indicate the host is * running.
*/
ret = xhci_handshake(&xhci->op_regs->status,
STS_HALT, 0, XHCI_MAX_HALT_USEC); if (ret == -ETIMEDOUT)
xhci_err(xhci, "Host took too long to start, " "waited %u microseconds.\n",
XHCI_MAX_HALT_USEC); if (!ret) { /* clear state flags. Including dying, halted or removing */
xhci->xhc_state = 0;
xhci->run_graceperiod = jiffies + msecs_to_jiffies(500);
}
return ret;
}
/* * Reset a halted HC. * * This resets pipelines, timers, counters, state machines, etc. * Transactions will be terminated immediately, and operational registers * will be set to their defaults.
*/ int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us)
{
u32 command;
u32 state; int ret;
state = readl(&xhci->op_regs->status);
if (state == ~(u32)0) { if (!(xhci->xhc_state & XHCI_STATE_DYING))
xhci_warn(xhci, "Host not accessible, reset failed.\n"); return -ENODEV;
}
if ((state & STS_HALT) == 0) {
xhci_warn(xhci, "Host controller not halted, aborting reset.\n"); return 0;
}
/* Existing Intel xHCI controllers require a delay of 1 mS, * after setting the CMD_RESET bit, and before accessing any * HC registers. This allows the HC to complete the * reset operation and be ready for HC register access. * Without this delay, the subsequent HC register access, * may result in a system hang very rarely.
*/ if (xhci->quirks & XHCI_INTEL_HOST)
udelay(1000);
ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, timeout_us); if (ret) return ret;
if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Wait for controller to be ready for doorbell rings"); /* * xHCI cannot write to any doorbells or operational registers other * than status until the "Controller Not Ready" flag is cleared.
*/
ret = xhci_handshake(&xhci->op_regs->status, STS_CNR, 0, timeout_us);
/* * Some Renesas controllers get into a weird state if they are * reset while programmed with 64bit addresses (they will preserve * the top half of the address in internal, non visible * registers). You end up with half the address coming from the * kernel, and the other half coming from the firmware. Also, * changing the programming leads to extra accesses even if the * controller is supposed to be halted. The controller ends up with * a fatal fault, and is then ripe for being properly reset. * * Special care is taken to only apply this if the device is behind * an iommu. Doing anything when there is no iommu is definitely * unsafe...
*/
domain = iommu_get_domain_for_dev(dev); if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !domain ||
domain->type == IOMMU_DOMAIN_IDENTITY) return;
xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
/* Clear HSEIE so that faults do not get signaled */
val = readl(&xhci->op_regs->command);
val &= ~CMD_HSEIE;
writel(val, &xhci->op_regs->command);
/* Clear HSE (aka FATAL) */
val = readl(&xhci->op_regs->status);
val |= STS_FATAL;
writel(val, &xhci->op_regs->status);
/* Now zero the registers, and brace for impact */
val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr); if (upper_32_bits(val))
xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring); if (upper_32_bits(val))
xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
for (i = 0; i < intrs; i++) { struct xhci_intr_reg __iomem *ir;
ir = &xhci->run_regs->ir_set[i];
val = xhci_read_64(xhci, &ir->erst_base); if (upper_32_bits(val))
xhci_write_64(xhci, 0, &ir->erst_base);
val= xhci_read_64(xhci, &ir->erst_dequeue); if (upper_32_bits(val))
xhci_write_64(xhci, 0, &ir->erst_dequeue);
}
/* Wait for the fault to appear. It will be cleared on reset */
err = xhci_handshake(&xhci->op_regs->status,
STS_FATAL, STS_FATAL,
XHCI_MAX_HALT_USEC); if (!err)
xhci_info(xhci, "Fault detected\n");
}
int xhci_enable_interrupter(struct xhci_interrupter *ir)
{
u32 iman;
if (!ir || !ir->ir_set) return -EINVAL;
iman = readl(&ir->ir_set->iman);
iman &= ~IMAN_IP;
iman |= IMAN_IE;
writel(iman, &ir->ir_set->iman);
/* Read operation to guarantee the write has been flushed from posted buffers */
readl(&ir->ir_set->iman); return 0;
}
int xhci_disable_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir)
{
u32 iman;
if (!ir || !ir->ir_set) return -EINVAL;
iman = readl(&ir->ir_set->iman);
iman &= ~IMAN_IP;
iman &= ~IMAN_IE;
writel(iman, &ir->ir_set->iman);
iman = readl(&ir->ir_set->iman); if (iman & IMAN_IP)
xhci_dbg(xhci, "%s: Interrupt pending\n", __func__);
return 0;
}
/* interrupt moderation interval imod_interval in nanoseconds */ int xhci_set_interrupter_moderation(struct xhci_interrupter *ir,
u32 imod_interval)
{
u32 imod;
if (!ir || !ir->ir_set) return -EINVAL;
/* IMODI value in IMOD register is in 250ns increments */
imod_interval = umin(imod_interval / 250, IMODI_MASK);
imod = readl(&ir->ir_set->imod);
imod &= ~IMODI_MASK;
imod |= imod_interval;
writel(imod, &ir->ir_set->imod);
/* * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver * that causes ports behind that hardware to enter compliance mode sometimes. * The quirk creates a timer that polls every 2 seconds the link state of * each host controller's port and recovers it by issuing a Warm reset * if Compliance mode is detected, otherwise the port will become "dead" (no * device connections or disconnections will be detected anymore). Becasue no * status event is generated when entering compliance mode (per xhci spec), * this quirk is needed on systems that have the failing hardware installed.
*/ staticvoid compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
{
xhci->port_status_u0 = 0;
timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
0);
xhci->comp_mode_recovery_timer.expires = jiffies +
msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
/* * This function identifies the systems that have installed the SN65LVPE502CP * USB3.0 re-driver and that need the Compliance Mode Quirk. * Systems: * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
*/ staticbool xhci_compliance_mode_recovery_timer_quirk_check(void)
{ constchar *dmi_product_name, *dmi_sys_vendor;
offset = readl(&xhci->cap_regs->db_off) & DBOFF_MASK;
xhci->dba = (void __iomem *)xhci->cap_regs + offset;
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Doorbell array is located at offset 0x%x from cap regs base addr", offset);
}
/* * Enable USB 3.0 device notifications for function remote wake, which is necessary * for allowing USB 3.0 devices to do remote wakeup from U3 (device suspend).
*/ staticvoid xhci_set_dev_notifications(struct xhci_hcd *xhci)
{
u32 dev_notf;
/* * Initialize memory for HCD and xHC (one-time init). * * Program the PAGESIZE register, initialize the device context array, create * device contexts (?), set up a command ring segment (or two?), create event * ring (one for now).
*/ staticint xhci_init(struct usb_hcd *hcd)
{ struct xhci_hcd *xhci = hcd_to_xhci(hcd); int retval;
/* * Enable interrupts before starting the host (xhci 4.2 and 5.5.2). * Protect the short window before host is running with a lock
*/
spin_lock_irqsave(&xhci->lock, flags);
if (xhci_start(xhci)) {
xhci_halt(xhci);
spin_unlock_irqrestore(&xhci->lock, flags); return -ENODEV;
}
xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
if (xhci->quirks & XHCI_NEC_HOST)
xhci_ring_cmd_db(xhci);
spin_unlock_irqrestore(&xhci->lock, flags);
return 0;
}
/* * Start the HC after it was halted. * * This function is called by the USB core when the HC driver is added. * Its opposite is xhci_stop(). * * xhci_init() must be called once before this function can be called. * Reset the HC, enable device slot contexts, program DCBAAP, and * set command ring pointer and event ring pointer. * * Setup MSI-X vectors and enable interrupts.
*/ int xhci_run(struct usb_hcd *hcd)
{
u64 temp_64; int ret; struct xhci_hcd *xhci = hcd_to_xhci(hcd); struct xhci_interrupter *ir = xhci->interrupters[0]; /* Start the xHCI host controller running only after the USB 2.0 roothub * is setup.
*/
hcd->uses_new_polling = 1; if (hcd->msi_enabled)
ir->ip_autoclear = true;
if (!usb_hcd_is_primary_hcd(hcd)) return xhci_run_finished(xhci);
if (xhci->quirks & XHCI_NEC_HOST) { struct xhci_command *command;
command = xhci_alloc_command(xhci, false, GFP_KERNEL); if (!command) return -ENOMEM;
ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
TRB_TYPE(TRB_NEC_GET_FW)); if (ret)
xhci_free_command(xhci, command);
}
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished %s for main hcd", __func__);
xhci_create_dbc_dev(xhci);
xhci_debugfs_init(xhci);
if (xhci_has_one_roothub(xhci)) return xhci_run_finished(xhci);
set_bit(HCD_FLAG_DEFER_RH_REGISTER, &hcd->flags);
return 0;
}
EXPORT_SYMBOL_GPL(xhci_run);
/* * Stop xHCI driver. * * This function is called by the USB core when the HC driver is removed. * Its opposite is xhci_run(). * * Disable device contexts, disable IRQs, and quiesce the HC. * Reset the HC, finish any completed transactions, and cleanup memory.
*/ void xhci_stop(struct usb_hcd *hcd)
{
u32 temp; struct xhci_hcd *xhci = hcd_to_xhci(hcd); struct xhci_interrupter *ir = xhci->interrupters[0];
mutex_lock(&xhci->mutex);
/* Only halt host and free memory after both hcds are removed */ if (!usb_hcd_is_primary_hcd(hcd)) {
mutex_unlock(&xhci->mutex); return;
}
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
xhci_mem_cleanup(xhci);
xhci_debugfs_exit(xhci);
xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_stop completed - status = %x",
readl(&xhci->op_regs->status));
mutex_unlock(&xhci->mutex);
}
EXPORT_SYMBOL_GPL(xhci_stop);
/* * Shutdown HC (not bus-specific) * * This is called when the machine is rebooting or halting. We assume that the * machine will be powered off, and the HC's internal state will be reset. * Don't bother to free memory. * * This will only ever be called with the main usb_hcd (the USB3 roothub).
*/ void xhci_shutdown(struct usb_hcd *hcd)
{ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
/* Don't poll the roothubs after shutdown. */
xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
__func__, hcd->self.busnum);
clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
timer_delete_sync(&hcd->rh_timer);
if (xhci->shared_hcd) {
clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
timer_delete_sync(&xhci->shared_hcd->rh_timer);
}
spin_lock_irq(&xhci->lock);
xhci_halt(xhci);
/* * Workaround for spurious wakeps at shutdown with HSW, and for boot * firmware delay in ADL-P PCH if port are left in U3 at shutdown
*/ if (xhci->quirks & XHCI_SPURIOUS_WAKEUP ||
xhci->quirks & XHCI_RESET_TO_DEFAULT)
xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
/* save both primary and all secondary interrupters */ /* fixme, shold we lock to prevent race with remove secondary interrupter? */ for (i = 0; i < xhci->max_interrupters; i++) {
ir = xhci->interrupters[i]; if (!ir) continue;
/* FIXME should we lock to protect against freeing of interrupters */ for (i = 0; i < xhci->max_interrupters; i++) {
ir = xhci->interrupters[i]; if (!ir) continue;
/* * The whole command ring must be cleared to zero when we suspend the host. * * The host doesn't save the command ring pointer in the suspend well, so we * need to re-program it on resume. Unfortunately, the pointer must be 64-byte * aligned, because of the reserved bits in the command ring dequeue pointer * register. Therefore, we can't just set the dequeue pointer back in the * middle of the ring (TRBs are 16-byte aligned).
*/ staticvoid xhci_clear_command_ring(struct xhci_hcd *xhci)
{ struct xhci_ring *ring; struct xhci_segment *seg;
ring = xhci->cmd_ring;
xhci_for_each_ring_seg(ring->first_seg, seg) { /* erase all TRBs before the link */
memset(seg->trbs, 0, sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1)); /* clear link cycle bit */
seg->trbs[TRBS_PER_SEGMENT - 1].link.control &= cpu_to_le32(~TRB_CYCLE);
}
xhci_initialize_ring_info(ring); /* * Reset the hardware dequeue pointer. * Yes, this will need to be re-written after resume, but we're paranoid * and want to make sure the hardware doesn't access bogus memory * because, say, the BIOS or an SMI started the host without changing * the command ring pointers.
*/
xhci_set_cmd_ring_deq(xhci);
}
/* * Disable port wake bits if do_wakeup is not set. * * Also clear a possible internal port wake state left hanging for ports that * detected termination but never successfully enumerated (trained to 0U). * Internal wake causes immediate xHCI wake after suspend. PORT_CSC write done * at enumeration clears this wake, force one here as well for unconnected ports
*/
status = readl(&xhci->op_regs->status); if (status & STS_EINT) returntrue; /* * Checking STS_EINT is not enough as there is a lag between a change * bit being set and the Port Status Change Event that it generated * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
*/
/* Clear root port wake on bits if wakeup not allowed. */
xhci_disable_hub_port_wake(xhci, &xhci->usb3_rhub, do_wakeup);
xhci_disable_hub_port_wake(xhci, &xhci->usb2_rhub, do_wakeup);
if (!HCD_HW_ACCESSIBLE(hcd)) return 0;
xhci_dbc_suspend(xhci);
/* Don't poll the roothubs on bus suspend. */
xhci_dbg(xhci, "%s: stopping usb%d port polling.\n",
__func__, hcd->self.busnum);
clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
timer_delete_sync(&hcd->rh_timer); if (xhci->shared_hcd) {
clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
timer_delete_sync(&xhci->shared_hcd->rh_timer);
}
if (xhci->quirks & XHCI_SUSPEND_DELAY)
usleep_range(1000, 1500);
spin_lock_irq(&xhci->lock);
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); if (xhci->shared_hcd)
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags); /* step 1: stop endpoint */ /* skipped assuming that port suspend has done */
/* step 3: save registers */
xhci_save_registers(xhci);
/* step 4: set CSS flag */
command = readl(&xhci->op_regs->command);
command |= CMD_CSS;
writel(command, &xhci->op_regs->command);
xhci->broken_suspend = 0; if (xhci_handshake(&xhci->op_regs->status,
STS_SAVE, 0, 20 * 1000)) { /* * AMD SNPS xHC 3.0 occasionally does not clear the * SSS bit of USBSTS and when driver tries to poll * to see if the xHC clears BIT(8) which never happens * and driver assumes that controller is not responding * and times out. To workaround this, its good to check * if SRE and HCE bits are not set (as per xhci * Section 5.4.2) and bypass the timeout.
*/
res = readl(&xhci->op_regs->status); if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
(((res & STS_SRE) == 0) &&
((res & STS_HCE) == 0))) {
xhci->broken_suspend = 1;
} else {
xhci_warn(xhci, "WARN: xHC save state timeout\n");
spin_unlock_irq(&xhci->lock); return -ETIMEDOUT;
}
}
spin_unlock_irq(&xhci->lock);
/* * Deleting Compliance Mode Recovery Timer because the xHCI Host * is about to be suspended.
*/ if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
(!(xhci_all_ports_seen_u0(xhci)))) {
timer_delete_sync(&xhci->comp_mode_recovery_timer);
xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, "%s: compliance mode recovery timer deleted",
__func__);
}
return rc;
}
EXPORT_SYMBOL_GPL(xhci_suspend);
/* * start xHC (not bus-specific) * * This is called when the machine transition from S3/S4 mode. *
*/ int xhci_resume(struct xhci_hcd *xhci, bool power_lost, bool is_auto_resume)
{
u32 command, temp = 0; struct usb_hcd *hcd = xhci_to_hcd(xhci); int retval = 0; bool comp_timer_running = false; bool pending_portevent = false; bool suspended_usb3_devs = false;
if (!hcd->state) return 0;
/* Wait a bit if either of the roothubs need to settle from the * transition into bus suspend.
*/
if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
msleep(100);
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags); if (xhci->shared_hcd)
set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
spin_lock_irq(&xhci->lock);
if (xhci->quirks & XHCI_RESET_ON_RESUME || xhci->broken_suspend)
power_lost = true;
if (!power_lost) { /* * Some controllers might lose power during suspend, so wait * for controller not ready bit to clear, just as in xHC init.
*/
retval = xhci_handshake(&xhci->op_regs->status,
STS_CNR, 0, 10 * 1000 * 1000); if (retval) {
xhci_warn(xhci, "Controller not ready at resume %d\n",
retval);
spin_unlock_irq(&xhci->lock); return retval;
} /* step 1: restore register */
xhci_restore_registers(xhci); /* step 2: initialize command ring buffer */
xhci_set_cmd_ring_deq(xhci); /* step 3: restore state and start state*/ /* step 3: set CRS flag */
command = readl(&xhci->op_regs->command);
command |= CMD_CRS;
writel(command, &xhci->op_regs->command); /* * Some controllers take up to 55+ ms to complete the controller * restore so setting the timeout to 100ms. Xhci specification * doesn't mention any timeout value.
*/ if (xhci_handshake(&xhci->op_regs->status,
STS_RESTORE, 0, 100 * 1000)) {
xhci_warn(xhci, "WARN: xHC restore state timeout\n");
spin_unlock_irq(&xhci->lock); return -ETIMEDOUT;
}
}
temp = readl(&xhci->op_regs->status);
/* re-initialize the HC on Restore Error, or Host Controller Error */ if ((temp & (STS_SRE | STS_HCE)) &&
!(xhci->xhc_state & XHCI_STATE_REMOVING)) { if (!power_lost)
xhci_warn(xhci, "xHC error in resume, USBSTS 0x%x, Reinit\n", temp);
power_lost = true;
}
if (power_lost) { if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
!(xhci_all_ports_seen_u0(xhci))) {
timer_delete_sync(&xhci->comp_mode_recovery_timer);
xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, "Compliance Mode Recovery Timer deleted!");
}
/* Let the USB core know _both_ roothubs lost power. */
usb_root_hub_lost_power(xhci->main_hcd->self.root_hub); if (xhci->shared_hcd)
usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
xhci_dbg(xhci, "cleaning up memory\n");
xhci_mem_cleanup(xhci);
xhci_debugfs_exit(xhci);
xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
readl(&xhci->op_regs->status));
/* USB core calls the PCI reinit and start functions twice: * first with the primary HCD, and then with the secondary HCD. * If we don't do the same, the host will never be started.
*/
xhci_dbg(xhci, "Initialize the xhci_hcd\n");
retval = xhci_init(hcd); if (retval) return retval;
comp_timer_running = true;
xhci_dbg(xhci, "Start the primary HCD\n");
retval = xhci_run(hcd); if (!retval && xhci->shared_hcd) {
xhci_dbg(xhci, "Start the secondary HCD\n");
retval = xhci_run(xhci->shared_hcd);
} if (retval) return retval; /* * Resume roothubs unconditionally as PORTSC change bits are not * immediately visible after xHC reset
*/
hcd->state = HC_STATE_SUSPENDED;
if (xhci->shared_hcd) {
xhci->shared_hcd->state = HC_STATE_SUSPENDED;
usb_hcd_resume_root_hub(xhci->shared_hcd);
}
usb_hcd_resume_root_hub(hcd);
/* step 5: walk topology and initialize portsc, * portpmsc and portli
*/ /* this is done in bus_resume */
/* step 6: restart each of the previously * Running endpoints by ringing their doorbells
*/
spin_unlock_irq(&xhci->lock);
xhci_dbc_resume(xhci);
if (retval == 0) { /* * Resume roothubs only if there are pending events. * USB 3 devices resend U3 LFPS wake after a 100ms delay if * the first wake signalling failed, give it that chance if * there are suspended USB 3 devices.
*/ if (xhci->usb3_rhub.bus_state.suspended_ports ||
xhci->usb3_rhub.bus_state.bus_suspended)
suspended_usb3_devs = true;
if (pending_portevent) { if (xhci->shared_hcd)
usb_hcd_resume_root_hub(xhci->shared_hcd);
usb_hcd_resume_root_hub(hcd);
}
}
done: /* * If system is subject to the Quirk, Compliance Mode Timer needs to * be re-initialized Always after a system resume. Ports are subject * to suffer the Compliance Mode issue again. It doesn't matter if * ports have entered previously to U0 before system's suspension.
*/ if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
compliance_mode_recovery_timer_init(xhci);
if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
/* Re-enable port polling. */
xhci_dbg(xhci, "%s: starting usb%d port polling.\n",
__func__, hcd->self.busnum); if (xhci->shared_hcd) {
set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
usb_hcd_poll_rh_status(xhci->shared_hcd);
}
set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
usb_hcd_poll_rh_status(hcd);
if (urb->transfer_buffer_length != 0 &&
!(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)) {
for_each_sg(urb->sg, sg, urb->num_sgs, i) {
len = len + sg->length; if (i > trb_size - 2) {
len = len - tail_sg->length; if (len < max_pkt) {
ret = true; break;
}
dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
buf_len = urb->transfer_buffer_length;
if (IS_ENABLED(CONFIG_HAS_DMA) &&
(urb->transfer_flags & URB_DMA_MAP_SINGLE))
dma_unmap_single(hcd->self.sysdev,
urb->transfer_dma,
urb->transfer_buffer_length,
dir);
if (usb_urb_dir_in(urb)) {
len = sg_pcopy_from_buffer(urb->sg, urb->num_sgs,
urb->transfer_buffer,
buf_len,
0); if (len != buf_len) {
xhci_dbg(hcd_to_xhci(hcd), "Copy from tmp buf to urb sg list failed\n");
urb->actual_length = len;
}
}
urb->transfer_flags &= ~URB_DMA_MAP_SINGLE;
kfree(urb->transfer_buffer);
urb->transfer_buffer = NULL;
}
/* * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT), * we'll copy the actual data into the TRB address register. This is limited to * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
*/ staticint xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
gfp_t mem_flags)
{ struct xhci_hcd *xhci;
xhci = hcd_to_xhci(hcd);
if (xhci_urb_suitable_for_idt(urb)) return 0;
if (xhci->quirks & XHCI_SG_TRB_CACHE_SIZE_QUIRK) { if (xhci_urb_temp_buffer_required(hcd, urb)) return xhci_map_temp_buffer(hcd, urb);
} return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
}
/** * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and * HCDs. Find the index for an endpoint given its descriptor. Use the return * value to right shift 1 for the bitmask. * @desc: USB endpoint descriptor to determine index for * * Index = (epnum * 2) + direction - 1, * where direction = 0 for OUT, 1 for IN. * For control endpoints, the IN index is used (OUT index is unused), so * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
*/ unsignedint xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
{ unsignedint index; if (usb_endpoint_xfer_control(desc))
index = (unsignedint) (usb_endpoint_num(desc)*2); else
index = (unsignedint) (usb_endpoint_num(desc)*2) +
(usb_endpoint_dir_in(desc) ? 1 : 0) - 1; return index;
}
EXPORT_SYMBOL_GPL(xhci_get_endpoint_index);
/* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint * address from the XHCI endpoint index.
*/ staticunsignedint xhci_get_endpoint_address(unsignedint ep_index)
{ unsignedint number = DIV_ROUND_UP(ep_index, 2); unsignedint direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN; return direction | number;
}
/* Find the flag for this endpoint (for use in the control context). Use the * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is * bit 1, etc.
*/ staticunsignedint xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
{ return 1 << (xhci_get_endpoint_index(desc) + 1);
}
/* Compute the last valid endpoint context index. Basically, this is the * endpoint index plus one. For slot contexts with more than valid endpoint, * we find the most significant bit set in the added contexts flags. * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
*/ unsignedint xhci_last_valid_endpoint(u32 added_ctxs)
{ return fls(added_ctxs) - 1;
}
/* Returns 1 if the arguments are OK; * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
*/ staticint xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev, constchar *func) { struct xhci_hcd *xhci; struct xhci_virt_device *virt_dev;
if (!hcd || (check_ep && !ep) || !udev) {
pr_debug("xHCI %s called with invalid args\n", func); return -EINVAL;
} if (!udev->parent) {
pr_debug("xHCI %s called for root hub\n", func); return 0;
}
xhci = hcd_to_xhci(hcd); if (check_virt_dev) { if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
func); return -EINVAL;
}
virt_dev = xhci->devs[udev->slot_id]; if (virt_dev->udev != udev) {
xhci_dbg(xhci, "xHCI %s called with udev and " "virt_dev does not match\n", func); return -EINVAL;
}
}
if (xhci->xhc_state & XHCI_STATE_HALTED) return -ENODEV;
/* * Full speed devices may have a max packet size greater than 8 bytes, but the * USB core doesn't know that until it reads the first 8 bytes of the * descriptor. If the usb_device's max packet size changes after that point, * we need to issue an evaluate context command and wait on it.
*/ staticint xhci_check_ep0_maxpacket(struct xhci_hcd *xhci, struct xhci_virt_device *vdev)
{ struct xhci_input_control_ctx *ctrl_ctx; struct xhci_ep_ctx *ep_ctx; struct xhci_command *command; int max_packet_size; int hw_max_packet_size; int ret = 0;
if (hw_max_packet_size == max_packet_size) return 0;
switch (max_packet_size) { case 8: case 16: case 32: case 64: case 9:
xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, "Max Packet Size for ep 0 changed.");
xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, "Max packet size in usb_device = %d",
max_packet_size);
xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, "Max packet size in xHCI HW = %d",
hw_max_packet_size);
xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, "Issuing evaluate context command.");
command = xhci_alloc_command(xhci, true, GFP_KERNEL); if (!command) return -ENOMEM;
command->in_ctx = vdev->in_ctx;
ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx); if (!ctrl_ctx) {
xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
__func__);
ret = -ENOMEM; break;
} /* Set up the modified control endpoint 0 */
xhci_endpoint_copy(xhci, vdev->in_ctx, vdev->out_ctx, 0);
ret = xhci_configure_endpoint(xhci, vdev->udev, command, true, false); /* Clean up the input context for later use by bandwidth functions */
ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG); break; default:
dev_dbg(&vdev->udev->dev, "incorrect max packet size %d for ep0\n",
max_packet_size); return -EINVAL;
}
kfree(command->completion);
kfree(command);
return ret;
}
/* * non-error returns are a promise to giveback() the urb later * we drop ownership so next owner (or urb unlink) can get it
*/ staticint xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
{ struct xhci_hcd *xhci = hcd_to_xhci(hcd); unsignedlong flags; int ret = 0; unsignedint slot_id, ep_index; unsignedint *ep_state; struct urb_priv *urb_priv; int num_tds;
if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
*ep_state);
ret = -EINVAL; goto free_priv;
} if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
ret = -EINVAL; goto free_priv;
}
switch (usb_endpoint_type(&urb->ep->desc)) {
case USB_ENDPOINT_XFER_CONTROL:
ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
slot_id, ep_index); break; case USB_ENDPOINT_XFER_BULK:
ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
slot_id, ep_index); break; case USB_ENDPOINT_XFER_INT:
ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
slot_id, ep_index); break; case USB_ENDPOINT_XFER_ISOC:
ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
slot_id, ep_index);
}
/* * Remove the URB's TD from the endpoint ring. This may cause the HC to stop * USB transfers, potentially stopping in the middle of a TRB buffer. The HC * should pick up where it left off in the TD, unless a Set Transfer Ring * Dequeue Pointer is issued. * * The TRBs that make up the buffers for the canceled URB will be "removed" from * the ring. Since the ring is a contiguous structure, they can't be physically * removed. Instead, there are two options: * * 1) If the HC is in the middle of processing the URB to be canceled, we * simply move the ring's dequeue pointer past those TRBs using the Set * Transfer Ring Dequeue Pointer command. This will be the common case, * when drivers timeout on the last submitted URB and attempt to cancel. * * 2) If the HC is in the middle of a different TD, we turn the TRBs into a * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The * HC will need to invalidate the any TRBs it has cached after the stop * endpoint command, as noted in the xHCI 0.95 errata. * * 3) The TD may have completed by the time the Stop Endpoint Command * completes, so software needs to handle that case too. * * This function should protect against the TD enqueueing code ringing the * doorbell while this code is waiting for a Stop Endpoint command to complete. * It also needs to account for multiple cancellations on happening at the same * time for the same endpoint. * * Note that this function can be called in any context, or so says * usb_hcd_unlink_urb()
*/ staticint xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
{ unsignedlong flags; int ret, i;
u32 temp; struct xhci_hcd *xhci; struct urb_priv *urb_priv; struct xhci_td *td; unsignedint ep_index; struct xhci_ring *ep_ring; struct xhci_virt_ep *ep; struct xhci_command *command; struct xhci_virt_device *vdev;
/* Make sure the URB hasn't completed or been unlinked already */
ret = usb_hcd_check_unlink_urb(hcd, urb, status); if (ret) goto done;
/* give back URB now if we can't queue it for cancel */
vdev = xhci->devs[urb->dev->slot_id];
urb_priv = urb->hcpriv; if (!vdev || !urb_priv) goto err_giveback;
ep_index = xhci_get_endpoint_index(&urb->ep->desc);
ep = &vdev->eps[ep_index];
ep_ring = xhci_urb_to_transfer_ring(xhci, urb); if (!ep || !ep_ring) goto err_giveback;
/* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
temp = readl(&xhci->op_regs->status); if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
xhci_hc_died(xhci); goto done;
}
/* * check ring is not re-allocated since URB was enqueued. If it is, then * make sure none of the ring related pointers in this URB private data * are touched, such as td_list, otherwise we overwrite freed data
*/ if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
xhci_err(xhci, "Canceled URB td not found on endpoint ring"); for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
td = &urb_priv->td[i]; if (!list_empty(&td->cancelled_td_list))
list_del_init(&td->cancelled_td_list);
} goto err_giveback;
}
if (xhci->xhc_state & XHCI_STATE_HALTED) {
xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, "HC halted, freeing TD manually."); for (i = urb_priv->num_tds_done;
i < urb_priv->num_tds;
i++) {
td = &urb_priv->td[i]; if (!list_empty(&td->td_list))
list_del_init(&td->td_list); if (!list_empty(&td->cancelled_td_list))
list_del_init(&td->cancelled_td_list);
} goto err_giveback;
}
i = urb_priv->num_tds_done; if (i < urb_priv->num_tds)
xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb, "Cancel URB %p, dev %s, ep 0x%x, " "starting at offset 0x%llx",
urb, urb->dev->devpath,
urb->ep->desc.bEndpointAddress,
(unsignedlonglong) xhci_trb_virt_to_dma(
urb_priv->td[i].start_seg,
urb_priv->td[i].start_trb));
for (; i < urb_priv->num_tds; i++) {
td = &urb_priv->td[i]; /* TD can already be on cancelled list if ep halted on it */ if (list_empty(&td->cancelled_td_list)) {
td->cancel_status = TD_DIRTY;
list_add_tail(&td->cancelled_td_list,
&ep->cancelled_td_list);
}
}
/* These completion handlers will sort out cancelled TDs for us */ if (ep->ep_state & (EP_STOP_CMD_PENDING | EP_HALTED | SET_DEQ_PENDING)) {
xhci_dbg(xhci, "Not queuing Stop Endpoint on slot %d ep %d in state 0x%x\n",
urb->dev->slot_id, ep_index, ep->ep_state); goto done;
}
/* In this case no commands are pending but the endpoint is stopped */ if (ep->ep_state & EP_CLEARING_TT) { /* and cancelled TDs can be given back right away */
xhci_dbg(xhci, "Invalidating TDs instantly on slot %d ep %d in state 0x%x\n",
urb->dev->slot_id, ep_index, ep->ep_state);
xhci_process_cancelled_tds(ep);
} else { /* Otherwise, queue a new Stop Endpoint command */
command = xhci_alloc_command(xhci, false, GFP_ATOMIC); if (!command) {
ret = -ENOMEM; goto done;
}
ep->stop_time = jiffies;
ep->ep_state |= EP_STOP_CMD_PENDING;
xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
ep_index, 0);
xhci_ring_cmd_db(xhci);
}
done:
spin_unlock_irqrestore(&xhci->lock, flags); return ret;
/* Drop an endpoint from a new bandwidth configuration for this device. * Only one call to this function is allowed per endpoint before * check_bandwidth() or reset_bandwidth() must be called. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will * add the endpoint to the schedule with possibly new parameters denoted by a * different endpoint descriptor in usb_host_endpoint. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is * not allowed. * * The USB core will not allow URBs to be queued to an endpoint that is being * disabled, so there's no need for mutual exclusion to protect * the xhci->devs[slot_id] structure.
*/ int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep)
{ struct xhci_hcd *xhci; struct xhci_container_ctx *in_ctx, *out_ctx; struct xhci_input_control_ctx *ctrl_ctx; unsignedint ep_index; struct xhci_ep_ctx *ep_ctx;
u32 drop_flag;
u32 new_add_flags, new_drop_flags; int ret;
ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); if (ret <= 0) return ret;
xhci = hcd_to_xhci(hcd); if (xhci->xhc_state & XHCI_STATE_DYING) return -ENODEV;
xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
drop_flag = xhci_get_endpoint_flag(&ep->desc); if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
__func__, drop_flag); return 0;
}
in_ctx = xhci->devs[udev->slot_id]->in_ctx;
out_ctx = xhci->devs[udev->slot_id]->out_ctx;
ctrl_ctx = xhci_get_input_control_ctx(in_ctx); if (!ctrl_ctx) {
xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
__func__); return 0;
}
ep_index = xhci_get_endpoint_index(&ep->desc);
ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index); /* If the HC already knows the endpoint is disabled, * or the HCD has noted it is disabled, ignore this request
*/ if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
le32_to_cpu(ctrl_ctx->drop_flags) &
xhci_get_endpoint_flag(&ep->desc)) { /* Do not warn when called after a usb_device_reset */ if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
__func__, ep); return 0;
}
xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
(unsignedint) ep->desc.bEndpointAddress,
udev->slot_id,
(unsignedint) new_drop_flags,
(unsignedint) new_add_flags); return 0;
}
EXPORT_SYMBOL_GPL(xhci_drop_endpoint);
/* Add an endpoint to a new possible bandwidth configuration for this device. * Only one call to this function is allowed per endpoint before * check_bandwidth() or reset_bandwidth() must be called. * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will * add the endpoint to the schedule with possibly new parameters denoted by a * different endpoint descriptor in usb_host_endpoint. * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is * not allowed. * * The USB core will not allow URBs to be queued to an endpoint until the * configuration or alt setting is installed in the device, so there's no need * for mutual exclusion to protect the xhci->devs[slot_id] structure.
*/ int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep)
{ struct xhci_hcd *xhci; struct xhci_container_ctx *in_ctx; unsignedint ep_index; struct xhci_input_control_ctx *ctrl_ctx; struct xhci_ep_ctx *ep_ctx;
u32 added_ctxs;
u32 new_add_flags, new_drop_flags; struct xhci_virt_device *virt_dev; int ret = 0;
ret = xhci_check_args(hcd, udev, ep, 1, true, __func__); if (ret <= 0) { /* So we won't queue a reset ep command for a root hub */
ep->hcpriv = NULL; return ret;
}
xhci = hcd_to_xhci(hcd); if (xhci->xhc_state & XHCI_STATE_DYING) return -ENODEV;
added_ctxs = xhci_get_endpoint_flag(&ep->desc); if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) { /* FIXME when we have to issue an evaluate endpoint command to * deal with ep0 max packet size changing once we get the * descriptors
*/
xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
__func__, added_ctxs); return 0;
}
virt_dev = xhci->devs[udev->slot_id];
in_ctx = virt_dev->in_ctx;
ctrl_ctx = xhci_get_input_control_ctx(in_ctx); if (!ctrl_ctx) {
xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
__func__); return 0;
}
ep_index = xhci_get_endpoint_index(&ep->desc); /* If this endpoint is already in use, and the upper layers are trying * to add it again without dropping it, reject the addition.
*/ if (virt_dev->eps[ep_index].ring &&
!(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
xhci_warn(xhci, "Trying to add endpoint 0x%x " "without dropping it.\n",
(unsignedint) ep->desc.bEndpointAddress); return -EINVAL;
}
/* If the HCD has already noted the endpoint is enabled, * ignore this request.
*/ if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
__func__, ep); return 0;
}
/* * Configuration and alternate setting changes must be done in * process context, not interrupt context (or so documenation * for usb_set_interface() and usb_set_configuration() claim).
*/ if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
__func__, ep->desc.bEndpointAddress); return -ENOMEM;
}
/* If xhci_endpoint_disable() was called for this endpoint, but the * xHC hasn't been notified yet through the check_bandwidth() call, * this re-adds a new state for the endpoint from the new endpoint * descriptors. We must drop and re-add this endpoint, so we leave the * drop flags alone.
*/
new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
/* Store the usb_device pointer for later use */
ep->hcpriv = udev;
ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx); if (!ctrl_ctx) {
xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
__func__); return;
}
/* When a device's add flag and drop flag are zero, any subsequent * configure endpoint command will leave that endpoint's state * untouched. Make sure we don't leave any old state in the input * endpoint contexts.
*/
ctrl_ctx->drop_flags = 0;
ctrl_ctx->add_flags = 0;
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK); /* Endpoint 0 is always valid */
slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1)); for (i = 1; i < 31; i++) {
ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
ep_ctx->ep_info = 0;
ep_ctx->ep_info2 = 0;
ep_ctx->deq = 0;
ep_ctx->tx_info = 0;
}
}
switch (*cmd_status) { case COMP_COMMAND_ABORTED: case COMP_COMMAND_RING_STOPPED:
xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
ret = -ETIME; break; case COMP_RESOURCE_ERROR:
dev_warn(&udev->dev, "Not enough host controller resources for new device state.\n");
ret = -ENOMEM; /* FIXME: can we allocate more resources for the HC? */ break; case COMP_BANDWIDTH_ERROR: case COMP_SECONDARY_BANDWIDTH_ERROR:
dev_warn(&udev->dev, "Not enough bandwidth for new device state.\n");
ret = -ENOSPC; /* FIXME: can we go back to the old state? */ break; case COMP_TRB_ERROR: /* the HCD set up something wrong */
dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, " "add flag = 1, " "and endpoint is not disabled.\n");
ret = -EINVAL; break; case COMP_INCOMPATIBLE_DEVICE_ERROR:
dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint configure command.\n");
ret = -ENODEV; break; case COMP_SUCCESS:
xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, "Successful Endpoint Configure command");
ret = 0; break; default:
xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
*cmd_status);
ret = -EINVAL; break;
} return ret;
}
switch (*cmd_status) { case COMP_COMMAND_ABORTED: case COMP_COMMAND_RING_STOPPED:
xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
ret = -ETIME; break; case COMP_PARAMETER_ERROR:
dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate context command.\n");
ret = -EINVAL; break; case COMP_SLOT_NOT_ENABLED_ERROR:
dev_warn(&udev->dev, "WARN: slot not enabled for evaluate context command.\n");
ret = -EINVAL; break; case COMP_CONTEXT_STATE_ERROR:
dev_warn(&udev->dev, "WARN: invalid context state for evaluate context command.\n");
ret = -EINVAL; break; case COMP_INCOMPATIBLE_DEVICE_ERROR:
dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate context command.\n");
ret = -ENODEV; break; case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR: /* Max Exit Latency too large error */
dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
ret = -EINVAL; break; case COMP_SUCCESS:
xhci_dbg_trace(xhci, trace_xhci_dbg_context_change, "Successful evaluate context command");
ret = 0; break; default:
xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
*cmd_status);
ret = -EINVAL; break;
} return ret;
}
/* Ignore the slot flag (bit 0), and the default control endpoint flag * (bit 1). The default control endpoint is added during the Address * Device command and is never removed until the slot is disabled.
*/
--> --------------------
--> maximum size reached
--> --------------------
Messung V0.5
¤ Dauer der Verarbeitung: 0.22 Sekunden
(vorverarbeitet)
¤
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