/* SDIO status in R5 Type e : error bit s : status bit r : detected and set for the actual command response x : detected and set during command execution. the host must poll the card by sending status command in order to read these bits. Clear condition a : according to the card state b : always related to the previous command. Reception of a valid command will clear it (with a delay of one command) c : clear by read
*/
#define R5_COM_CRC_ERROR (1 << 15) /* er, b */ #define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */ #define R5_ERROR (1 << 11) /* erx, c */ #define R5_FUNCTION_NUMBER (1 << 9) /* er, c */ #define R5_OUT_OF_RANGE (1 << 8) /* er, c */ #define R5_STATUS(x) (x & 0xCB00) #define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b */
/* * Card Common Control Registers (CCCR)
*/
#define SDIO_CCCR_CCCR 0x00
#define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */ #define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */ #define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */ #define SDIO_CCCR_REV_3_00 3 /* CCCR/FBR Version 3.00 */
#define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */ #define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */ #define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */ #define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */ #define SDIO_SDIO_REV_3_00 4 /* SDIO Spec Version 3.00 */
#define SDIO_CCCR_SD 0x01
#define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */ #define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */ #define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */ #define SDIO_SD_REV_3_00 3 /* SD Physical Spec Version 3.00 */
#define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */ #define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */ #define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */ #define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */ #define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */ #define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */ #define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */ #define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
#define SDIO_CCCR_CIS 0x09 /* common CIS pointer (3 bytes) */
/* Following 4 regs are valid only if SBS is set */ #define SDIO_CCCR_SUSPEND 0x0c #define SDIO_CCCR_SELx 0x0d #define SDIO_CCCR_EXECx 0x0e #define SDIO_CCCR_READYx 0x0f
#define SDIO_CCCR_BLKSIZE 0x10
#define SDIO_CCCR_POWER 0x12
#define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */ #define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
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