/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note * * Copyright 2016-2023 HabanaLabs, Ltd. * All Rights Reserved. *
*/
#ifndef HABANALABS_H_ #define HABANALABS_H_
#include <drm/drm.h>
/* * Defines that are asic-specific but constitutes as ABI between kernel driver * and userspace
*/ #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */
/* * 128 SOBs reserved for collective wait * 16 SOBs reserved for sync stream
*/ #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144
/* * 64 monitors reserved for collective wait * 8 monitors reserved for sync stream
*/ #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72
/* Max number of elements in timestamps registration buffers */ #define TS_MAX_ELEMENTS_NUM (1 << 20) /* 1MB */
/* * Goya queue Numbering * * The external queues (PCI DMA channels) MUST be before the internal queues * and each group (PCI DMA channels and internal) must be contiguous inside * itself but there can be a gap between the two groups (although not * recommended)
*/
/* * Gaudi queue Numbering * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*. * Except one CPU queue, all the rest are internal queues.
*/
/* * In GAUDI2 we have two modes of operation in regard to queues: * 1. Legacy mode, where each QMAN exposes 4 streams to the user * 2. F/W mode, where we use F/W to schedule the JOBS to the different queues. * * When in legacy mode, the user sends the queue id per JOB according to * enum gaudi2_queue_id below. * * When in F/W mode, the user sends a stream id per Command Submission. The * stream id is a running number from 0 up to (N-1), where N is the number * of streams the F/W exposes and is passed to the user in * struct hl_info_hw_ip_info
*/
/* * ASIC specific PLL index * * Used to retrieve in frequency info of different IPs via HL_INFO_PLL_FREQUENCY under * DRM_IOCTL_HL_INFO IOCTL. * The enums need to be used as an index in struct hl_pll_frequency_info.
*/
/** * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is * submitted to the GOYA's DMA QMAN. This attribute is not relevant * to the H/W but the kernel driver use it to parse the packet's * addresses and patch/validate them. * @HL_DMA_HOST_TO_DRAM: DMA operation from Host memory to GOYA's DDR. * @HL_DMA_HOST_TO_SRAM: DMA operation from Host memory to GOYA's SRAM. * @HL_DMA_DRAM_TO_SRAM: DMA operation from GOYA's DDR to GOYA's SRAM. * @HL_DMA_SRAM_TO_DRAM: DMA operation from GOYA's SRAM to GOYA's DDR. * @HL_DMA_SRAM_TO_HOST: DMA operation from GOYA's SRAM to Host memory. * @HL_DMA_DRAM_TO_HOST: DMA operation from GOYA's DDR to Host memory. * @HL_DMA_DRAM_TO_DRAM: DMA operation from GOYA's DDR to GOYA's DDR. * @HL_DMA_SRAM_TO_SRAM: DMA operation from GOYA's SRAM to GOYA's SRAM. * @HL_DMA_ENUM_MAX: number of values in enum
*/ enum hl_goya_dma_direction {
HL_DMA_HOST_TO_DRAM,
HL_DMA_HOST_TO_SRAM,
HL_DMA_DRAM_TO_SRAM,
HL_DMA_SRAM_TO_DRAM,
HL_DMA_SRAM_TO_HOST,
HL_DMA_DRAM_TO_HOST,
HL_DMA_DRAM_TO_DRAM,
HL_DMA_SRAM_TO_SRAM,
HL_DMA_ENUM_MAX
};
/** * enum hl_device_status - Device status information. * @HL_DEVICE_STATUS_OPERATIONAL: Device is operational. * @HL_DEVICE_STATUS_IN_RESET: Device is currently during reset. * @HL_DEVICE_STATUS_MALFUNCTION: Device is unusable. * @HL_DEVICE_STATUS_NEEDS_RESET: Device needs reset because auto reset was disabled. * @HL_DEVICE_STATUS_IN_DEVICE_CREATION: Device is operational but its creation is still in * progress. * @HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE: Device is currently during reset that was * triggered because the user released the device * @HL_DEVICE_STATUS_LAST: Last status.
*/ enum hl_device_status {
HL_DEVICE_STATUS_OPERATIONAL,
HL_DEVICE_STATUS_IN_RESET,
HL_DEVICE_STATUS_MALFUNCTION,
HL_DEVICE_STATUS_NEEDS_RESET,
HL_DEVICE_STATUS_IN_DEVICE_CREATION,
HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE,
HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE
};
/* Opcode for management ioctl * * HW_IP_INFO - Receive information about different IP blocks in the * device. * HL_INFO_HW_EVENTS - Receive an array describing how many times each event * occurred since the last hard reset. * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the * specific context. This is relevant only for devices * where the dram is managed by the kernel driver * HL_INFO_HW_IDLE - Retrieve information about the idle status of each * internal engine. * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't * require an open context. * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device * over the last period specified by the user. * The period can be between 100ms to 1s, in * resolution of 100ms. The return value is a * percentage of the utilization rate. * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each * event occurred since the driver was loaded. * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate * of the device in MHz. The maximum clock rate is * configurable via sysfs parameter * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset * operations performed on the device since the last * time the driver was loaded. * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time * for synchronization. * HL_INFO_CS_COUNTERS - Retrieve command submission counters * HL_INFO_PCI_COUNTERS - Retrieve PCI counters * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency * HL_INFO_POWER - Retrieve power information * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls * HL_INFO_DRAM_REPLACED_ROWS - Retrieve DRAM replaced rows info * HL_INFO_DRAM_PENDING_ROWS - Retrieve DRAM pending rows num * HL_INFO_LAST_ERR_OPEN_DEV_TIME - Retrieve timestamp of the last time the device was opened * and CS timeout or razwi error occurred. * HL_INFO_CS_TIMEOUT_EVENT - Retrieve CS timeout timestamp and its related CS sequence number. * HL_INFO_RAZWI_EVENT - Retrieve parameters of razwi: * Timestamp of razwi. * The address which accessing it caused the razwi. * Razwi initiator. * Razwi cause, was it a page fault or MMU access error. * May return 0 even though no new data is available, in that case * timestamp will be 0. * HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES - Retrieve valid page sizes for device memory allocation * HL_INFO_SECURED_ATTESTATION - Retrieve attestation report of the boot. * HL_INFO_REGISTER_EVENTFD - Register eventfd for event notifications. * HL_INFO_UNREGISTER_EVENTFD - Unregister eventfd * HL_INFO_GET_EVENTS - Retrieve the last occurred events * HL_INFO_UNDEFINED_OPCODE_EVENT - Retrieve last undefined opcode error information. * May return 0 even though no new data is available, in that case * timestamp will be 0. * HL_INFO_ENGINE_STATUS - Retrieve the status of all the h/w engines in the asic. * HL_INFO_PAGE_FAULT_EVENT - Retrieve parameters of captured page fault. * May return 0 even though no new data is available, in that case * timestamp will be 0. * HL_INFO_USER_MAPPINGS - Retrieve user mappings, captured after page fault event. * HL_INFO_FW_GENERIC_REQ - Send generic request to FW. * HL_INFO_HW_ERR_EVENT - Retrieve information on the reported HW error. * May return 0 even though no new data is available, in that case * timestamp will be 0. * HL_INFO_FW_ERR_EVENT - Retrieve information on the reported FW error. * May return 0 even though no new data is available, in that case * timestamp will be 0. * HL_INFO_USER_ENGINE_ERR_EVENT - Retrieve the last engine id that reported an error.
*/ #define HL_INFO_HW_IP_INFO 0 #define HL_INFO_HW_EVENTS 1 #define HL_INFO_DRAM_USAGE 2 #define HL_INFO_HW_IDLE 3 #define HL_INFO_DEVICE_STATUS 4 #define HL_INFO_DEVICE_UTILIZATION 6 #define HL_INFO_HW_EVENTS_AGGREGATE 7 #define HL_INFO_CLK_RATE 8 #define HL_INFO_RESET_COUNT 9 #define HL_INFO_TIME_SYNC 10 #define HL_INFO_CS_COUNTERS 11 #define HL_INFO_PCI_COUNTERS 12 #define HL_INFO_CLK_THROTTLE_REASON 13 #define HL_INFO_SYNC_MANAGER 14 #define HL_INFO_TOTAL_ENERGY 15 #define HL_INFO_PLL_FREQUENCY 16 #define HL_INFO_POWER 17 #define HL_INFO_OPEN_STATS 18 #define HL_INFO_DRAM_REPLACED_ROWS 21 #define HL_INFO_DRAM_PENDING_ROWS 22 #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23 #define HL_INFO_CS_TIMEOUT_EVENT 24 #define HL_INFO_RAZWI_EVENT 25 #define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26 #define HL_INFO_SECURED_ATTESTATION 27 #define HL_INFO_REGISTER_EVENTFD 28 #define HL_INFO_UNREGISTER_EVENTFD 29 #define HL_INFO_GET_EVENTS 30 #define HL_INFO_UNDEFINED_OPCODE_EVENT 31 #define HL_INFO_ENGINE_STATUS 32 #define HL_INFO_PAGE_FAULT_EVENT 33 #define HL_INFO_USER_MAPPINGS 34 #define HL_INFO_FW_GENERIC_REQ 35 #define HL_INFO_HW_ERR_EVENT 36 #define HL_INFO_FW_ERR_EVENT 37 #define HL_INFO_USER_ENGINE_ERR_EVENT 38 #define HL_INFO_DEV_SIGNED 40
/* Maximum buffer size for retrieving engines status */ #define HL_ENGINES_DATA_MAX_SIZE SZ_1M
/** * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC * @sram_base_address: The first SRAM physical base address that is free to be * used by the user. * @dram_base_address: The first DRAM virtual or physical base address that is * free to be used by the user. * @dram_size: The DRAM size that is available to the user. * @sram_size: The SRAM size that is available to the user. * @num_of_events: The number of events that can be received from the f/w. This * is needed so the user can what is the size of the h/w events * array he needs to pass to the kernel when he wants to fetch * the event counters. * @device_id: PCI device ID of the ASIC. * @module_id: Module ID of the ASIC for mezzanine cards in servers * (From OCP spec). * @decoder_enabled_mask: Bit-mask that represents which decoders are enabled. * @first_available_interrupt_id: The first available interrupt ID for the user * to be used when it works with user interrupts. * Relevant for Gaudi2 and later. * @server_type: Server type that the Gaudi ASIC is currently installed in. * The value is according to enum hl_server_type * @cpld_version: CPLD version on the board. * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs. * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs. * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs. * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler * in some ASICs. * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant * for Goya/Gaudi only. * @dram_enabled: Whether the DRAM is enabled. * @security_enabled: Whether security is enabled on device. * @mme_master_slave_mode: Indicate whether the MME is working in master/slave * configuration. Relevant for Gaudi2 and later. * @cpucp_version: The CPUCP f/w version. * @card_name: The card name as passed by the f/w. * @tpc_enabled_mask_ext: Bit-mask that represents which TPCs are enabled. * Relevant for Gaudi2 and later. * @dram_page_size: The DRAM physical page size. * @edma_enabled_mask: Bit-mask that represents which EDMAs are enabled. * Relevant for Gaudi2 and later. * @number_of_user_interrupts: The number of interrupts that are available to the userspace * application to use. Relevant for Gaudi2 and later. * @device_mem_alloc_default_page_size: default page size used in device memory allocation. * @revision_id: PCI revision ID of the ASIC. * @tpc_interrupt_id: interrupt id for TPC to use in order to raise events towards the host. * @rotator_enabled_mask: Bit-mask that represents which rotators are enabled. * Relevant for Gaudi3 and later. * @engine_core_interrupt_reg_addr: interrupt register address for engine core to use * in order to raise events toward FW. * @reserved_dram_size: DRAM size reserved for driver and firmware.
*/ struct hl_info_hw_ip_info {
__u64 sram_base_address;
__u64 dram_base_address;
__u64 dram_size;
__u32 sram_size;
__u32 num_of_events;
__u32 device_id;
__u32 module_id;
__u32 decoder_enabled_mask;
__u16 first_available_interrupt_id;
__u16 server_type;
__u32 cpld_version;
__u32 psoc_pci_pll_nr;
__u32 psoc_pci_pll_nf;
__u32 psoc_pci_pll_od;
__u32 psoc_pci_pll_div_factor;
__u8 tpc_enabled_mask;
__u8 dram_enabled;
__u8 security_enabled;
__u8 mme_master_slave_mode;
__u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
__u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
__u64 tpc_enabled_mask_ext;
__u64 dram_page_size;
__u32 edma_enabled_mask;
__u16 number_of_user_interrupts;
__u8 reserved1;
__u8 reserved2;
__u64 reserved3;
__u64 device_mem_alloc_default_page_size;
__u64 reserved4;
__u64 reserved5;
__u32 reserved6;
__u8 reserved7;
__u8 revision_id;
__u16 tpc_interrupt_id;
__u32 rotator_enabled_mask;
__u32 reserved9;
__u64 engine_core_interrupt_reg_addr;
__u64 reserved_dram_size;
};
struct hl_info_hw_idle {
__u32 is_idle; /* * Bitmask of busy engines. * Bits definition is according to `enum <chip>_engine_id'.
*/
__u32 busy_engines_mask;
/* * Extended Bitmask of busy engines. * Bits definition is according to `enum <chip>_engine_id'.
*/
__u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE];
};
/** * struct hl_info_clk_throttle - clock throttling reason * @clk_throttling_reason: each bit represents a clk throttling reason * @clk_throttling_timestamp_us: represents CPU timestamp in microseconds of the start-event * @clk_throttling_duration_ns: the clock throttle time in nanosec
*/ struct hl_info_clk_throttle {
__u32 clk_throttling_reason;
__u32 pad;
__u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX];
__u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX];
};
/** * struct hl_info_energy - device energy information * @total_energy_consumption: total device energy consumption
*/ struct hl_info_energy {
__u64 total_energy_consumption;
};
/** * struct hl_open_stats_info - device open statistics information * @open_counter: ever growing counter, increased on each successful dev open * @last_open_period_ms: duration (ms) device was open last time * @is_compute_ctx_active: Whether there is an active compute context executing * @compute_ctx_in_release: true if the current compute context is being released
*/ struct hl_open_stats_info {
__u64 open_counter;
__u64 last_open_period_ms;
__u8 is_compute_ctx_active;
__u8 compute_ctx_in_release;
__u8 pad[6];
};
/** * struct hl_power_info - power information * @power: power consumption
*/ struct hl_power_info {
__u64 power;
};
/** * struct hl_info_sync_manager - sync manager information * @first_available_sync_object: first available sob * @first_available_monitor: first available monitor * @first_available_cq: first available cq
*/ struct hl_info_sync_manager {
__u32 first_available_sync_object;
__u32 first_available_monitor;
__u32 first_available_cq;
__u32 reserved;
};
/** * struct hl_info_cs_counters - command submission counters * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue * @total_parsing_drop_cnt: total dropped due to error in packet parsing * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing * @total_queue_full_drop_cnt: total dropped due to queue full * @ctx_queue_full_drop_cnt: context dropped due to queue full * @total_device_in_reset_drop_cnt: total dropped due to device in reset * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight * @total_validation_drop_cnt: total dropped due to validation error * @ctx_validation_drop_cnt: context dropped due to validation error
*/ struct hl_info_cs_counters {
__u64 total_out_of_mem_drop_cnt;
__u64 ctx_out_of_mem_drop_cnt;
__u64 total_parsing_drop_cnt;
__u64 ctx_parsing_drop_cnt;
__u64 total_queue_full_drop_cnt;
__u64 ctx_queue_full_drop_cnt;
__u64 total_device_in_reset_drop_cnt;
__u64 ctx_device_in_reset_drop_cnt;
__u64 total_max_cs_in_flight_drop_cnt;
__u64 ctx_max_cs_in_flight_drop_cnt;
__u64 total_validation_drop_cnt;
__u64 ctx_validation_drop_cnt;
};
/** * struct hl_info_last_err_open_dev_time - last error boot information. * @timestamp: timestamp of last time the device was opened and error occurred.
*/ struct hl_info_last_err_open_dev_time {
__s64 timestamp;
};
/** * struct hl_info_cs_timeout_event - last CS timeout information. * @timestamp: timestamp when last CS timeout event occurred. * @seq: sequence number of last CS timeout event.
*/ struct hl_info_cs_timeout_event {
__s64 timestamp;
__u64 seq;
};
/** * struct hl_info_razwi_event - razwi information. * @timestamp: timestamp of razwi. * @addr: address which accessing it caused razwi. * @engine_id: engine id of the razwi initiator, if it was initiated by engine that does not * have engine id it will be set to HL_RAZWI_NA_ENG_ID. If there are several possible * engines which caused the razwi, it will hold all of them. * @num_of_possible_engines: contains number of possible engine ids. In some asics, razwi indication * might be common for several engines and there is no way to get the * exact engine. In this way, engine_id array will be filled with all * possible engines caused this razwi. Also, there might be possibility * in gaudi, where we don't indication on specific engine, in that case * the value of this parameter will be zero. * @flags: bitmask for additional data: HL_RAZWI_READ - razwi caused by read operation * HL_RAZWI_WRITE - razwi caused by write operation * HL_RAZWI_LBW - razwi caused by lbw fabric transaction * HL_RAZWI_HBW - razwi caused by hbw fabric transaction * HL_RAZWI_RR - razwi caused by range register * HL_RAZWI_ADDR_DEC - razwi caused by address decode error * Note: this data is not supported by all asics, in that case the relevant bits will not * be set.
*/ struct hl_info_razwi_event {
__s64 timestamp;
__u64 addr;
__u16 engine_id[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR];
__u16 num_of_possible_engines;
__u8 flags;
__u8 pad[5];
};
#define MAX_QMAN_STREAMS_INFO 4 #define OPCODE_INFO_MAX_ADDR_SIZE 8 /** * struct hl_info_undefined_opcode_event - info about last undefined opcode error * @timestamp: timestamp of the undefined opcode error * @cb_addr_streams: CB addresses (per stream) that are currently exists in the PQ * entries. In case all streams array entries are * filled with values, it means the execution was in Lower-CP. * @cq_addr: the address of the current handled command buffer * @cq_size: the size of the current handled command buffer * @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array. * should be equal to 1 in case of undefined opcode * in Upper-CP (specific stream) and equal to 4 incase * of undefined opcode in Lower-CP. * @engine_id: engine-id that the error occurred on * @stream_id: the stream id the error occurred on. In case the stream equals to * MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower-CP.
*/ struct hl_info_undefined_opcode_event {
__s64 timestamp;
__u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE];
__u64 cq_addr;
__u32 cq_size;
__u32 cb_addr_streams_len;
__u32 engine_id;
__u32 stream_id;
};
/** * struct hl_info_hw_err_event - info about HW error * @timestamp: timestamp of error occurrence * @event_id: The async event ID (specific to each device type). * @pad: size padding for u64 granularity.
*/ struct hl_info_hw_err_event {
__s64 timestamp;
__u16 event_id;
__u16 pad[3];
};
/* FW error definition for event_type in struct hl_info_fw_err_event */ enum hl_info_fw_err_type {
HL_INFO_FW_HEARTBEAT_ERR,
HL_INFO_FW_REPORTED_ERR,
};
/** * struct hl_info_fw_err_event - info about FW error * @timestamp: time-stamp of error occurrence * @err_type: The type of event as defined in hl_info_fw_err_type. * @event_id: The async event ID (specific to each device type, applicable only when event type is * HL_INFO_FW_REPORTED_ERR). * @pad: size padding for u64 granularity.
*/ struct hl_info_fw_err_event {
__s64 timestamp;
__u16 err_type;
__u16 event_id;
__u32 pad;
};
/** * struct hl_info_engine_err_event - engine error info * @timestamp: time-stamp of error occurrence * @engine_id: engine id who reported the error. * @error_count: Amount of errors reported. * @pad: size padding for u64 granularity.
*/ struct hl_info_engine_err_event {
__s64 timestamp;
__u16 engine_id;
__u16 error_count;
__u32 pad;
};
/** * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information. * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size * (e.g. 0x2100000 means that 1MB and 32MB pages are supported).
*/ struct hl_info_dev_memalloc_page_sizes {
__u64 page_order_bitmask;
};
#define SEC_PCR_DATA_BUF_SZ 256 #define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ #define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */ #define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ #define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */ #define SEC_DEV_INFO_BUF_SZ 5120
/* * struct hl_info_sec_attest - attestation report of the boot * @nonce: number only used once. random number provided by host. this also passed to the quote * command as a qualifying data. * @pcr_quote_len: length of the attestation quote data (bytes) * @pub_data_len: length of the public data (bytes) * @certificate_len: length of the certificate (bytes) * @pcr_num_reg: number of PCR registers in the pcr_data array * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes) * @quote_sig_len: length of the attestation report signature (bytes) * @pcr_data: raw values of the PCR registers * @pcr_quote: attestation report data structure * @quote_sig: signature structure of the attestation report * @public_data: public key for the signed attestation * (outPublic + name + qualifiedName) * @certificate: certificate for the attestation signing key
*/ struct hl_info_sec_attest {
__u32 nonce;
__u16 pcr_quote_len;
__u16 pub_data_len;
__u16 certificate_len;
__u8 pcr_num_reg;
__u8 pcr_reg_len;
__u8 quote_sig_len;
__u8 pcr_data[SEC_PCR_DATA_BUF_SZ];
__u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ];
__u8 quote_sig[SEC_SIGNATURE_BUF_SZ];
__u8 public_data[SEC_PUB_DATA_BUF_SZ];
__u8 certificate[SEC_CERTIFICATE_BUF_SZ];
__u8 pad0[2];
};
/* * struct hl_info_signed - device information signed by a secured device. * @nonce: number only used once. random number provided by host. this also passed to the quote * command as a qualifying data. * @pub_data_len: length of the public data (bytes) * @certificate_len: length of the certificate (bytes) * @info_sig_len: length of the attestation signature (bytes) * @public_data: public key info signed info data (outPublic + name + qualifiedName) * @certificate: certificate for the signing key * @info_sig: signature of the info + nonce data. * @dev_info_len: length of device info (bytes) * @dev_info: device info as byte array.
*/ struct hl_info_signed {
__u32 nonce;
__u16 pub_data_len;
__u16 certificate_len;
__u8 info_sig_len;
__u8 public_data[SEC_PUB_DATA_BUF_SZ];
__u8 certificate[SEC_CERTIFICATE_BUF_SZ];
__u8 info_sig[SEC_SIGNATURE_BUF_SZ];
__u16 dev_info_len;
__u8 dev_info[SEC_DEV_INFO_BUF_SZ];
__u8 pad[2];
};
/** * struct hl_page_fault_info - page fault information. * @timestamp: timestamp of page fault. * @addr: address which accessing it caused page fault. * @engine_id: engine id which caused the page fault, supported only in gaudi3.
*/ struct hl_page_fault_info {
__s64 timestamp;
__u64 addr;
__u16 engine_id;
__u8 pad[6];
};
/** * struct hl_info_args - Main structure to retrieve device related information. * @return_pointer: User space address of the relevant structure related to HL_INFO_* operation * mentioned in @op. * @return_size: Size of the structure used in @return_pointer, just like "size" in "snprintf", it * limits how many bytes the kernel can write. For hw_events array, the size should be * hl_info_hw_ip_info.num_of_events * sizeof(__u32). * @op: Defines which type of information to be retrieved. Refer HL_INFO_* for details. * @dcore_id: DCORE id for which the information is relevant (for Gaudi refer to enum gaudi_dcores). * @ctx_id: Context ID of the user. Currently not in use. * @period_ms: Period value, in milliseconds, for utilization rate in range 100ms - 1000ms in 100 ms * resolution. Currently not in use. * @pll_index: Index as defined in hl_<asic type>_pll_index enumeration. * @eventfd: event file descriptor for event notifications. * @user_buffer_actual_size: Actual data size which was copied to user allocated buffer by the * driver. It is possible for the user to allocate buffer larger than * needed, hence updating this variable so user will know the exact amount * of bytes copied by the kernel to the buffer. * @sec_attest_nonce: Nonce number used for attestation report. * @array_size: Number of array members copied to user buffer. * Relevant for HL_INFO_USER_MAPPINGS info ioctl. * @fw_sub_opcode: generic requests sub opcodes. * @pad: Padding to 64 bit.
*/ struct hl_info_args {
__u64 return_pointer;
__u32 return_size;
__u32 op;
/* Opcode to create a new command buffer */ #define HL_CB_OP_CREATE 0 /* Opcode to destroy previously created command buffer */ #define HL_CB_OP_DESTROY 1 /* Opcode to retrieve information about a command buffer */ #define HL_CB_OP_INFO 2
/* 2MB minus 32 bytes for 2xMSG_PROT */ #define HL_MAX_CB_SIZE (0x200000 - 32)
/* Indicates whether the command buffer should be mapped to the device's MMU */ #define HL_CB_FLAGS_MAP 0x1
/* Used with HL_CB_OP_INFO opcode to get the device va address for kernel mapped CB */ #define HL_CB_FLAGS_GET_DEVICE_VA 0x2
struct hl_cb_in { /* Handle of CB or 0 if we want to create one */
__u64 cb_handle; /* HL_CB_OP_* */
__u32 op;
/* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that * will be allocated, regardless of this parameter's value, is PAGE_SIZE
*/
__u32 cb_size;
/* Context ID - Currently not in use */
__u32 ctx_id; /* HL_CB_FLAGS_* */
__u32 flags;
};
struct hl_cb_out { union { /* Handle of CB */
__u64 cb_handle;
union { /* Information about CB */ struct { /* Usage count of CB */
__u32 usage_cnt;
__u32 pad;
};
union hl_cb_args { struct hl_cb_in in; struct hl_cb_out out;
};
/* HL_CS_CHUNK_FLAGS_ values * * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB: * Indicates if the CB was allocated and mapped by userspace * (relevant to Gaudi2 and later). User allocated CB is a command buffer, * allocated by the user, via malloc (or similar). After allocating the * CB, the user invokes - “memory ioctl” to map the user memory into a * device virtual address. The user provides this address via the * cb_handle field. The interface provides the ability to create a * large CBs, Which aren’t limited to “HL_MAX_CB_SIZE”. Therefore, it * increases the PCI-DMA queues throughput. This CB allocation method * also reduces the use of Linux DMA-able memory pool. Which are limited * and used by other Linux sub-systems.
*/ #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1
/* * This structure size must always be fixed to 64-bytes for backward * compatibility
*/ struct hl_cs_chunk { union { /* Goya/Gaudi: * For external queue, this represents a Handle of CB on the * Host. * For internal queue in Goya, this represents an SRAM or * a DRAM address of the internal CB. In Gaudi, this might also * represent a mapped host address of the CB. * * Gaudi2 onwards: * For H/W queue, this represents either a Handle of CB on the * Host, or an SRAM, a DRAM, or a mapped host address of the CB. * * A mapped host address is in the device address space, after * a host address was mapped by the device MMU.
*/
__u64 cb_handle;
/* Relevant only when HL_CS_FLAGS_WAIT or * HL_CS_FLAGS_COLLECTIVE_WAIT is set * This holds address of array of u64 values that contain * signal CS sequence numbers. The wait described by * this job will listen on all those signals * (wait event per signal)
*/
__u64 signal_seq_arr;
/* * Relevant only when HL_CS_FLAGS_WAIT or * HL_CS_FLAGS_COLLECTIVE_WAIT is set * along with HL_CS_FLAGS_ENCAP_SIGNALS. * This is the CS sequence which has the encapsulated signals.
*/
__u64 encaps_signal_seq;
};
/* Index of queue to put the CB on */
__u32 queue_index;
union { /* * Size of command buffer with valid packets * Can be smaller then actual CB size
*/
__u32 cb_size;
/* Relevant only when HL_CS_FLAGS_WAIT or * HL_CS_FLAGS_COLLECTIVE_WAIT is set. * Number of entries in signal_seq_arr
*/
__u32 num_signal_seq_arr;
/* Relevant only when HL_CS_FLAGS_WAIT or * HL_CS_FLAGS_COLLECTIVE_WAIT is set along * with HL_CS_FLAGS_ENCAP_SIGNALS * This set the signals range that the user want to wait for * out of the whole reserved signals range. * e.g if the signals range is 20, and user don't want * to wait for signal 8, so he set this offset to 7, then * he call the API again with 9 and so on till 20.
*/
__u32 encaps_signal_offset;
};
/* HL_CS_CHUNK_FLAGS_* */
__u32 cs_chunk_flags;
/* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set. * This holds the collective engine ID. The wait described by this job * will sync with this engine and with all NICs before completion.
*/
__u32 collective_engine_id;
/* Align structure to 64 bytes */
__u32 pad[10];
};
/* * The encapsulated signals CS is merged into the existing CS ioctls. * In order to use this feature need to follow the below procedure: * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY * the output of this API will be the SOB offset from CFG_BASE. * this address will be used to patch CB cmds to do the signaling for this * SOB by incrementing it's value. * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY * CS type, note that this might fail if out-of-sync happened to the SOB * value, in case other signaling request to the same SOB occurred between * reserve-unreserve calls. * 2. Use the staged CS to do the encapsulated signaling jobs. * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset * field. This offset allows app to wait on part of the reserved signals. * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag * to wait for the encapsulated signals.
*/ #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000
/* * The engine cores CS is merged into the existing CS ioctls. * Use it to control the engine cores mode.
*/ #define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000
/* * The flush HBW PCI writes is merged into the existing CS ioctls. * Used to flush all HBW PCI writes. * This is a blocking operation and for this reason the user shall not use * the return sequence number (which will be invalid anyway)
*/ #define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000
/* * The engines CS is merged into the existing CS ioctls. * Use it to control engines modes.
*/ #define HL_CS_FLAGS_ENGINES_COMMAND 0x10000
union { struct { /* this holds address of array of hl_cs_chunk for restore phase */
__u64 chunks_restore;
/* holds address of array of hl_cs_chunk for execution phase */
__u64 chunks_execute;
};
/* Valid only when HL_CS_FLAGS_ENGINE_CORE_COMMAND is set */ struct { /* this holds address of array of uint32 for engine_cores */
__u64 engine_cores;
/* number of engine cores in engine_cores array */
__u32 num_engine_cores;
/* the core command to be sent towards engine cores */
__u32 core_command;
};
/* Valid only when HL_CS_FLAGS_ENGINES_COMMAND is set */ struct { /* this holds address of array of uint32 for engines */
__u64 engines;
/* number of engines in engines array */
__u32 num_engines;
/* the engine command to be sent towards engines */
__u32 engine_command;
};
};
union { /* * Sequence number of a staged submission CS * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset.
*/
__u64 seq;
/* * Encapsulated signals handle id * Valid for two flows: * 1. CS with encapsulated signals: * when HL_CS_FLAGS_STAGED_SUBMISSION and * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST * and HL_CS_FLAGS_ENCAP_SIGNALS are set. * 2. unreserve signals: * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set.
*/
__u32 encaps_sig_handle_id;
/* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ struct { /* Encapsulated signals number */
__u32 encaps_signals_count;
/* Number of chunks in restore phase array. Maximum number is * HL_MAX_JOBS_PER_CS
*/
__u32 num_chunks_restore;
/* Number of chunks in execution array. Maximum number is * HL_MAX_JOBS_PER_CS
*/
__u32 num_chunks_execute;
/* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT * is set
*/
__u32 timeout;
/* HL_CS_FLAGS_* */
__u32 cs_flags;
/* Context ID - Currently not in use */
__u32 ctx_id;
__u8 pad[4];
};
struct hl_cs_out { union { /* * seq holds the sequence number of the CS to pass to wait * ioctl. All values are valid except for 0 and ULLONG_MAX
*/
__u64 seq;
/* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ struct { /* This is the reserved signal handle id */
__u32 handle_id;
/* This is the signals count */
__u32 count;
};
};
/* HL_CS_STATUS */
__u32 status;
/* * SOB base address offset * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY or HL_CS_FLAGS_SIGNAL is set
*/
__u32 sob_base_addr_offset;
/* * Count of completed signals in SOB before current signal submission. * Valid only when (HL_CS_FLAGS_ENCAP_SIGNALS & HL_CS_FLAGS_STAGED_SUBMISSION) * or HL_CS_FLAGS_SIGNAL is set
*/
__u16 sob_count_before_submission;
__u16 pad[3];
};
union hl_cs_args { struct hl_cs_in in; struct hl_cs_out out;
};
struct hl_wait_cs_in { union { struct { /* * In case of wait_cs holds the CS sequence number. * In case of wait for multi CS hold a user pointer to * an array of CS sequence numbers
*/
__u64 seq; /* Absolute timeout to wait for command submission * in microseconds
*/
__u64 timeout_us;
};
struct { union { /* User address for completion comparison. * upon interrupt, driver will compare the value pointed * by this address with the supplied target value. * in order not to perform any comparison, set address * to all 1s. * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set
*/
__u64 addr;
/* cq_counters_handle to a kernel mapped cb which contains * cq counters. * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set
*/
__u64 cq_counters_handle;
};
/* Target value for completion comparison */
__u64 target;
};
};
/* Context ID - Currently not in use */
__u32 ctx_id;
/* HL_WAIT_CS_FLAGS_* * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK * * in order to wait for any CQ interrupt, set interrupt value to * HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT. * * in order to wait for any decoder interrupt, set interrupt value to * HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT.
*/
__u32 flags;
union { struct { /* Multi CS API info- valid entries in multi-CS array */
__u8 seq_arr_len;
__u8 pad[7];
};
/* Absolute timeout to wait for an interrupt in microseconds. * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set
*/
__u64 interrupt_timeout_us;
};
/* * cq counter offset inside the counters cb pointed by cq_counters_handle above. * upon interrupt, driver will compare the value pointed * by this address (cq_counters_handle + cq_counters_offset) * with the supplied target value. * relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set
*/
__u64 cq_counters_offset;
/* * Timestamp_handle timestamps buffer handle. * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set
*/
__u64 timestamp_handle;
/* * Timestamp_offset is offset inside the timestamp buffer pointed by timestamp_handle above. * upon interrupt, if the cq reached the target value then driver will write * timestamp to this offset. * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set
*/
__u64 timestamp_offset;
};
struct hl_wait_cs_out { /* HL_WAIT_CS_STATUS_* */
__u32 status; /* HL_WAIT_CS_STATUS_FLAG* */
__u32 flags; /* * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set * for wait_cs: timestamp of CS completion * for wait_multi_cs: timestamp of FIRST CS completion
*/
__s64 timestamp_nsec; /* multi CS completion bitmap */
__u32 cs_completion_map;
__u32 pad;
};
union hl_wait_cs_args { struct hl_wait_cs_in in; struct hl_wait_cs_out out;
};
/* Opcode to allocate device memory */ #define HL_MEM_OP_ALLOC 0
/* Opcode to map host and device memory */ #define HL_MEM_OP_MAP 2
/* Opcode to unmap previously mapped host and device memory */ #define HL_MEM_OP_UNMAP 3
/* Opcode to map a hw block */ #define HL_MEM_OP_MAP_BLOCK 4
/* Opcode to create DMA-BUF object for an existing device memory allocation * and to export an FD of that DMA-BUF back to the caller
*/ #define HL_MEM_OP_EXPORT_DMABUF_FD 5
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