#define IOCR_OUTPUTS_OFFSET 0 /* (rw) offset for the number of OUTs in the
* ConfES register. */ #define IOCR_INPUTS_OFFSET 8 /* (rw) offset for the number of INs in the
* ConfES register. */ #define FREQ_RATIO_OFFSET 19 /* (rw) offset for frequency ratio in the
* ConfES register. */ #define FREQ_RATIO_SINGLE_MODE 0x01 /* value for single mode frequency ratio:
* sample rate = frequency rate. */
/* the capture bit position in the object_id field in driver commands depends upon the number of managed channels. For now, 64 IN + 64 OUT are supported. HOwever, the communication protocol forsees 1024 channels, hence bit 10 indicates a capture (input) object).
*/ #define ID_IS_CAPTURE (1L << 10) #define ID_OFFSET 13 /* object ID is at the 13th bit in the
* 1st command word.*/ #define ID_CH_MASK 0x3F #define OPCODE_OFFSET 24 /* offset of the command opcode in the first
* command word.*/
/* pipe states */ enum pipe_state_t {
PSTATE_IDLE = 0, /* the pipe is not processed in the XES_IRQ
* (free or stopped, or paused). */
PSTATE_RUN = 1, /* sustained play/record state. */
PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do
* not DMA, record pipe do a last DMA. */
PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do * not yet increase their sample count, record
* pipes do not DMA. */
PSTATE_CLOSING = 4, /* the pipe is releasing, and may not yet
* receive an "alloc" command. */
};
/* stream states */ enum stream_state_t {
SSTATE_STOP = 0x00, /* setting to stop resets the stream spl
* count.*/
SSTATE_RUN = (0x01 << 0), /* start DMA and spl count handling. */
SSTATE_PAUSE = (0x01 << 1), /* pause DMA and spl count handling. */
};
/* buffer flags */ enum buffer_flags {
BF_VALID = 0x80, /* set if the buffer is valid, clear if free.*/
BF_CURRENT = 0x40, /* set if this is the current buffer (there is
* always a current buffer).*/
BF_NOTIFY_EOB = 0x20, /* set if this buffer must cause a PCI event
* when finished.*/
BF_CIRCULAR = 0x10, /* set if buffer[1] must be copied to buffer[0]
* by the end of this buffer.*/
BF_64BITS_ADR = 0x08, /* set if the hi part of the address is valid.*/
BF_xx = 0x04, /* future extension.*/
BF_EOB = 0x02, /* set if finished, but not yet free.*/
BF_PAUSE = 0x01, /* pause stream at buffer end.*/
BF_ZERO = 0x00, /* no flags (init).*/
};
/* * Stream Flags definitions
*/ enum stream_flags {
SF_ZERO = 0x00000000, /* no flags (stream invalid). */
SF_VALID = 0x10000000, /* the stream has a valid DMA_conf
* info (setstreamformat). */
SF_XRUN = 0x20000000, /* the stream is un x-run state. */
SF_START = 0x40000000, /* the DMA is running.*/
SF_ASIO = 0x80000000, /* ASIO.*/
};
#define MASK_SPL_COUNT_HI 0x00FFFFFF /* 4 MSBits are status bits */ #define PSTATE_OFFSET 28 /* 4 MSBits are status bits */
#define MASK_STREAM_HAS_MAPPING (1L << 12) #define MASK_STREAM_IS_ASIO (1L << 9) #define STREAM_FMT_OFFSET 10 /* the stream fmt bits start at the 10th
* bit in the command word. */
#define FREQ_FIELD_OFFSET 15 /* offset of the freq field in the response
* word */
#define BUFF_FLAGS_OFFSET 24 /* offset of the buffer flags in the
* response word. */ #define MASK_DATA_SIZE 0x00FFFFFF /* this must match the field size of
* datasize in the buffer_t structure. */
#define MASK_BUFFER_ID 0xFF /* the cancel command awaits a buffer ID,
* may be 0xFF for "current". */
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