Quelle  acp_2_2_sh_mask.h   Sprache: C

/*
 * ACP_2_2 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef ACP_2_2_SH_MASK_H
#define ACP_2_2_SH_MASK_H

#define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_1__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_1__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_1__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_1__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_1__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_1__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_2__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_2__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_2__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_2__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_2__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_2__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_3__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_3__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_3__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_3__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_3__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_3__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_4__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_4__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_4__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_4__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_4__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_4__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_5__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_5__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_5__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_5__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_5__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_5__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_6__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_6__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_6__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_6__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_6__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_6__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_7__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_7__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_7__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_7__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_7__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_7__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_8__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_8__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_8__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_8__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_8__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_8__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_8__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_8__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_8__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_9__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_9__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_9__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_9__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_9__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_9__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_9__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_9__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_9__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_9__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_10__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_10__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_10__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_10__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_10__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_10__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_10__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_10__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_10__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_10__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_11__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_11__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_11__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_11__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_11__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_11__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_11__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_11__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_11__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_11__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_12__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_12__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_12__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_12__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_12__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_12__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_12__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_12__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_12__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_12__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_13__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_13__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_13__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_13__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_13__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_13__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_13__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_13__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_13__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_13__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_14__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_14__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_14__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_14__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_14__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_14__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_14__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_14__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_14__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_14__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_CNTL_15__DMAChRst_MASK 0x1
#define ACP_DMA_CNTL_15__DMAChRst__SHIFT 0x0
#define ACP_DMA_CNTL_15__DMAChRun_MASK 0x2
#define ACP_DMA_CNTL_15__DMAChRun__SHIFT 0x1
#define ACP_DMA_CNTL_15__DMAChIOCEn_MASK 0x4
#define ACP_DMA_CNTL_15__DMAChIOCEn__SHIFT 0x2
#define ACP_DMA_CNTL_15__Circular_DMA_En_MASK 0x8
#define ACP_DMA_CNTL_15__Circular_DMA_En__SHIFT 0x3
#define ACP_DMA_CNTL_15__DMAChGracefulRstEn_MASK 0x10
#define ACP_DMA_CNTL_15__DMAChGracefulRstEn__SHIFT 0x4
#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx_MASK 0x3ff
#define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt_MASK 0x3ff
#define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt__SHIFT 0x0
#define ACP_DMA_PRIO_0__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_0__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_1__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_1__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_2__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_2__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_3__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_3__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_4__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_4__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_5__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_5__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_6__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_6__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_7__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_7__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_8__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_8__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_9__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_9__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_10__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_10__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_11__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_11__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_12__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_12__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_13__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_13__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_14__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_14__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_PRIO_15__DMAChPrioLvl_MASK 0x1
#define ACP_DMA_PRIO_15__DMAChPrioLvl__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx_MASK 0x3ff
#define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt_MASK 0x1ffff
#define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt__SHIFT 0x0
#define ACP_DMA_ERR_STS_0__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_0__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_0__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_0__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_1__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_1__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_1__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_1__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_2__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_2__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_2__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_2__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_3__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_3__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_3__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_3__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_4__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_4__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_4__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_4__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_5__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_5__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_5__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_5__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_6__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_6__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_6__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_6__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_7__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_7__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_7__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_7__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_8__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_8__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_8__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_8__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_9__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_9__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_9__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_9__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_10__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_10__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_10__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_10__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_11__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_11__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_11__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_11__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_12__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_12__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_12__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_12__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_13__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_13__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_13__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_13__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_14__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_14__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_14__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_14__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_ERR_STS_15__DMAChTermErr_MASK 0x1
#define ACP_DMA_ERR_STS_15__DMAChTermErr__SHIFT 0x0
#define ACP_DMA_ERR_STS_15__DMAChErrCode_MASK 0x1e
#define ACP_DMA_ERR_STS_15__DMAChErrCode__SHIFT 0x1
#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr_MASK 0xffffffff
#define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr__SHIFT 0x0
#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr_MASK 0xf
#define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr__SHIFT 0x0
#define ACP_DMA_CH_STS__DMAChSts_MASK 0xffff
#define ACP_DMA_CH_STS__DMAChSts__SHIFT 0x0
#define ACP_DMA_CH_GROUP__DMAChanelGrouping_MASK 0x1
#define ACP_DMA_CH_GROUP__DMAChanelGrouping__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET0__Offset_MASK 0xfffffff
#define ACP_DSP0_CACHE_OFFSET0__Offset__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_CACHE_SIZE0__Size_MASK 0xffffff
#define ACP_DSP0_CACHE_SIZE0__Size__SHIFT 0x0
#define ACP_DSP0_CACHE_SIZE0__PageEnable_MASK 0x80000000
#define ACP_DSP0_CACHE_SIZE0__PageEnable__SHIFT 0x1f
#define ACP_DSP0_CACHE_OFFSET1__Offset_MASK 0xfffffff
#define ACP_DSP0_CACHE_OFFSET1__Offset__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_CACHE_SIZE1__Size_MASK 0xffffff
#define ACP_DSP0_CACHE_SIZE1__Size__SHIFT 0x0
#define ACP_DSP0_CACHE_SIZE1__PageEnable_MASK 0x80000000
#define ACP_DSP0_CACHE_SIZE1__PageEnable__SHIFT 0x1f
#define ACP_DSP0_CACHE_OFFSET2__Offset_MASK 0xfffffff
#define ACP_DSP0_CACHE_OFFSET2__Offset__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_CACHE_SIZE2__Size_MASK 0xffffff
#define ACP_DSP0_CACHE_SIZE2__Size__SHIFT 0x0
#define ACP_DSP0_CACHE_SIZE2__PageEnable_MASK 0x80000000
#define ACP_DSP0_CACHE_SIZE2__PageEnable__SHIFT 0x1f
#define ACP_DSP0_CACHE_OFFSET3__Offset_MASK 0xfffffff
#define ACP_DSP0_CACHE_OFFSET3__Offset__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_CACHE_SIZE3__Size_MASK 0xffffff
#define ACP_DSP0_CACHE_SIZE3__Size__SHIFT 0x0
#define ACP_DSP0_CACHE_SIZE3__PageEnable_MASK 0x80000000
#define ACP_DSP0_CACHE_SIZE3__PageEnable__SHIFT 0x1f
#define ACP_DSP0_CACHE_OFFSET4__Offset_MASK 0xfffffff
#define ACP_DSP0_CACHE_OFFSET4__Offset__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_CACHE_SIZE4__Size_MASK 0xffffff
#define ACP_DSP0_CACHE_SIZE4__Size__SHIFT 0x0
#define ACP_DSP0_CACHE_SIZE4__PageEnable_MASK 0x80000000
#define ACP_DSP0_CACHE_SIZE4__PageEnable__SHIFT 0x1f
#define ACP_DSP0_CACHE_OFFSET5__Offset_MASK 0xfffffff
#define ACP_DSP0_CACHE_OFFSET5__Offset__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_CACHE_SIZE5__Size_MASK 0xffffff
#define ACP_DSP0_CACHE_SIZE5__Size__SHIFT 0x0
#define ACP_DSP0_CACHE_SIZE5__PageEnable_MASK 0x80000000
#define ACP_DSP0_CACHE_SIZE5__PageEnable__SHIFT 0x1f
#define ACP_DSP0_CACHE_OFFSET6__Offset_MASK 0xfffffff
#define ACP_DSP0_CACHE_OFFSET6__Offset__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_CACHE_SIZE6__Size_MASK 0xffffff
#define ACP_DSP0_CACHE_SIZE6__Size__SHIFT 0x0
#define ACP_DSP0_CACHE_SIZE6__PageEnable_MASK 0x80000000
#define ACP_DSP0_CACHE_SIZE6__PageEnable__SHIFT 0x1f
#define ACP_DSP0_CACHE_OFFSET7__Offset_MASK 0xfffffff
#define ACP_DSP0_CACHE_OFFSET7__Offset__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_CACHE_SIZE7__Size_MASK 0xffffff
#define ACP_DSP0_CACHE_SIZE7__Size__SHIFT 0x0
#define ACP_DSP0_CACHE_SIZE7__PageEnable_MASK 0x80000000
#define ACP_DSP0_CACHE_SIZE7__PageEnable__SHIFT 0x1f
#define ACP_DSP0_CACHE_OFFSET8__Offset_MASK 0xfffffff
#define ACP_DSP0_CACHE_OFFSET8__Offset__SHIFT 0x0
#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_CACHE_SIZE8__Size_MASK 0xffffff
#define ACP_DSP0_CACHE_SIZE8__Size__SHIFT 0x0
#define ACP_DSP0_CACHE_SIZE8__PageEnable_MASK 0x80000000
#define ACP_DSP0_CACHE_SIZE8__PageEnable__SHIFT 0x1f
#define ACP_DSP0_NONCACHE_OFFSET0__Offset_MASK 0xfffffff
#define ACP_DSP0_NONCACHE_OFFSET0__Offset__SHIFT 0x0
#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_NONCACHE_SIZE0__Size_MASK 0xffffff
#define ACP_DSP0_NONCACHE_SIZE0__Size__SHIFT 0x0
#define ACP_DSP0_NONCACHE_SIZE0__PageEnable_MASK 0x80000000
#define ACP_DSP0_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f
#define ACP_DSP0_NONCACHE_OFFSET1__Offset_MASK 0xfffffff
#define ACP_DSP0_NONCACHE_OFFSET1__Offset__SHIFT 0x0
#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP0_NONCACHE_SIZE1__Size_MASK 0xffffff
#define ACP_DSP0_NONCACHE_SIZE1__Size__SHIFT 0x0
#define ACP_DSP0_NONCACHE_SIZE1__PageEnable_MASK 0x80000000
#define ACP_DSP0_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f
#define ACP_DSP0_DEBUG_PC__DebugPC_MASK 0xffffffff
#define ACP_DSP0_DEBUG_PC__DebugPC__SHIFT 0x0
#define ACP_DSP0_NMI_SEL__NMISel_MASK 0x1
#define ACP_DSP0_NMI_SEL__NMISel__SHIFT 0x0
#define ACP_DSP0_CLKRST_CNTL__ClkEn_MASK 0x1
#define ACP_DSP0_CLKRST_CNTL__ClkEn__SHIFT 0x0
#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP_MASK 0x2
#define ACP_DSP0_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1
#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4
#define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2
#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8
#define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3
#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10
#define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4
#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status_MASK 0x20
#define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5
#define ACP_DSP0_RUNSTALL__RunStallCntl_MASK 0x1
#define ACP_DSP0_RUNSTALL__RunStallCntl__SHIFT 0x0
#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1
#define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0
#define ACP_DSP0_WAIT_MODE__WaitMode_MASK 0x1
#define ACP_DSP0_WAIT_MODE__WaitMode__SHIFT 0x0
#define ACP_DSP0_VECT_SEL__StaticVectorSel_MASK 0x1
#define ACP_DSP0_VECT_SEL__StaticVectorSel__SHIFT 0x0
#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff
#define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0
#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff
#define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0
#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff
#define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET0__Offset_MASK 0xfffffff
#define ACP_DSP1_CACHE_OFFSET0__Offset__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_CACHE_SIZE0__Size_MASK 0xffffff
#define ACP_DSP1_CACHE_SIZE0__Size__SHIFT 0x0
#define ACP_DSP1_CACHE_SIZE0__PageEnable_MASK 0x80000000
#define ACP_DSP1_CACHE_SIZE0__PageEnable__SHIFT 0x1f
#define ACP_DSP1_CACHE_OFFSET1__Offset_MASK 0xfffffff
#define ACP_DSP1_CACHE_OFFSET1__Offset__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_CACHE_SIZE1__Size_MASK 0xffffff
#define ACP_DSP1_CACHE_SIZE1__Size__SHIFT 0x0
#define ACP_DSP1_CACHE_SIZE1__PageEnable_MASK 0x80000000
#define ACP_DSP1_CACHE_SIZE1__PageEnable__SHIFT 0x1f
#define ACP_DSP1_CACHE_OFFSET2__Offset_MASK 0xfffffff
#define ACP_DSP1_CACHE_OFFSET2__Offset__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_CACHE_SIZE2__Size_MASK 0xffffff
#define ACP_DSP1_CACHE_SIZE2__Size__SHIFT 0x0
#define ACP_DSP1_CACHE_SIZE2__PageEnable_MASK 0x80000000
#define ACP_DSP1_CACHE_SIZE2__PageEnable__SHIFT 0x1f
#define ACP_DSP1_CACHE_OFFSET3__Offset_MASK 0xfffffff
#define ACP_DSP1_CACHE_OFFSET3__Offset__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_CACHE_SIZE3__Size_MASK 0xffffff
#define ACP_DSP1_CACHE_SIZE3__Size__SHIFT 0x0
#define ACP_DSP1_CACHE_SIZE3__PageEnable_MASK 0x80000000
#define ACP_DSP1_CACHE_SIZE3__PageEnable__SHIFT 0x1f
#define ACP_DSP1_CACHE_OFFSET4__Offset_MASK 0xfffffff
#define ACP_DSP1_CACHE_OFFSET4__Offset__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_CACHE_SIZE4__Size_MASK 0xffffff
#define ACP_DSP1_CACHE_SIZE4__Size__SHIFT 0x0
#define ACP_DSP1_CACHE_SIZE4__PageEnable_MASK 0x80000000
#define ACP_DSP1_CACHE_SIZE4__PageEnable__SHIFT 0x1f
#define ACP_DSP1_CACHE_OFFSET5__Offset_MASK 0xfffffff
#define ACP_DSP1_CACHE_OFFSET5__Offset__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_CACHE_SIZE5__Size_MASK 0xffffff
#define ACP_DSP1_CACHE_SIZE5__Size__SHIFT 0x0
#define ACP_DSP1_CACHE_SIZE5__PageEnable_MASK 0x80000000
#define ACP_DSP1_CACHE_SIZE5__PageEnable__SHIFT 0x1f
#define ACP_DSP1_CACHE_OFFSET6__Offset_MASK 0xfffffff
#define ACP_DSP1_CACHE_OFFSET6__Offset__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_CACHE_SIZE6__Size_MASK 0xffffff
#define ACP_DSP1_CACHE_SIZE6__Size__SHIFT 0x0
#define ACP_DSP1_CACHE_SIZE6__PageEnable_MASK 0x80000000
#define ACP_DSP1_CACHE_SIZE6__PageEnable__SHIFT 0x1f
#define ACP_DSP1_CACHE_OFFSET7__Offset_MASK 0xfffffff
#define ACP_DSP1_CACHE_OFFSET7__Offset__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_CACHE_SIZE7__Size_MASK 0xffffff
#define ACP_DSP1_CACHE_SIZE7__Size__SHIFT 0x0
#define ACP_DSP1_CACHE_SIZE7__PageEnable_MASK 0x80000000
#define ACP_DSP1_CACHE_SIZE7__PageEnable__SHIFT 0x1f
#define ACP_DSP1_CACHE_OFFSET8__Offset_MASK 0xfffffff
#define ACP_DSP1_CACHE_OFFSET8__Offset__SHIFT 0x0
#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_CACHE_SIZE8__Size_MASK 0xffffff
#define ACP_DSP1_CACHE_SIZE8__Size__SHIFT 0x0
#define ACP_DSP1_CACHE_SIZE8__PageEnable_MASK 0x80000000
#define ACP_DSP1_CACHE_SIZE8__PageEnable__SHIFT 0x1f
#define ACP_DSP1_NONCACHE_OFFSET0__Offset_MASK 0xfffffff
#define ACP_DSP1_NONCACHE_OFFSET0__Offset__SHIFT 0x0
#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_NONCACHE_SIZE0__Size_MASK 0xffffff
#define ACP_DSP1_NONCACHE_SIZE0__Size__SHIFT 0x0
#define ACP_DSP1_NONCACHE_SIZE0__PageEnable_MASK 0x80000000
#define ACP_DSP1_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f
#define ACP_DSP1_NONCACHE_OFFSET1__Offset_MASK 0xfffffff
#define ACP_DSP1_NONCACHE_OFFSET1__Offset__SHIFT 0x0
#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP1_NONCACHE_SIZE1__Size_MASK 0xffffff
#define ACP_DSP1_NONCACHE_SIZE1__Size__SHIFT 0x0
#define ACP_DSP1_NONCACHE_SIZE1__PageEnable_MASK 0x80000000
#define ACP_DSP1_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f
#define ACP_DSP1_DEBUG_PC__DebugPC_MASK 0xffffffff
#define ACP_DSP1_DEBUG_PC__DebugPC__SHIFT 0x0
#define ACP_DSP1_NMI_SEL__NMISel_MASK 0x1
#define ACP_DSP1_NMI_SEL__NMISel__SHIFT 0x0
#define ACP_DSP1_CLKRST_CNTL__ClkEn_MASK 0x1
#define ACP_DSP1_CLKRST_CNTL__ClkEn__SHIFT 0x0
#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP_MASK 0x2
#define ACP_DSP1_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1
#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4
#define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2
#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8
#define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3
#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10
#define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4
#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status_MASK 0x20
#define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5
#define ACP_DSP1_RUNSTALL__RunStallCntl_MASK 0x1
#define ACP_DSP1_RUNSTALL__RunStallCntl__SHIFT 0x0
#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1
#define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0
#define ACP_DSP1_WAIT_MODE__WaitMode_MASK 0x1
#define ACP_DSP1_WAIT_MODE__WaitMode__SHIFT 0x0
#define ACP_DSP1_VECT_SEL__StaticVectorSel_MASK 0x1
#define ACP_DSP1_VECT_SEL__StaticVectorSel__SHIFT 0x0
#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff
#define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0
#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff
#define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0
#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff
#define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET0__Offset_MASK 0xfffffff
#define ACP_DSP2_CACHE_OFFSET0__Offset__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_CACHE_SIZE0__Size_MASK 0xffffff
#define ACP_DSP2_CACHE_SIZE0__Size__SHIFT 0x0
#define ACP_DSP2_CACHE_SIZE0__PageEnable_MASK 0x80000000
#define ACP_DSP2_CACHE_SIZE0__PageEnable__SHIFT 0x1f
#define ACP_DSP2_CACHE_OFFSET1__Offset_MASK 0xfffffff
#define ACP_DSP2_CACHE_OFFSET1__Offset__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_CACHE_SIZE1__Size_MASK 0xffffff
#define ACP_DSP2_CACHE_SIZE1__Size__SHIFT 0x0
#define ACP_DSP2_CACHE_SIZE1__PageEnable_MASK 0x80000000
#define ACP_DSP2_CACHE_SIZE1__PageEnable__SHIFT 0x1f
#define ACP_DSP2_CACHE_OFFSET2__Offset_MASK 0xfffffff
#define ACP_DSP2_CACHE_OFFSET2__Offset__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_CACHE_SIZE2__Size_MASK 0xffffff
#define ACP_DSP2_CACHE_SIZE2__Size__SHIFT 0x0
#define ACP_DSP2_CACHE_SIZE2__PageEnable_MASK 0x80000000
#define ACP_DSP2_CACHE_SIZE2__PageEnable__SHIFT 0x1f
#define ACP_DSP2_CACHE_OFFSET3__Offset_MASK 0xfffffff
#define ACP_DSP2_CACHE_OFFSET3__Offset__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_CACHE_SIZE3__Size_MASK 0xffffff
#define ACP_DSP2_CACHE_SIZE3__Size__SHIFT 0x0
#define ACP_DSP2_CACHE_SIZE3__PageEnable_MASK 0x80000000
#define ACP_DSP2_CACHE_SIZE3__PageEnable__SHIFT 0x1f
#define ACP_DSP2_CACHE_OFFSET4__Offset_MASK 0xfffffff
#define ACP_DSP2_CACHE_OFFSET4__Offset__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_CACHE_SIZE4__Size_MASK 0xffffff
#define ACP_DSP2_CACHE_SIZE4__Size__SHIFT 0x0
#define ACP_DSP2_CACHE_SIZE4__PageEnable_MASK 0x80000000
#define ACP_DSP2_CACHE_SIZE4__PageEnable__SHIFT 0x1f
#define ACP_DSP2_CACHE_OFFSET5__Offset_MASK 0xfffffff
#define ACP_DSP2_CACHE_OFFSET5__Offset__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_CACHE_SIZE5__Size_MASK 0xffffff
#define ACP_DSP2_CACHE_SIZE5__Size__SHIFT 0x0
#define ACP_DSP2_CACHE_SIZE5__PageEnable_MASK 0x80000000
#define ACP_DSP2_CACHE_SIZE5__PageEnable__SHIFT 0x1f
#define ACP_DSP2_CACHE_OFFSET6__Offset_MASK 0xfffffff
#define ACP_DSP2_CACHE_OFFSET6__Offset__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_CACHE_SIZE6__Size_MASK 0xffffff
#define ACP_DSP2_CACHE_SIZE6__Size__SHIFT 0x0
#define ACP_DSP2_CACHE_SIZE6__PageEnable_MASK 0x80000000
#define ACP_DSP2_CACHE_SIZE6__PageEnable__SHIFT 0x1f
#define ACP_DSP2_CACHE_OFFSET7__Offset_MASK 0xfffffff
#define ACP_DSP2_CACHE_OFFSET7__Offset__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_CACHE_SIZE7__Size_MASK 0xffffff
#define ACP_DSP2_CACHE_SIZE7__Size__SHIFT 0x0
#define ACP_DSP2_CACHE_SIZE7__PageEnable_MASK 0x80000000
#define ACP_DSP2_CACHE_SIZE7__PageEnable__SHIFT 0x1f
#define ACP_DSP2_CACHE_OFFSET8__Offset_MASK 0xfffffff
#define ACP_DSP2_CACHE_OFFSET8__Offset__SHIFT 0x0
#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_CACHE_SIZE8__Size_MASK 0xffffff
#define ACP_DSP2_CACHE_SIZE8__Size__SHIFT 0x0
#define ACP_DSP2_CACHE_SIZE8__PageEnable_MASK 0x80000000
#define ACP_DSP2_CACHE_SIZE8__PageEnable__SHIFT 0x1f
#define ACP_DSP2_NONCACHE_OFFSET0__Offset_MASK 0xfffffff
#define ACP_DSP2_NONCACHE_OFFSET0__Offset__SHIFT 0x0
#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_NONCACHE_SIZE0__Size_MASK 0xffffff
#define ACP_DSP2_NONCACHE_SIZE0__Size__SHIFT 0x0
#define ACP_DSP2_NONCACHE_SIZE0__PageEnable_MASK 0x80000000
#define ACP_DSP2_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f
#define ACP_DSP2_NONCACHE_OFFSET1__Offset_MASK 0xfffffff
#define ACP_DSP2_NONCACHE_OFFSET1__Offset__SHIFT 0x0
#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
#define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
#define ACP_DSP2_NONCACHE_SIZE1__Size_MASK 0xffffff
#define ACP_DSP2_NONCACHE_SIZE1__Size__SHIFT 0x0
#define ACP_DSP2_NONCACHE_SIZE1__PageEnable_MASK 0x80000000
#define ACP_DSP2_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f
#define ACP_DSP2_DEBUG_PC__DebugPC_MASK 0xffffffff
#define ACP_DSP2_DEBUG_PC__DebugPC__SHIFT 0x0
#define ACP_DSP2_NMI_SEL__NMISel_MASK 0x1
#define ACP_DSP2_NMI_SEL__NMISel__SHIFT 0x0
#define ACP_DSP2_CLKRST_CNTL__ClkEn_MASK 0x1
#define ACP_DSP2_CLKRST_CNTL__ClkEn__SHIFT 0x0
#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP_MASK 0x2
#define ACP_DSP2_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1
#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4
#define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2
#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8
#define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3
#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10
#define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4
#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status_MASK 0x20
#define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5
#define ACP_DSP2_RUNSTALL__RunStallCntl_MASK 0x1
#define ACP_DSP2_RUNSTALL__RunStallCntl__SHIFT 0x0
#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1
#define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0
#define ACP_DSP2_WAIT_MODE__WaitMode_MASK 0x1
#define ACP_DSP2_WAIT_MODE__WaitMode__SHIFT 0x0
#define ACP_DSP2_VECT_SEL__StaticVectorSel_MASK 0x1
#define ACP_DSP2_VECT_SEL__StaticVectorSel__SHIFT 0x0
#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff
#define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0
#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff
#define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0
#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff
#define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap_MASK 0x3
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap__SHIFT 0x0
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb_MASK 0x80
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb__SHIFT 0x7
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb_MASK 0x100
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb_MASK 0x400
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode_MASK 0x2000
#define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode__SHIFT 0xd
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000
#define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f
#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1
#define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0
#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff
#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0
#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000
#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f
#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff
#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0
#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000
#define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f
#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff
#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0
#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000
#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f
#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff
#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0
#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000
#define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap_MASK 0x3
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap__SHIFT 0x0
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb_MASK 0x80
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb__SHIFT 0x7
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb_MASK 0x100
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb_MASK 0x400
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode_MASK 0x2000
#define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode__SHIFT 0xd
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000
#define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f
#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1
#define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0
#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff
#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0
#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000
#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f
#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff
#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0
#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000
#define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f
#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff
#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0
#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000
#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f
#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff
#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0
#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000
#define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f
#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize_MASK 0x3
#define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr_MASK 0xfffffff
#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK 0x20000000
#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel__SHIFT 0x1d
#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK 0x40000000
#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel__SHIFT 0x1e
#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK 0x80000000
#define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable__SHIFT 0x1f
#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize_MASK 0x3
#define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr_MASK 0xfffffff
#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel_MASK 0x20000000
#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel__SHIFT 0x1d
#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel_MASK 0x40000000
#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel__SHIFT 0x1e
#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable_MASK 0x80000000
#define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable__SHIFT 0x1f
#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize_MASK 0x3
#define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr_MASK 0xfffffff
#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel_MASK 0x20000000
#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel__SHIFT 0x1d
#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel_MASK 0x40000000
#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel__SHIFT 0x1e
#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable_MASK 0x80000000
#define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable__SHIFT 0x1f
#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize_MASK 0x3
#define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr_MASK 0xfffffff
#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel_MASK 0x20000000
#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel__SHIFT 0x1d
#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel_MASK 0x40000000
#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel__SHIFT 0x1e
#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable_MASK 0x80000000
#define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable__SHIFT 0x1f
#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize_MASK 0x3
#define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr_MASK 0xfffffff
#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel_MASK 0x20000000
#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel__SHIFT 0x1d
#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel_MASK 0x40000000
#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel__SHIFT 0x1e
#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable_MASK 0x80000000
#define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable__SHIFT 0x1f
#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize_MASK 0x3
#define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr_MASK 0xfffffff
#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel_MASK 0x20000000
#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel__SHIFT 0x1d
#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel_MASK 0x40000000
#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel__SHIFT 0x1e
#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable_MASK 0x80000000
#define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable__SHIFT 0x1f
#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize_MASK 0x3
#define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr_MASK 0xfffffff
#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel_MASK 0x20000000
#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel__SHIFT 0x1d
#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel_MASK 0x40000000
#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel__SHIFT 0x1e
#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable_MASK 0x80000000
#define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable__SHIFT 0x1f
#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize_MASK 0x3
#define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr_MASK 0xfffffff
#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr__SHIFT 0x0
#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel_MASK 0x20000000
#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel__SHIFT 0x1d
#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel_MASK 0x40000000
#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel__SHIFT 0x1e
#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable_MASK 0x80000000
#define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable__SHIFT 0x1f
#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate_MASK 0x1
#define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate__SHIFT 0x0
#define ACP_CONTROL__ClkEn_MASK 0x1
#define ACP_CONTROL__ClkEn__SHIFT 0x0
#define ACP_CONTROL__JtagEn_MASK 0x400
#define ACP_CONTROL__JtagEn__SHIFT 0xa
#define ACP_STATUS__ClkOn_MASK 0x1
#define ACP_STATUS__ClkOn__SHIFT 0x0
#define ACP_STATUS__ACPRefClkSpd_MASK 0x2
#define ACP_STATUS__ACPRefClkSpd__SHIFT 0x1
#define ACP_STATUS__SMUStutterLastEdge_MASK 0x4
#define ACP_STATUS__SMUStutterLastEdge__SHIFT 0x2
#define ACP_STATUS__MCStutterLastEdge_MASK 0x8
#define ACP_STATUS__MCStutterLastEdge__SHIFT 0x3
#define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
#define ACP_SOFT_RESET__SoftResetAud__SHIFT 0x8
#define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200
#define ACP_SOFT_RESET__SoftResetDMA__SHIFT 0x9
#define ACP_SOFT_RESET__InternalSoftResetMode_MASK 0x4000
#define ACP_SOFT_RESET__InternalSoftResetMode__SHIFT 0xe
#define ACP_SOFT_RESET__ExternalSoftResetMode_MASK 0x8000
#define ACP_SOFT_RESET__ExternalSoftResetMode__SHIFT 0xf
#define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
#define ACP_SOFT_RESET__SoftResetAudDone__SHIFT 0x18
#define ACP_SOFT_RESET__SoftResetDMADone_MASK 0x2000000
#define ACP_SOFT_RESET__SoftResetDMADone__SHIFT 0x19
#define ACP_PwrMgmt_CNTL__SCLKSleepCntl_MASK 0x3
#define ACP_PwrMgmt_CNTL__SCLKSleepCntl__SHIFT 0x0
#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter_MASK 0xffff
#define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter__SHIFT 0x0
#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox_MASK 0xffffffff
#define ACP_SMU_MAILBOX__ACP_SMU_Mailbox__SHIFT 0x0
#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg_MASK 0xffffffff
#define ACP_FUTURE_REG_SCLK_0__ACPFutureReg__SHIFT 0x0
#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg_MASK 0xffffffff
#define ACP_FUTURE_REG_SCLK_1__ACPFutureReg__SHIFT 0x0
#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg_MASK 0xffffffff
#define ACP_FUTURE_REG_SCLK_2__ACPFutureReg__SHIFT 0x0
#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg_MASK 0xffffffff
#define ACP_FUTURE_REG_SCLK_3__ACPFutureReg__SHIFT 0x0
#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg_MASK 0xffffffff
#define ACP_FUTURE_REG_SCLK_4__ACPFutureReg__SHIFT 0x0
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable_MASK 0x1
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable__SHIFT 0x0
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable_MASK 0x2
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable__SHIFT 0x1
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable_MASK 0x4
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable__SHIFT 0x2
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable_MASK 0x8
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable__SHIFT 0x3
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable_MASK 0x10
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable__SHIFT 0x4
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable_MASK 0x20
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable__SHIFT 0x5
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable_MASK 0x40
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable__SHIFT 0x6
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable_MASK 0x80
#define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable__SHIFT 0x7
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable_MASK 0x100
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable__SHIFT 0x8
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x200
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable__SHIFT 0x9
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable_MASK 0x400
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT 0xa
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable_MASK 0x800
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable__SHIFT 0xb
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable_MASK 0x1000
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable__SHIFT 0xc
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable_MASK 0x2000
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable__SHIFT 0xd
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable_MASK 0x4000
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable__SHIFT 0xe
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable_MASK 0x8000
#define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable__SHIFT 0xf
#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt_MASK 0xffff
#define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt__SHIFT 0x0
#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt_MASK 0xffff
#define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt__SHIFT 0x0
#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt_MASK 0xffff
#define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt__SHIFT 0x0
#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt_MASK 0xffff
#define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt__SHIFT 0x0
#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt_MASK 0xffff
#define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt__SHIFT 0x0
#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt_MASK 0xffff
#define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt__SHIFT 0x0
#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt_MASK 0xffff
#define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt__SHIFT 0x0
#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt_MASK 0xffff
#define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt__SHIFT 0x0
#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt_MASK 0xffff
#define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt__SHIFT 0x0
#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt_MASK 0xffff
#define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt__SHIFT 0x0
#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt_MASK 0xffff
#define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt__SHIFT 0x0
#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt_MASK 0xffff
#define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt__SHIFT 0x0
#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt_MASK 0xffff
#define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt__SHIFT 0x0
#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt_MASK 0xffff
#define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt__SHIFT 0x0
#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt_MASK 0xffff
#define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt__SHIFT 0x0
#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt_MASK 0xffff
#define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt__SHIFT 0x0
#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl_MASK 0xf
#define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl__SHIFT 0x0
#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb_MASK 0x1
#define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb__SHIFT 0x0
#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask_MASK 0x1
#define ACP_EXTERNAL_INTR_CNTL__ACPErrMask__SHIFT 0x0
#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask_MASK 0x2
#define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1
#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4
#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2
#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8
#define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3
#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask_MASK 0x10
#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4
#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask_MASK 0x40
#define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6
#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask_MASK 0x100
#define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask__SHIFT 0x8
#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x200
#define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask__SHIFT 0x9
#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask_MASK 0x400
#define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT 0xa
#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x800
#define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xb
#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK 0xffff0000
#define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask__SHIFT 0x10
#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr_MASK 0x1
#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr__SHIFT 0x0
#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource_MASK 0xe
#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource__SHIFT 0x1
#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver_MASK 0x10
#define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver__SHIFT 0x4
#define ACP_ERROR_SOURCE_STS__BRBAddrErr_MASK 0x20
#define ACP_ERROR_SOURCE_STS__BRBAddrErr__SHIFT 0x5
#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource_MASK 0x3c0
#define ACP_ERROR_SOURCE_STS__BRBAddrErrSource__SHIFT 0x6
#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver_MASK 0x400
#define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT 0xa
#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr_MASK 0x800
#define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr__SHIFT 0xb
#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr_MASK 0x1000
#define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr__SHIFT 0xc
#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr_MASK 0x2000
#define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr__SHIFT 0xd
#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr_MASK 0x4000
#define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr__SHIFT 0xe
#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr_MASK 0x8000
#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr__SHIFT 0xf
#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource_MASK 0x70000
#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource__SHIFT 0x10
#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver_MASK 0x80000
#define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver__SHIFT 0x13
#define ACP_ERROR_SOURCE_STS__DAGBErr_MASK 0x100000
#define ACP_ERROR_SOURCE_STS__DAGBErr__SHIFT 0x14
#define ACP_ERROR_SOURCE_STS__DAGBErrSource_MASK 0x1e00000
#define ACP_ERROR_SOURCE_STS__DAGBErrSource__SHIFT 0x15
#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver_MASK 0x2000000
#define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver__SHIFT 0x19
#define ACP_ERROR_SOURCE_STS__DMATermOnErr_MASK 0x4000000
#define ACP_ERROR_SOURCE_STS__DMATermOnErr__SHIFT 0x1a
#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr_MASK 0x10000000
#define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr__SHIFT 0x1c
#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0_MASK 0x1
#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0__SHIFT 0x0
#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1_MASK 0x2
#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1__SHIFT 0x1
#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2_MASK 0x4
#define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2__SHIFT 0x2
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--> --------------------