/* * Copyright (c) 2002, 2022, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2012, 2022 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * #ifndef CPU_PPC_ASSEMBLER_PPC_HPP#define CPU_PPC_ASSEMBLER_PPC_HPP#include "asm/assembler.hpp" #include "asm/register.hpp" // Address is an abstraction used to represent a memory location // as used in assembler instructions. // PPC instructions grok either baseReg + indexReg or baseReg + disp. class Address {private :Register _base; // Base register. Register _index; // Index register. // Displacement. public :Register b, Register i, address d = 0)"can't have both" );Register b, address d = 0)Register b, ByteSize d)Register b, intptr_t d)Register b, RegisterOrConstant roc)if (roc.is_constant()) _disp = roc.as_constant(); else _index = roc.as_register();// accessors Register base() const { return _base; }Register index() const { return _index; }int disp() const { return (int )_disp; }bool is_const() const { return _base == noreg && _index == noreg; }class AddressLiteral {private :switch (rtype) {case relocInfo::external_word_type:return external_word_Relocation::spec(addr);case relocInfo::internal_word_type:return internal_word_Relocation::spec(addr);case relocInfo::opt_virtual_call_type:return opt_virtual_call_Relocation::spec();case relocInfo::static_call_type:return static_call_Relocation::spec();case relocInfo::runtime_call_type:return runtime_call_Relocation::spec();case relocInfo::none:return RelocationHolder();default :return RelocationHolder();protected :// creation public :const & rspec)const { return (intptr_t) _address; }const RelocationHolder& rspec() const { return _rspec; }// Argument is an abstraction used to represent an outgoing // actual argument or an incoming formal parameter, whether // it resides in memory or in a register, in a manner consistent // with the PPC Application Binary Interface, or ABI. This is // often referred to as the native or C calling convention. class Argument {private :int _number; // The number of the argument. public :enum {// Only 8 registers may contain integer parameters. // Can have up to 8 floating registers. // PPC C calling conventions. // The first eight arguments are passed in int regs if they are int. // The first thirteen float arguments are passed in float regs. // Only the first 8 parameters are not placed on the stack. Aix disassembly // shows that xlC places all float args after argument 8 on the stack AND // in a register. This is not documented, but we follow this convention, too. // duplicates num_java_iarg_registers // num_java_farg_registers // creation int number) : _number(number) {}int number() const { return _number; }// Locating register-based arguments: bool is_register() const { return _number < n_register_parameters; }Register as_register() const {"must be a register argument" );return as_Register(number() + R3_ARG1->encoding());#if !defined (ABI_ELFv2)// A ppc64 function descriptor. struct FunctionDescriptor {private :public :inline address entry() const { return _entry; }inline address toc() const { return _toc; }inline address env() const { return _env; }inline void set_entry(address entry) { _entry = entry; }inline void set_toc( address toc) { _toc = toc; }inline void set_env( address env) { _env = env; }inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); }inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); }inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); }// Friend functions can be called without loading toc and env. enum {inline bool is_friend_function() const {return (toc() == (address) friend_toc) && (env() == (address) friend_env);// Constructor for stack-allocated instances. #endif // The PPC Assembler: Pure assembler doing NO optimizations on the // instruction level; i.e., what you write is what you get. The // Assembler is generating code into a CodeBuffer. class Assembler : public AbstractAssembler {protected :// Displacement routines static int patched_branch(int dest_pos, int inst, int inst_pos);static int branch_destination(int inst, int pos);friend class AbstractAssembler;// Code patchers need various routines like inv_wdisp() friend class NativeInstruction;friend class NativeGeneralJump;friend class Relocation;public :enum shifts {// SPR_5_9 field in bits 11 -- 15 // SPR_0_4 field in bits 16 -- 20 // RS field in bits 21 -- 25 // opcode in bits 26 -- 31 // Shift counts in prefix word // Prefix type in bits 24 -- 25 // ST1 field in bits 23 -- 23 // R-bit in bits 20 -- 20 // ST4 field in bits 23 -- 20 enum opcdxos_masks {// trap instructions // DS-FORM enum opcdxos {// Special purpose registers // Attention: Higher and lower half are inserted in reversed order. // condition register logic instructions // CTR-related opcodes // X-FORM // 32 bit opcode encodings // DS-FORM // X-FORM // X-FORM // X-FORM // 64 bit opcode encodings // DS-FORM // DS-FORM // X-FORM // X-FORM // DS-FORM // DS-FORM // X-FORM // X-FORM // X-FORM // MD-FORM // MD-FORM // MD-FORM // MD-FORM // XS-FORM // X-FORM // X-FORM // X-FORM // XO-FORM // XO-FORM // XO-FORM // XO-FORM // XO-FORM // X-FORM // X-FORM // X-FORM // X-FORM // Byte reverse opcodes (introduced with Power10) // X-FORM // X-FORM // X-FORM // opcodes only used for floating arithmetic // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx" // on Power7. Do not use. // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1), // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1), // PPC64-internal FPU conversion opcodes // Fused multiply-accumulate instructions. // A-FORM // A-FORM // Vector instruction support for >= Power6 // Vector Storage Access // Vector-Scalar (VSX) instruction support. // XX2-FORM // XX2-FORM // Deliver A Random Number (introduced with POWER9) // Vector Permute and Formatting // Vector Integer // Vector Floating-Point // not implemented yet // Vector Status and Control // AES (introduced with Power 8) // SHA (introduced with Power 8) // Vector Binary Polynomial Multiplication (introduced with Power 8) // Vector Permute and Xor (introduced with Power 8) // Transactional Memory instructions (introduced with Power 8) // Icache and dcache related instructions // Instruction synchronization // Memory barriers // Wait instructions for polling. // Trap instructions // Atomics. enum opcdeos_mask {// Mask for prefix primary opcode field // Mask for prefix opcode and type fields // Masks for type 00/10 and type 01/11, including opcode, type, and st fieds // Masks for each instructions enum opcdeos {// Prefixed addi/li // xxpermx // Trap instructions TO bits enum trap_to_bits {// single bits // 0, left end // 4, right end // compound ones // Branch hints BH field enum branch_hint_bh {// bclr cases: // bcctr cases: // Branch prediction hints AT field enum branch_hint_at {// at=00 // at=10 // at=11 // Branch prediction hints enum branch_hint_concept {// Use the same encoding as branch_hint_at to simply code. // Used in BO field of branch instruction. enum branch_condition {// bo=001at // bo=011at // bo=10100 // Branch condition with combined prediction hints. enum branch_condition_with_hint {// Elemental Memory Barriers (>=Power 8) enum Elemental_Membar_mask_bits {// Branch prediction hints. inline static int add_bhint_to_boint(const int bhint, const int boint) {switch (boint) {case bcondCRbiIs0:case bcondCRbiIs1:// branch_hint and branch_hint_at have same encodings int )bhintNoHint == (int )bhintatNoHintint )bhintIsNotTaken == (int )bhintatIsNotTakenint )bhintIsTaken == (int )bhintatIsTaken,"wrong encodings" );"wrong encodings" );return (boint & ~0x03) | bhint;case bcondAlways:// no branch_hint return boint;default :return 0;// Extract bcond from boint. inline static int inv_boint_bcond(const int boint) {int r_bcond = boint & ~0x03;"bad branch condition" );return r_bcond;// Extract bhint from boint. inline static int inv_boint_bhint(const int boint) {int r_bhint = boint & 0x03;"bad branch hint" );return r_bhint;// Calculate opposite of given bcond. inline static int opposite_bcond(const int bcond) {switch (bcond) {case bcondCRbiIs0:return bcondCRbiIs1;case bcondCRbiIs1:return bcondCRbiIs0;default :return 0;// Calculate opposite of given bhint. inline static int opposite_bhint(const int bhint) {switch (bhint) {case bhintatNoHint:return bhintatNoHint;case bhintatIsNotTaken:return bhintatIsTaken;case bhintatIsTaken:return bhintatIsNotTaken;default :return 0;// PPC branch instructions enum ppcops {enum Condition {public :// Helper functions for groups of instructions enum Predict { pt = 1, pn = 0 }; // pt = predict taken //---< calculate length of instruction >--- // With PPC64 being a RISC architecture, this always is BytesPerInstWord // instruction must start at passed address static unsigned int instr_len(unsigned char *instr) { return BytesPerInstWord; }//---< longest instructions >--- static unsigned int instr_maxlen() { return BytesPerInstWord; }// Test if x is within signed immediate range for nbits. static bool is_simm(int x, unsigned int nbits) {"out of bounds" );const int min = -(((int )1) << nbits-1);const int maxplus1 = (((int )1) << nbits-1);return min <= x && x < maxplus1;static bool is_simm(jlong x, unsigned int nbits) {"out of bounds" );const jlong min = -(((jlong)1) << nbits-1);const jlong maxplus1 = (((jlong)1) << nbits-1);return min <= x && x < maxplus1;// Test if x is within unsigned immediate range for nbits. static bool is_uimm(int x, unsigned int nbits) {"out of bounds" );const unsigned int maxplus1 = (((unsigned int )1) << nbits);return (unsigned int )x < maxplus1;static bool is_uimm(jlong x, unsigned int nbits) {"out of bounds" );const julong maxplus1 = (((julong)1) << nbits);return (julong)x < maxplus1;protected :// helpers // X is supposed to fit in a field "nbits" wide // and be sign-extended. Check the range. static void assert_signed_range(intptr_t x, int nbits) {"value out of range" );static void assert_signed_word_disp_range(intptr_t x, int nbits) {"not word aligned" );static void assert_unsigned_const(int x, int nbits) {"unsigned constant out of range" );static int fmask(juint hi_bit, juint lo_bit) {"bad bits" );return (1 << ( hi_bit-lo_bit + 1 )) - 1;// inverse of u_field static int inv_u_field(int x, int hi_bit, int lo_bit) {return int (r);// signed version: extract from field and sign-extend static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) {return x;static int u_field(int x, int hi_bit, int lo_bit) {"value out of range" );int r = x << lo_bit;"just checking" );return r;// Same as u_field for signed values static int s_field(int x, int hi_bit, int lo_bit) {int nbits = hi_bit - lo_bit + 1;"value out of range" );int r = x << lo_bit;return r;// inv_op for ppc instructions static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); }// Determine target address from li, bd field of branch instruction. static intptr_t inv_li_field(int x) {return r;static intptr_t inv_bd_field(int x, intptr_t pos) {return r;#define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit))#define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit))// Extract instruction fields from instruction words. public :static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); }static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); }static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); }static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); }static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); }// Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0. // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0. static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; }static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); }static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); }static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); }static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); }static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }// For extended opcodes (prefixed instructions) introduced with Power 10 static long inv_r_eo( int x) { return inv_opp_u_field(x, 11, 11); }static long inv_type( int x) { return inv_opp_u_field(x, 7, 6); }static long inv_st_x0( int x) { return inv_opp_u_field(x, 8, 8); }static long inv_st_x1( int x) { return inv_opp_u_field(x, 11, 8); }// - 8LS:D/MLS:D Formats static long inv_d0_eo( long x) { return inv_opp_u_field(x, 31, 14); }// - 8RR:XX4/8RR:D Formats static long inv_imm0_eo(int x) { return inv_opp_u_field(x, 31, 16); }static long inv_uimm_eo(int x) { return inv_opp_u_field(x, 31, 29); }static long inv_imm_eo( int x) { return inv_opp_u_field(x, 31, 24); }#define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))#define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))// instruction fields static int aa( int x) { return opp_u_field(x, 30, 30); }static int ba( int x) { return opp_u_field(x, 15, 11); }static int bb( int x) { return opp_u_field(x, 20, 16); }static int bc( int x) { return opp_u_field(x, 25, 21); }static int bd( int x) { return opp_s_field(x, 29, 16); }static int bf( ConditionRegister cr) { return bf(cr->encoding()); }static int bf( int x) { return opp_u_field(x, 8, 6); }static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); }static int bfa( int x) { return opp_u_field(x, 13, 11); }static int bh( int x) { return opp_u_field(x, 20, 19); }static int bi( int x) { return opp_u_field(x, 15, 11); }static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; }static int bo( int x) { return opp_u_field(x, 10, 6); }static int bt( int x) { return opp_u_field(x, 10, 6); }static int d1( int x) { return opp_s_field(x, 31, 16); }static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset" ); return opp_s_field(x, 31, 16); }static int eh( int x) { return opp_u_field(x, 31, 31); }static int flm( int x) { return opp_u_field(x, 14, 7); }static int fra( FloatRegister r) { return fra(r->encoding());}static int frb( FloatRegister r) { return frb(r->encoding());}static int frc( FloatRegister r) { return frc(r->encoding());}static int frs( FloatRegister r) { return frs(r->encoding());}static int frt( FloatRegister r) { return frt(r->encoding());}static int fra( int x) { return opp_u_field(x, 15, 11); }static int frb( int x) { return opp_u_field(x, 20, 16); }static int frc( int x) { return opp_u_field(x, 25, 21); }static int frs( int x) { return opp_u_field(x, 10, 6); }static int frt( int x) { return opp_u_field(x, 10, 6); }static int fxm( int x) { return opp_u_field(x, 19, 12); }static int imm8( int x) { return opp_u_field(uimm(x, 8), 20, 13); }static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1" ); return opp_u_field(x, 10, 10); }static int l14( int x) { return opp_u_field(x, 15, 14); }static int l15( int x) { return opp_u_field(x, 15, 15); }static int l910( int x) { return opp_u_field(x, 10, 9); }static int e1215( int x) { return opp_u_field(x, 15, 12); }static int lev( int x) { return opp_u_field(x, 26, 20); }static int li( int x) { return opp_s_field(x, 29, 6); }static int lk( int x) { return opp_u_field(x, 31, 31); }static int mb2125( int x) { return opp_u_field(x, 25, 21); }static int me2630( int x) { return opp_u_field(x, 30, 26); }static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); }static int me2126( int x) { return mb2126(x); }static int nb( int x) { return opp_u_field(x, 20, 16); }//static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes static int oe( int x) { return opp_u_field(x, 21, 21); }static int ra( Register r) { return ra(r->encoding()); }static int ra( int x) { return opp_u_field(x, 15, 11); }static int rb( Register r) { return rb(r->encoding()); }static int rb( int x) { return opp_u_field(x, 20, 16); }static int rc( int x) { return opp_u_field(x, 31, 31); }static int rs( Register r) { return rs(r->encoding()); }static int rs( int x) { return opp_u_field(x, 10, 6); }// we don't want to use R0 in memory accesses, because it has value `0' then static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access" ); return ra(r); }static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access" ); return ra(x); }// register r is target static int rt( Register r) { return rs(r); }static int rt( int x) { return rs(x); }static int rta( Register r) { return ra(r); }static int rta0mem( Register r) { rta(r); return ra0mem(r); }static int sh1620( int x) { return opp_u_field(x, 20, 16); }static int sh30( int x) { return opp_u_field(x, 30, 30); }static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); }static int si( int x) { return opp_s_field(x, 31, 16); }static int spr( int x) { return opp_u_field(x, 20, 11); }static int sr( int x) { return opp_u_field(x, 15, 12); }static int tbr( int x) { return opp_u_field(x, 20, 11); }static int th( int x) { return opp_u_field(x, 10, 7); }static int thct( int x) { assert((x&8) == 0, "must be valid cache specification" ); return th(x); }static int thds( int x) { assert((x&8) == 8, "must be valid stream specification" ); return th(x); }static int to( int x) { return opp_u_field(x, 10, 6); }static int u( int x) { return opp_u_field(x, 19, 16); }static int ui( int x) { return opp_u_field(x, 31, 16); }// Support vector instructions for >= Power6. static int vra( int x) { return opp_u_field(x, 15, 11); }static int vrb( int x) { return opp_u_field(x, 20, 16); }static int vrc( int x) { return opp_u_field(x, 25, 21); }static int vrs( int x) { return opp_u_field(x, 10, 6); }static int vrt( int x) { return opp_u_field(x, 10, 6); }static int vra( VectorRegister r) { return vra(r->encoding());}static int vrb( VectorRegister r) { return vrb(r->encoding());}static int vrc( VectorRegister r) { return vrc(r->encoding());}static int vrs( VectorRegister r) { return vrs(r->encoding());}static int vrt( VectorRegister r) { return vrt(r->encoding());}// Only used on SHA sigma instructions (VX-form) static int vst( int x) { return opp_u_field(x, 16, 16); }static int vsix( int x) { return opp_u_field(x, 20, 17); }// Support Vector-Scalar (VSX) instructions. static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); }static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); }static int vsrc( int x) { return opp_u_field(x & 0x1F, 25, 21) | opp_u_field((x & 0x20) >> 5, 28, 28); }static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); }static int vsrt( int x) { return vsrs(x); }static int vsdm( int x) { return opp_u_field(x, 23, 22); }static int vsrs_dq( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 28, 28); }static int vsrt_dq( int x) { return vsrs_dq(x); }static int vsra( VectorSRegister r) { return vsra(r->encoding());}static int vsrb( VectorSRegister r) { return vsrb(r->encoding());}static int vsrc( VectorSRegister r) { return vsrc(r->encoding());}static int vsrs( VectorSRegister r) { return vsrs(r->encoding());}static int vsrt( VectorSRegister r) { return vsrt(r->encoding());}static int vsrs_dq(VectorSRegister r) { return vsrs_dq(r->encoding());}static int vsrt_dq(VectorSRegister r) { return vsrt_dq(r->encoding());}static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions static int xxsplt_uim(int x) { return opp_u_field(x, 15, 14); } // for xxsplt* instructions // For extended opcodes (prefixed instructions) introduced with Power 10 static long r_eo( int x) { return opp_u_field(x, 11, 11); }static long type( int x) { return opp_u_field(x, 7, 6); }static long st_x0( int x) { return opp_u_field(x, 8, 8); }static long st_x1( int x) { return opp_u_field(x, 11, 8); }// - 8LS:D/MLS:D Formats static long d0_eo( long x) { return opp_u_field((x >> 16) & 0x3FFFF, 31, 14); }static long d1_eo( long x) { return opp_u_field(x & 0xFFFF, 31, 16); }static long s0_eo( long x) { return d0_eo(x); }static long s1_eo( long x) { return d1_eo(x); }// - 8RR:XX4/8RR:D Formats static long imm0_eo( int x) { return opp_u_field(x >> 16, 31, 16); }static long imm1_eo( int x) { return opp_u_field(x & 0xFFFF, 31, 16); }static long uimm_eo( int x) { return opp_u_field(x, 31, 29); }static long imm_eo( int x) { return opp_u_field(x, 31, 24); }//static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes protected :// Compute relative address for branch. static intptr_t disp(intptr_t x, intptr_t off) {int xx = x - off;return xx;public :// signed immediate, in low bits, nbits long static int simm(int x, int nbits) {return x & ((1 << nbits) - 1);// unsigned immediate, in low bits, nbits long static int uimm(int x, int nbits) {return x & ((1 << nbits) - 1);static void set_imm(int * instr, short s) {// imm is always in the lower 16 bits of the instruction, // so this is endian-neutral. Same for the get_imm below. int )((w & ~0x0000FFFF) | (s & 0x0000FFFF));static int get_imm(address a, int instruction_number) {return (short )((int *)a)[instruction_number];static inline int hi16_signed( int x) { return (int )(int16_t)(x >> 16); }static inline int lo16_unsigned(int x) { return x & 0xffff; }protected :// Extract the top 32 bits in a 64 bit word. static int32_t hi32(int64_t x) {return r;public :static inline unsigned int align_addr(unsigned int addr, unsigned int a) {return ((addr + (a - 1)) & ~(a - 1));static inline bool is_aligned(unsigned int addr, unsigned int a) {return (0 == addr % a);void flush() {inline void emit_int32(int ); // shadows AbstractAssembler::emit_int32 inline void emit_data(int );inline void emit_data(int , RelocationHolder const &);inline void emit_data(int , relocInfo::relocType rtype);// Emit an address. inline address emit_addr(const address addr = NULL);#if !defined (ABI_ELFv2)// Emit a function descriptor with the specified entry point, TOC, // and ENV. If the entry point is NULL, the descriptor will point // just past the descriptor. // Use values from friend functions as defaults. inline address emit_fd(address entry = NULL,#endif ///////////////////////////////////////////////////////////////////////////////////// // PPC instructions ///////////////////////////////////////////////////////////////////////////////////// // Memory instructions use r0 as hard coded 0, e.g. to simulate loading // immediates. The normal instruction encoders enforce that r0 is not // passed to them. Use either extended mnemonics encoders or the special ra0 // versions. // Issue an illegal instruction. inline void illtrap();static inline bool is_illtrap(address instr_addr);// PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions inline void addi( Register d, Register a, int si16);inline void addis(Register d, Register a, int si16);// Prefixed add immediate, introduced by POWER10 inline void paddi(Register d, Register a, long si34, bool r);inline void pli( Register d, long si34);private :inline void addi_r0ok( Register d, Register a, int si16);inline void addis_r0ok(Register d, Register a, int si16);inline void paddi_r0ok(Register d, Register a, long si34, bool r);public :inline void addic_( Register d, Register a, int si16);inline void subfic( Register d, Register a, int si16);inline void add( Register d, Register a, Register b);inline void add_( Register d, Register a, Register b);inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec. inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability. inline void subf_( Register d, Register a, Register b);inline void addc( Register d, Register a, Register b);inline void addc_( Register d, Register a, Register b);inline void subfc( Register d, Register a, Register b);inline void subfc_( Register d, Register a, Register b);inline void adde( Register d, Register a, Register b);inline void adde_( Register d, Register a, Register b);inline void subfe( Register d, Register a, Register b);inline void subfe_( Register d, Register a, Register b);inline void addme( Register d, Register a);inline void addme_( Register d, Register a);inline void subfme( Register d, Register a);inline void subfme_(Register d, Register a);inline void addze( Register d, Register a);inline void addze_( Register d, Register a);inline void subfze( Register d, Register a);inline void subfze_(Register d, Register a);inline void neg( Register d, Register a);inline void neg_( Register d, Register a);inline void mulli( Register d, Register a, int si16);inline void mulld( Register d, Register a, Register b);inline void mulld_( Register d, Register a, Register b);inline void mullw( Register d, Register a, Register b);inline void mullw_( Register d, Register a, Register b);inline void mulhw( Register d, Register a, Register b);inline void mulhw_( Register d, Register a, Register b);inline void mulhwu( Register d, Register a, Register b);inline void mulhwu_(Register d, Register a, Register b);inline void mulhd( Register d, Register a, Register b);inline void mulhd_( Register d, Register a, Register b);inline void mulhdu( Register d, Register a, Register b);inline void mulhdu_(Register d, Register a, Register b);inline void divd( Register d, Register a, Register b);inline void divd_( Register d, Register a, Register b);inline void divw( Register d, Register a, Register b);inline void divw_( Register d, Register a, Register b);inline void divdu( Register d, Register a, Register b);inline void divdu_( Register d, Register a, Register b);inline void divwu( Register d, Register a, Register b);inline void divwu_( Register d, Register a, Register b);// Fixed-Point Arithmetic Instructions with Overflow detection inline void addo( Register d, Register a, Register b);inline void addo_( Register d, Register a, Register b);inline void subfo( Register d, Register a, Register b);inline void subfo_( Register d, Register a, Register b);inline void addco( Register d, Register a, Register b);inline void addco_( Register d, Register a, Register b);inline void subfco( Register d, Register a, Register b);inline void subfco_( Register d, Register a, Register b);inline void addeo( Register d, Register a, Register b);inline void addeo_( Register d, Register a, Register b);inline void subfeo( Register d, Register a, Register b);inline void subfeo_( Register d, Register a, Register b);quality 94%
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