/* * Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2016, 2022 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. *
*/
// AND immediate and set condition code, works for 64 bit immediates/operation as well. void and_imm(Register r, long mask, Register tmp = Z_R0, bool wide = false);
// 1's complement, 32bit or 64bit. Optimized to exploit distinct operands facility. // Note: The condition code is neither preserved nor correctly set by this code!!! // Note: (wide == false) does not protect the high order half of the target register // from alternation. It only serves as optimization hint for 32-bit results. void not_(Register r1, Register r2 = noreg, bool wide = false); // r1 = ~r2
// Expanded support of all "rotate_then_<logicalOP>" instructions. // // Generalize and centralize rotate_then_<logicalOP> emitter. // Functional description. For details, see Principles of Operation, Chapter 7, "Rotate Then Insert..." // - Bits in a register are numbered left (most significant) to right (least significant), i.e. [0..63]. // - Bytes in a register are numbered left (most significant) to right (least significant), i.e. [0..7]. // - Register src is rotated to the left by (nRotate&0x3f) positions. // - Negative values for nRotate result in a rotation to the right by abs(nRotate) positions. // - The bits in positions [lBitPos..rBitPos] of the _ROTATED_ src operand take part in the // logical operation performed on the contents (in those positions) of the dst operand. // - The logical operation that is performed on the dst operand is one of // o insert the selected bits (replacing the original contents of those bit positions) // o and the selected bits with the corresponding bits of the dst operand // o or the selected bits with the corresponding bits of the dst operand // o xor the selected bits with the corresponding bits of the dst operand // - For clear_dst == true, the destination register is cleared before the bits are inserted. // For clear_dst == false, only the bit positions that get data inserted from src // are changed. All other bit positions remain unchanged. // - For test_only == true, the result of the logicalOP is only used to set the condition code, dst remains unchanged. // For test_only == false, the result of the logicalOP replaces the selected bits of dst. // - src32bit and dst32bit indicate the respective register is used as 32bit value only. // Knowledge can simplify code generation. // // Here is an important performance note, valid for all <logicalOP>s except "insert": // Due to the too complex nature of the operation, it cannot be done in a single cycle. // Timing constraints require the instructions to be cracked into two micro-ops, taking // one or two cycles each to execute. In some cases, an additional pipeline bubble might get added. // Macroscopically, that makes up for a three- or four-cycle instruction where you would // expect just a single cycle. // It is thus not beneficial from a performance point of view to exploit those instructions. // Other reasons (code compactness, register pressure, ...) might outweigh this penalty. // unsignedlong create_mask(int lBitPos, int rBitPos); void rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos, int nRotate, bool src32bit, bool dst32bit, bool oneBits); void rotate_then_insert(Register dst, Register src, int lBitPos, int rBitPos, int nRotate, bool clear_dst); void rotate_then_and(Register dst, Register src, int lBitPos, int rBitPos, int nRotate, bool test_only); void rotate_then_or(Register dst, Register src, int lBitPos, int rBitPos, int nRotate, bool test_onlyt); void rotate_then_xor(Register dst, Register src, int lBitPos, int rBitPos, int nRotate, bool test_only);
void add64(Register r1, RegisterOrConstant inc);
// Helper function to multiply the 64bit contents of a register by a 16bit constant. // The optimization tries to avoid the mghi instruction, since it uses the FPU for // calculation and is thus rather slow. // // There is no handling for special cases, e.g. cval==0 or cval==1. // // Returns len of generated code block. unsignedint mul_reg64_const16(Register rval, Register work, int cval);
// Generic operation r1 := r2 + imm. void add2reg(Register r1, int64_t imm, Register r2 = noreg); // Generic operation r := b + x + d. void add2reg_with_index(Register r, int64_t d, Register x, Register b = noreg);
// Load a value from memory and test (set CC). void load_and_test_byte (Register dst, const Address &a); void load_and_test_short (Register dst, const Address &a); void load_and_test_int (Register dst, const Address &a); void load_and_test_int2long(Register dst, const Address &a); void load_and_test_long (Register dst, const Address &a);
// Test a bit in memory. Result is reflected in CC. void testbit(const Address &a, unsignedint bit); // Test a bit in a register. Result is reflected in CC. void testbit(Register r, unsignedint bitPos);
// Clear a register, i.e. load const zero into reg. Return len (in bytes) of // generated instruction(s). // whole_reg: Clear 64 bits if true, 32 bits otherwise. // set_cc: Use instruction that sets the condition code, if true. int clear_reg(Register r, bool whole_reg = true, bool set_cc = true);
#ifdef ASSERT int preset_reg(Register r, unsignedlong pattern, int pattern_len); #endif
// Clear (store zeros) a small piece of memory. // CAUTION: Do not use this for atomic memory clearing. Use store_const() instead. // addr: Address descriptor of memory to clear. // Index register will not be used! // size: Number of bytes to clear. void clear_mem(const Address& addr, unsigned size);
// Move immediate values to memory. Currently supports 32 and 64 bit stores, // but may be extended to 16 bit store operation, if needed. // For details, see implementation in *.cpp file. int store_const(const Address &dest, long imm, unsignedint lm, unsignedint lc, Register scratch = Z_R0); inlineint store_const(const Address &dest, long imm, Register scratch = Z_R0, bool is_long = true);
// Move/initialize arbitrarily large memory area. No check for destructive overlap. // Being interruptible, these instructions need a retry-loop. void move_long_ext(Register dst, Register src, unsignedint pad);
// Load a 32bit constant into a 64bit register. void load_const_32to64(Register t, int64_t x, bool sign_extend=true); // Load a 64 bit constant. void load_const(Register t, long a); inlinevoid load_const(Register t, void* a); inlinevoid load_const(Register t, Label& L); inlinevoid load_const(Register t, const AddressLiteral& a); // Get the 64 bit constant from a `load_const' sequence. staticlong get_const(address load_const); // Patch the 64 bit constant of a `load_const' sequence. This is a low level // procedure. It neither flushes the instruction cache nor is it atomic. staticvoid patch_const(address load_const, long x); staticint load_const_size() { return 12; }
// Turn a char into boolean. NOTE: destroys r. void c2bool(Register r, Register t = Z_R0);
// Optimized version of load_const for constants that do not need to be // loaded by a sequence of instructions of fixed length and that do not // need to be patched. int load_const_optimized_rtn_len(Register t, long x, bool emit); inlinevoid load_const_optimized(Register t, long x); inlinevoid load_const_optimized(Register t, void* a); inlinevoid load_const_optimized(Register t, Label& L); inlinevoid load_const_optimized(Register t, const AddressLiteral& a);
public:
//---------------------------------------------------------- // oops in code ------------- // including compressed oops support ------------- //----------------------------------------------------------
// Metadata in code that we have to keep track of.
AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
AddressLiteral constant_metadata_address(Metadata* obj); // find_index
staticvoid patch_target_addr_pcrel(address pc, address con); staticvoid patch_addr_pcrel(address pc, address con) {
patch_target_addr_pcrel(pc, con); // Just delegate. This is only for nativeInst_s390.cpp.
}
//--------------------------------------------------------- // Some macros for more comfortable assembler programming. //---------------------------------------------------------
// NOTE: pass NearLabel T to signal that the branch target T will be bound to a near address.
// // Support for frame handling // // Specify the register that should be stored as the return pc in the // current frame (default is R14). inlinevoid save_return_pc(Register pc = Z_R14); inlinevoid restore_return_pc();
// Get current PC.
address get_PC(Register result);
// Get current PC + offset. Offset given in bytes, must be even!
address get_PC(Register result, int64_t offset);
// Get size of instruction at pc (which must point to valid code). void instr_size(Register size, Register pc);
// Accessing, and in particular modifying, a stack location is only safe if // the stack pointer (Z_SP) is set such that the accessed stack location is // in the reserved range. // // From a performance point of view, it is desirable not to change the SP // first and then immediately use it to access the freshly reserved space. // That opens a small gap, though. If, just after storing some value (the // frame pointer) into the to-be-reserved space, an interrupt is caught, // the handler might use the space beyond Z_SP for it's own purpose. // If that happens, the stored value might get altered.
// Resize current frame either relatively wrt to current SP or absolute. void resize_frame_sub(Register offset, Register fp, bool load_fp=true); void resize_frame_abs_with_offset(Register newSP, Register fp, int offset, bool load_fp); void resize_frame_absolute(Register addr, Register fp, bool load_fp); void resize_frame(RegisterOrConstant offset, Register fp, bool load_fp=true);
// Push a frame of size bytes, if copy_sp is false, old_sp must already // contain a copy of Z_SP. void push_frame(Register bytes, Register old_sp, bool copy_sp = true, bool bytes_with_inverted_sign = false);
// Push a frame of size `bytes'. no abi space provided. // Don't rely on register locking, instead pass a scratch register // (Z_R0 by default). // CAUTION! passing registers >= Z_R2 may produce bad results on // old CPUs! unsignedint push_frame(unsignedint bytes, Register scratch = Z_R0);
// Push a frame of size `bytes' with abi160 on top. unsignedint push_frame_abi160(unsignedint bytes);
// Pop current C frame. void pop_frame(); // Pop current C frame and restore return PC register (Z_R14). void pop_frame_restore_retPC(int frame_size_in_bytes);
// // Calls //
private:
address _last_calls_return_pc;
public: // Support for VM calls. This is the base routine called by the // different versions of call_VM_leaf. The interpreter may customize // this version by overriding it for its purposes (e.g., to // save/restore additional registers when doing a VM call). void call_VM_leaf_base(address entry_point); void call_VM_leaf_base(address entry_point, bool allow_relocation);
// It is imperative that all calls into the VM are handled via the // call_VM macros. They make sure that the stack linkage is setup // correctly. Call_VM's correspond to ENTRY/ENTRY_X entry points // while call_VM_leaf's correspond to LEAF entry points. // // This is the base routine called by the different versions of // call_VM. The interpreter may customize this version by overriding // it for its purposes (e.g., to save/restore additional registers // when doing a VM call).
// If no last_java_sp is specified (noreg) then SP will be used instead.
virtualvoid call_VM_base( Register oop_result, // Where an oop-result ends up if any; use noreg otherwise. Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise.
address entry_point, // The entry point. bool check_exception); // Flag which indicates if exception should be checked. virtualvoid call_VM_base( Register oop_result, // Where an oop-result ends up if any; use noreg otherwise. Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise.
address entry_point, // The entry point. bool allow_relocation, // Flag to request generation of relocatable code. bool check_exception); // Flag which indicates if exception should be checked.
// Call into the VM. // Passes the thread pointer (in Z_ARG1) as a prepended argument. // Makes sure oop return values are visible to the GC. void call_VM(Register oop_result, address entry_point, bool check_exceptions = true); void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
// Call a C function via its function entry. Updates and returns _last_calls_return_pc. inline address call(Register function_entry); inline address call_c(Register function_entry);
address call_c(address function_entry); // Variant for really static (non-relocatable) calls which are never patched.
address call_c_static(address function_entry); // TOC or pc-relative call + emits a runtime_call relocation.
address call_c_opt(address function_entry);
// Get the pc where the last call will return to. Returns _last_calls_return_pc. inline address last_calls_return_pc();
private: staticbool is_call_far_patchable_variant0_at(address instruction_addr); // Dynamic TOC: load target addr from CP and call. staticbool is_call_far_patchable_variant2_at(address instruction_addr); // PC-relative call, prefixed with NOPs.
public: bool call_far_patchable(address target, int64_t toc_offset); staticbool is_call_far_patchable_at(address inst_start); // All supported forms of patchable calls. staticbool is_call_far_patchable_pcrelative_at(address inst_start); // Pc-relative call with leading nops. staticbool is_call_far_pcrelative(address instruction_addr); // Pure far pc-relative call, with one leading size adjustment nop. staticvoid set_dest_of_call_far_patchable_at(address inst_start, address target, int64_t toc_offset); static address get_dest_of_call_far_patchable_at(address inst_start, address toc_start);
void align_call_far_patchable(address pc);
// PCrelative TOC access.
// This value is independent of code position - constant for the lifetime of the VM. staticint call_far_patchable_size() { return load_const_from_toc_size() + call_byregister_size();
}
staticint jump_byregister_size() { return 2; } staticint jump_pcrelative_size() { return 4; } staticint jump_far_pcrelative_size() { return 6; } staticint call_byregister_size() { return 2; } staticint call_pcrelative_size() { return 4; } staticint call_far_pcrelative_size() { return 2 + 6; } // Prepend each BRASL with a nop. staticint call_far_pcrelative_size_raw() { return 6; } // Prepend each BRASL with a nop.
// // Java utilities //
// These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. // The implementation is only non-empty for the InterpreterMacroAssembler, // as only the interpreter handles PopFrame and ForceEarlyReturn requests. virtualvoid check_and_handle_popframe(Register java_thread); virtualvoid check_and_handle_earlyret(Register java_thread);
// Read from the polling page. void load_from_polling_page(Register polling_page_address, int64_t offset = 0);
// Check if given instruction is a read from the polling page // as emitted by load_from_polling_page. staticbool is_load_from_polling_page(address instr_loc); // Extract poll address from instruction and ucontext. static address get_poll_address(address instr_loc, void* ucontext); // Extract poll register from instruction. static uint get_poll_register(address instr_loc);
// Check if safepoint requested and if so branch void safepoint_poll(Label& slow_path, Register temp_reg);
// Check for reserved stack access in method being exited. If the reserved // stack area was accessed, protect it again and throw StackOverflowError. // Uses Z_R1. void reserved_stack_check(Register return_pc);
// Atomics // -- none?
void tlab_allocate(Register obj, // Result: pointer to object after successful allocation Register var_size_in_bytes, // Object size in bytes if unknown at compile time; invalid otherwise. int con_size_in_bytes, // Object size in bytes if known at compile time. Register t1, // temp register
Label& slow_case); // Continuation point if fast allocation fails.
// Factor out code to call ic_miss_handler. unsignedint call_ic_miss_handler(Label& ICM, int trapMarker, int requiredSize, Register scratch); void nmethod_UEP(Label& ic_miss);
// Emitters for "partial subtype" checks.
// Test sub_klass against super_klass, with fast and slow paths.
// The fast path produces a tri-state answer: yes / no / maybe-slow. // One of the three labels can be NULL, meaning take the fall-through. // If super_check_offset is -1, the value is loaded up from super_klass. // No registers are killed, except temp_reg and temp2_reg. // If super_check_offset is not -1, temp1_reg is not used and can be noreg. void check_klass_subtype_fast_path(Register sub_klass, Register super_klass, Register temp1_reg,
Label* L_success,
Label* L_failure,
Label* L_slow_path,
RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
// The rest of the type check; must be wired to a corresponding fast path. // It does not repeat the fast path logic, so don't use it standalone. // The temp_reg can be noreg, if no temps are available. // It can also be sub_klass or super_klass, meaning it's OK to kill that one. // Updates the sub's secondary super cache as necessary. void check_klass_subtype_slow_path(Register Rsubklass, Register Rsuperklas, Register Rarray_ptr, // tmp Register Rlength, // tmp
Label* L_success,
Label* L_failure);
// Simplified, combined version, good for typical uses. // Falls through on failure. void check_klass_subtype(Register sub_klass, Register super_klass, Register temp1_reg, Register temp2_reg,
Label& L_success);
// Increment a counter at counter_address when the eq condition code is set. // Kills registers tmp1_reg and tmp2_reg and preserves the condition code. void increment_counter_eq(address counter_address, Register tmp1_reg, Register tmp2_reg);
// Read vm result from thread. void get_vm_result (Register oop_result); void get_vm_result_2(Register result);
// Vm result is currently getting hijacked to for oop preservation. void set_vm_result(Register oop_result);
// Support for NULL-checks // // Generates code that causes a NULL OS exception if the content of reg is NULL. // If the accessed location is M[reg + offset] and the offset is known, provide the // offset. No explicit code generation is needed if the offset is within a certain // range (0 <= offset <= page_size). // // %%%%%% Currently not done for z/Architecture
// Klass oop manipulations if compressed. void encode_klass_not_null(Register dst, Register src = noreg); void decode_klass_not_null(Register dst, Register src); void decode_klass_not_null(Register dst); void load_klass(Register klass, Address mem); void load_klass(Register klass, Register src_oop); void store_klass(Register klass, Register dst_oop, Register ck = noreg); // Klass will get compressed if ck not provided. void store_klass_gap(Register s, Register dst_oop);
// This function calculates the size of the code generated by // decode_klass_not_null(register dst) // when (Universe::heap() != NULL). Hence, if the instructions // it generates change, then this method needs to be updated. staticint instr_size_for_decode_klass_not_null();
// Emit an oop const to the constant pool and set a relocation info // with address current_pc. Return the TOC offset of the constant. int store_const_in_toc(AddressLiteral& val); int store_oop_in_toc(AddressLiteral& oop); // Emit an oop const to the constant pool via store_oop_in_toc, or // emit a scalar const to the constant pool via store_const_in_toc, // and load the constant into register dst. bool load_const_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg); // Get CPU version dependent size of load_const sequence. // The returned value is valid only for code sequences // generated by load_const, not load_const_optimized. staticint load_const_from_toc_size() { return load_long_pcrelative_size();
} bool load_oop_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg); static intptr_t get_const_from_toc(address pc); staticvoid set_const_in_toc(address pc, unsignedlong new_data, CodeBlob *cb);
private: // Generate printout in stop(). staticconstchar* stop_types[]; enum {
stop_stop = 0,
stop_untested = 1,
stop_unimplemented = 2,
stop_shouldnotreachhere = 3,
stop_end = 4
}; // Prints msg and stops execution. void stop(int type, constchar* msg, int id = 0);
address stop_chain(address reentry, int type, constchar* msg, int id, bool allow_relocation); // Non-relocateable code only!! void stop_static(int type, constchar* msg, int id); // Non-relocateable code only!!
public:
// Prints msg and stops.
address stop_chain( address reentry, constchar* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, true); }
address stop_chain_static(address reentry, constchar* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, false); } void stop_static (constchar* msg = "", int id = 0) { stop_static(stop_stop, msg, id); } void stop (constchar* msg = "", int id = 0) { stop(stop_stop, msg, id); } void untested (constchar* msg = "", int id = 0) { stop(stop_untested, msg, id); } void unimplemented(constchar* msg = "", int id = 0) { stop(stop_unimplemented, msg, id); } void should_not_reach_here(constchar* msg = "", int id = -1) { stop(stop_shouldnotreachhere, msg, id); }
// Factor out part of stop into subroutine to save space. void stop_subroutine();
// Prints msg, but don't stop. void warn(constchar* msg);
//----------------------------- //--- basic block tracing code //----------------------------- void trace_basic_block(uint i); void init_basic_block_trace(); // Number of bytes a basic block gets larger due to the tracing code macro (worst case). // Currently, worst case is 48 bytes. 64 puts us securely on the safe side. staticint basic_blck_trace_blk_size_incr() { return 64; }
// Write pattern 0x0101010101010101 in region [low-before, high+after]. // Low and high may be the same registers. Before and after are // the numbers of 8-byte words. void zap_from_to(Register low, Register high, Register tmp1 = Z_R0, Register tmp2 = Z_R1, int before = 0, int after = 0) PRODUCT_RETURN;
// Emitters for CRC32 calculation. // A note on invertCRC: // Unfortunately, internal representation of crc differs between CRC32 and CRC32C. // CRC32 holds it's current crc value in the externally visible representation. // CRC32C holds it's current crc value in internal format, ready for updating. // Thus, the crc value must be bit-flipped before updating it in the CRC32 case. // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()). // The bool invertCRC parameter indicates whether bit-flipping is required before updates. private: void fold_byte_crc32(Register crc, Register table, Register val, Register tmp); void fold_8bit_crc32(Register crc, Register table, Register tmp); void update_byte_crc32( Register crc, Register val, Register table); void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table, Register data); void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc, Register t0, Register t1, Register t2, Register t3); public: void kernel_crc32_singleByteReg(Register crc, Register val, Register table, bool invertCRC); void kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp, bool invertCRC); void kernel_crc32_1byte(Register crc, Register buf, Register len, Register table, Register t0, Register t1, Register t2, Register t3, bool invertCRC); void kernel_crc32_1word(Register crc, Register buf, Register len, Register table, Register t0, Register t1, Register t2, Register t3, bool invertCRC);
// Emitters for BigInteger.multiplyToLen intrinsic // note: length of result array (zlen) is passed on the stack private: void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2); void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, Register y, Register y_idx, Register z, Register carry, Register product, Register idx, Register kdx); void multiply_add_128_x_128(Register x_xstart, Register y, Register z, Register yz_idx, Register idx, Register carry, Register product, int offset); void multiply_128_x_128_loop(Register x_xstart, Register y, Register z, Register yz_idx, Register idx, Register jdx, Register carry, Register product, Register carry2); public: void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
};
/** * class SkipIfEqual: * * Instantiating this class will result in assembly code being output that will * jump around any code emitted between the creation of the instance and it's * automatic destruction at the end of a scope block, depending on the value of * the flag passed to the constructor, which will be checked at run-time.
*/ class SkipIfEqual { private:
MacroAssembler* _masm;
Label _label;
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