/* * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. *
*/
void MonitorExitStub::emit_code(LIR_Assembler* ce) {
__ bind(_entry); if (_compute_lock) { // lock_reg was destroyed by fast unlocking attempt => recompute it
ce->monitor_address(_monitor_ix, _lock_reg);
}
ce->store_parameter(_lock_reg->as_register(), 0); // note: non-blocking leaf routine => no call info needed
Runtime1::StubID exit_id; if (ce->compilation()->has_fpu_code()) {
exit_id = Runtime1::monitorexit_id;
} else {
exit_id = Runtime1::monitorexit_nofpu_id;
}
__ call(RuntimeAddress(Runtime1::entry_for(exit_id)));
__ jmp(_continuation);
}
// Implementation of patching: // - Copy the code at given offset to an inlined buffer (first the bytes, then the number of bytes) // - Replace original code with a call to the stub // At Runtime: // - call to stub, jump to runtime // - in runtime: preserve all registers (rspecially objects, i.e., source and destination object) // - in runtime: after initializing class, restore original code, reexecute instruction
int PatchingStub::_patch_info_offset = -NativeGeneralJump::instruction_size;
void PatchingStub::align_patch_site(MacroAssembler* masm) { // We're patching a 5-7 byte instruction on intel and we need to // make sure that we don't see a piece of the instruction. It // appears mostly impossible on Intel to simply invalidate other // processors caches and since they may do aggressive prefetch it's // very hard to make a guess about what code might be in the icache. // Force the instruction to be double word aligned so that it // doesn't span a cache line.
masm->align(align_up((int)NativeGeneralJump::instruction_size, wordSize));
}
// static field accesses have special semantics while the class // initializer is being run so we emit a test which can be used to // check that this code is being executed by the initializing // thread.
address being_initialized_entry = __ pc(); if (CommentedAssembly) {
__ block_comment(" patch template");
} if (_id == load_klass_id) { // produce a copy of the load klass instruction for use by the being initialized case #ifdef ASSERT
address start = __ pc(); #endif
Metadata* o = NULL;
__ mov_metadata(_obj, o); #ifdef ASSERT for (int i = 0; i < _bytes_to_copy; i++) {
address ptr = (address)(_pc_start + i); int a_byte = (*ptr) & 0xFF;
assert(a_byte == *start++, "should be the same code");
} #endif
} elseif (_id == load_mirror_id) { // produce a copy of the load mirror instruction for use by the being // initialized case #ifdef ASSERT
address start = __ pc(); #endif
jobject o = NULL;
__ movoop(_obj, o); #ifdef ASSERT for (int i = 0; i < _bytes_to_copy; i++) {
address ptr = (address)(_pc_start + i); int a_byte = (*ptr) & 0xFF;
assert(a_byte == *start++, "should be the same code");
} #endif
} else { // make a copy the code which is going to be patched. for (int i = 0; i < _bytes_to_copy; i++) {
address ptr = (address)(_pc_start + i); int a_byte = (*ptr) & 0xFF;
__ emit_int8(a_byte);
*ptr = 0x90; // make the site look like a nop
}
}
address end_of_patch = __ pc(); int bytes_to_skip = 0; if (_id == load_mirror_id) { int offset = __ offset(); if (CommentedAssembly) {
__ block_comment(" being_initialized check");
}
assert(_obj != noreg, "must be a valid register"); Register tmp = rax; Register tmp2 = rbx;
__ push(tmp);
__ push(tmp2); // Load without verification to keep code size small. We need it because // begin_initialized_entry_offset has to fit in a byte. Also, we know it's not null.
__ movptr(tmp2, Address(_obj, java_lang_Class::klass_offset()));
__ get_thread(tmp);
__ cmpptr(tmp, Address(tmp2, InstanceKlass::init_thread_offset()));
__ pop(tmp2);
__ pop(tmp);
__ jcc(Assembler::notEqual, call_patch);
// access_field patches may execute the patched code before it's // copied back into place so we need to jump back into the main // code of the nmethod to continue execution.
__ jmp(_patch_site_continuation);
// make sure this extra code gets skipped
bytes_to_skip += __ offset() - offset;
} if (CommentedAssembly) {
__ block_comment("patch data encoded as movl");
} // Now emit the patch record telling the runtime how to find the // pieces of the patch. We only need 3 bytes but for readability of // the disassembly we make the data look like a movl reg, imm32, // which requires 5 bytes int sizeof_patch_record = 5;
bytes_to_skip += sizeof_patch_record;
// emit the offsets needed to find the code to patch int being_initialized_entry_offset = __ pc() - being_initialized_entry + sizeof_patch_record;
void ImplicitNullCheckStub::emit_code(LIR_Assembler* ce) {
address a; if (_info->deoptimize_on_exception()) { // Deoptimize, do not throw the exception, because it is probably wrong to do it here.
a = Runtime1::entry_for(Runtime1::predicate_failed_trap_id);
} else {
a = Runtime1::entry_for(Runtime1::throw_null_pointer_exception_id);
}
void SimpleExceptionStub::emit_code(LIR_Assembler* ce) {
assert(__ rsp_offset() == 0, "frame size should be fixed");
__ bind(_entry); // pass the object on stack because all registers must be preserved if (_obj->is_cpu_register()) {
ce->store_parameter(_obj->as_register(), 0);
}
__ call(RuntimeAddress(Runtime1::entry_for(_stub)));
ce->add_call_info_here(_info);
debug_only(__ should_not_reach_here());
}
void ArrayCopyStub::emit_code(LIR_Assembler* ce) { //---------------slow case: call to native-----------------
__ bind(_entry); // Figure out where the args should go // This should really convert the IntrinsicID to the Method* and signature // but I don't know how to do that. //
VMRegPair args[5];
BasicType signature[5] = { T_OBJECT, T_INT, T_OBJECT, T_INT, T_INT};
SharedRuntime::java_calling_convention(signature, args, 5);
// next registers will get stored on the stack for (int i = 0; i < 5 ; i++ ) {
VMReg r_1 = args[i].first(); if (r_1->is_stack()) { int st_off = r_1->reg2stack() * wordSize;
__ movptr (Address(rsp, st_off), r[i]);
} else {
assert(r[i] == args[i].first()->as_Register(), "Wrong register for arg ");
}
}
ce->align_call(lir_static_call);
ce->emit_static_call_stub(); if (ce->compilation()->bailed_out()) { return; // CodeCache is full
}
AddressLiteral resolve(SharedRuntime::get_resolve_static_call_stub(),
relocInfo::static_call_type);
__ call(resolve);
ce->add_call_info_here(info());
#ifndef PRODUCT if (PrintC1Statistics) {
__ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_slowcase_cnt), rscratch1);
} #endif
__ jmp(_continuation);
}
#undef __
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