/* * Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. *
*/
class RegisterSaver { // Capture info about frame layout #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off enum layout {
fpu_state_off = 0,
fpu_state_end = fpu_state_off+FPUStateSizeInWords,
st0_off, st0H_off,
st1_off, st1H_off,
st2_off, st2H_off,
st3_off, st3H_off,
st4_off, st4H_off,
st5_off, st5H_off,
st6_off, st6H_off,
st7_off, st7H_off,
xmm_off,
DEF_XMM_OFFS(0),
DEF_XMM_OFFS(1),
DEF_XMM_OFFS(2),
DEF_XMM_OFFS(3),
DEF_XMM_OFFS(4),
DEF_XMM_OFFS(5),
DEF_XMM_OFFS(6),
DEF_XMM_OFFS(7),
flags_off = xmm7_off + 16/BytesPerInt + 1, // 16-byte stack alignment fill word
rdi_off,
rsi_off,
ignore_off, // extra copy of rbp,
rsp_off,
rbx_off,
rdx_off,
rcx_off,
rax_off, // The frame sender code expects that rbp will be in the "natural" place and // will override any oopMap setting for it. We must therefore force the layout // so that it agrees with the frame sender code.
rbp_off,
return_off, // slot for return address
reg_save_size }; enum { FPU_regs_live = flags_off - fpu_state_end };
// Offsets into the register save area // Used by deoptimization when it is managing result register // values on its own
staticint raxOffset(void) { return rax_off; } staticint rdxOffset(void) { return rdx_off; } staticint rbxOffset(void) { return rbx_off; } staticint xmm0Offset(void) { return xmm0_off; } // This really returns a slot in the fp save area, which one is not important staticint fpResultOffset(void) { return st0_off; }
// During deoptimization only the result register need to be restored // all the other values have already been extracted.
OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool verify_fpu, bool save_vectors) { int num_xmm_regs = XMMRegister::number_of_registers; int ymm_bytes = num_xmm_regs * 16; int zmm_bytes = num_xmm_regs * 32; #ifdef COMPILER2 int opmask_state_bytes = KRegister::number_of_registers * 8; if (save_vectors) {
assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX");
assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported"); // Save upper half of YMM registers int vect_bytes = ymm_bytes; if (UseAVX > 2) { // Save upper half of ZMM registers as well
vect_bytes += zmm_bytes;
additional_frame_words += opmask_state_bytes / wordSize;
}
additional_frame_words += vect_bytes / wordSize;
} #else
assert(!save_vectors, "vectors are generated only by C2"); #endif int frame_size_in_bytes = (reg_save_size + additional_frame_words) * wordSize; int frame_words = frame_size_in_bytes / wordSize;
*total_frame_words = frame_words;
// save registers, fpu state, and flags // We assume caller has already has return address slot on the stack // We push epb twice in this sequence because we want the real rbp, // to be under the return like a normal enter and we want to use pusha // We push by hand instead of using push.
__ enter();
__ pusha();
__ pushf();
__ subptr(rsp,FPU_regs_live*wordSize); // Push FPU registers space
__ push_FPU_state(); // Save FPU state & init
if (verify_fpu) { // Some stubs may have non standard FPU control word settings so // only check and reset the value when it required to be the // standard value. The safepoint blob in particular can be used // in methods which are using the 24 bit control word for // optimized float math.
#ifdef ASSERT // Make sure the control word has the expected value
Label ok;
__ cmpw(Address(rsp, 0), StubRoutines::x86::fpu_cntrl_wrd_std());
__ jccb(Assembler::equal, ok);
__ stop("corrupted control word detected");
__ bind(ok); #endif
// Reset the control word to guard against exceptions being unmasked // since fstp_d can cause FPU stack underflow exceptions. Write it // into the on stack copy and then reload that to make sure that the // current and future values are correct.
__ movw(Address(rsp, 0), StubRoutines::x86::fpu_cntrl_wrd_std());
}
__ frstor(Address(rsp, 0)); if (!verify_fpu) { // Set the control word so that exceptions are masked for the // following code.
__ fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_std()));
}
int off = st0_off; int delta = st1_off - off;
// Save the FPU registers in de-opt-able form for (int n = 0; n < FloatRegister::number_of_registers; n++) {
__ fstp_d(Address(rsp, off*wordSize));
off += delta;
}
off = xmm0_off;
delta = xmm1_off - off; if(UseSSE == 1) { // Save the XMM state for (int n = 0; n < num_xmm_regs; n++) {
__ movflt(Address(rsp, off*wordSize), as_XMMRegister(n));
off += delta;
}
} elseif(UseSSE >= 2) { // Save whole 128bit (16 bytes) XMM registers for (int n = 0; n < num_xmm_regs; n++) {
__ movdqu(Address(rsp, off*wordSize), as_XMMRegister(n));
off += delta;
}
}
#ifdef COMPILER2 if (save_vectors) {
__ subptr(rsp, ymm_bytes); // Save upper half of YMM registers for (int n = 0; n < num_xmm_regs; n++) {
__ vextractf128_high(Address(rsp, n*16), as_XMMRegister(n));
} if (UseAVX > 2) {
__ subptr(rsp, zmm_bytes); // Save upper half of ZMM registers for (int n = 0; n < num_xmm_regs; n++) {
__ vextractf64x4_high(Address(rsp, n*32), as_XMMRegister(n));
}
__ subptr(rsp, opmask_state_bytes); // Save opmask registers for (int n = 0; n < KRegister::number_of_registers; n++) {
__ kmov(Address(rsp, n*8), as_KRegister(n));
}
}
} #else
assert(!save_vectors, "vectors are generated only by C2"); #endif
__ vzeroupper();
// Set an oopmap for the call site. This oopmap will map all // oop-registers and debug-info registers as callee-saved. This // will allow deoptimization at this safepoint to find all possible // debug-info recordings, as well as let GC find all oops.
OopMapSet *oop_maps = new OopMapSet();
OopMap* map = new OopMap( frame_words, 0 );
map->set_callee_saved(STACK_OFFSET(rax_off), rax->as_VMReg());
map->set_callee_saved(STACK_OFFSET(rcx_off), rcx->as_VMReg());
map->set_callee_saved(STACK_OFFSET(rdx_off), rdx->as_VMReg());
map->set_callee_saved(STACK_OFFSET(rbx_off), rbx->as_VMReg()); // rbp, location is known implicitly, no oopMap
map->set_callee_saved(STACK_OFFSET(rsi_off), rsi->as_VMReg());
map->set_callee_saved(STACK_OFFSET(rdi_off), rdi->as_VMReg());
// %%% This is really a waste but we'll keep things as they were for now for the upper component
off = st0_off;
delta = st1_off - off; for (int n = 0; n < FloatRegister::number_of_registers; n++) {
FloatRegister freg_name = as_FloatRegister(n);
map->set_callee_saved(STACK_OFFSET(off), freg_name->as_VMReg());
map->set_callee_saved(STACK_OFFSET(off+1), NEXTREG(freg_name));
off += delta;
}
off = xmm0_off;
delta = xmm1_off - off; for (int n = 0; n < num_xmm_regs; n++) {
XMMRegister xmm_name = as_XMMRegister(n);
map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg());
map->set_callee_saved(STACK_OFFSET(off+1), NEXTREG(xmm_name));
off += delta;
} #undef NEXTREG #undef STACK_OFFSET
return map;
}
void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) { int opmask_state_bytes = 0; int additional_frame_bytes = 0; int num_xmm_regs = XMMRegister::number_of_registers; int ymm_bytes = num_xmm_regs * 16; int zmm_bytes = num_xmm_regs * 32; // Recover XMM & FPU state #ifdef COMPILER2 if (restore_vectors) {
assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX");
assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported"); // Save upper half of YMM registers
additional_frame_bytes = ymm_bytes; if (UseAVX > 2) { // Save upper half of ZMM registers as well
additional_frame_bytes += zmm_bytes;
opmask_state_bytes = KRegister::number_of_registers * 8;
additional_frame_bytes += opmask_state_bytes;
}
} #else
assert(!restore_vectors, "vectors are generated only by C2"); #endif
int off = xmm0_off; int delta = xmm1_off - off;
__ vzeroupper();
if (UseSSE == 1) { // Restore XMM registers
assert(additional_frame_bytes == 0, ""); for (int n = 0; n < num_xmm_regs; n++) {
__ movflt(as_XMMRegister(n), Address(rsp, off*wordSize));
off += delta;
}
} elseif (UseSSE >= 2) { // Restore whole 128bit (16 bytes) XMM registers. Do this before restoring YMM and // ZMM because the movdqu instruction zeros the upper part of the XMM register. for (int n = 0; n < num_xmm_regs; n++) {
__ movdqu(as_XMMRegister(n), Address(rsp, off*wordSize+additional_frame_bytes));
off += delta;
}
}
if (restore_vectors) {
off = additional_frame_bytes - ymm_bytes; // Restore upper half of YMM registers. for (int n = 0; n < num_xmm_regs; n++) {
__ vinsertf128_high(as_XMMRegister(n), Address(rsp, n*16+off));
} if (UseAVX > 2) { // Restore upper half of ZMM registers.
off = opmask_state_bytes; for (int n = 0; n < num_xmm_regs; n++) {
__ vinsertf64x4_high(as_XMMRegister(n), Address(rsp, n*32+off));
} for (int n = 0; n < KRegister::number_of_registers; n++) {
__ kmov(as_KRegister(n), Address(rsp, n*8));
}
}
__ addptr(rsp, additional_frame_bytes);
}
__ pop_FPU_state();
__ addptr(rsp, FPU_regs_live*wordSize); // Pop FPU registers
__ popf();
__ popa(); // Get the rbp, described implicitly by the frame sender code (no oopMap)
__ pop(rbp);
}
// Just restore result register. Only used by deoptimization. By // now any callee save register that needs to be restore to a c2 // caller of the deoptee has been extracted into the vframeArray // and will be stuffed into the c2i adapter we create for later // restoration so only result registers need to be restored here. //
__ frstor(Address(rsp, 0)); // Restore fpu state
// Recover XMM & FPU state if( UseSSE == 1 ) {
__ movflt(xmm0, Address(rsp, xmm0_off*wordSize));
} elseif( UseSSE >= 2 ) {
__ movdbl(xmm0, Address(rsp, xmm0_off*wordSize));
}
__ movptr(rax, Address(rsp, rax_off*wordSize));
__ movptr(rdx, Address(rsp, rdx_off*wordSize)); // Pop all of the register save are off the stack except the return address
__ addptr(rsp, return_off * wordSize);
}
// Is vector's size (in bytes) bigger than a size saved by default? // 16 bytes XMM registers are saved by default using SSE2 movdqu instructions. // Note, MaxVectorSize == 0 with UseSSE < 2 and vectors are not generated. bool SharedRuntime::is_wide_vector(int size) { return size > 16;
}
// The java_calling_convention describes stack locations as ideal slots on // a frame with no abi restrictions. Since we must observe abi restrictions // (like the placement of the register window) the slots must be biased by // the following value. staticint reg2offset_in(VMReg r) { // Account for saved rbp, and return address // This should really be in_preserve_stack_slots return (r->reg2stack() + 2) * VMRegImpl::stack_slot_size;
}
// --------------------------------------------------------------------------- // Read the array of BasicTypes from a signature, and compute where the // arguments should go. Values in the VMRegPair regs array refer to 4-byte // quantities. Values less than SharedInfo::stack0 are registers, those above // refer to 4-byte stack slots. All stack slots are based off of the stack pointer // as framesizes are fixed. // VMRegImpl::stack0 refers to the first slot 0(sp). // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. // Register up to Register::number_of_registers are the 32-bit // integer registers.
// Pass first two oop/int args in registers ECX and EDX. // Pass first two float/double args in registers XMM0 and XMM1. // Doubles have precedence, so if you pass a mix of floats and doubles // the doubles will grab the registers before the floats will.
// Note: the INPUTS in sig_bt are in units of Java argument words, which are // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit // units regardless of build. Of course for i486 there is no 64 bit build
// --------------------------------------------------------------------------- // The compiled Java calling convention. // Pass first two oop/int args in registers ECX and EDX. // Pass first two float/double args in registers XMM0 and XMM1. // Doubles have precedence, so if you pass a mix of floats and doubles // the doubles will grab the registers before the floats will. int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
VMRegPair *regs, int total_args_passed) {
uint stack = 0; // Starting stack position for args on stack
// Pass first two oop/int args in registers ECX and EDX.
uint reg_arg0 = 9999;
uint reg_arg1 = 9999;
// Pass first two float/double args in registers XMM0 and XMM1. // Doubles have precedence, so if you pass a mix of floats and doubles // the doubles will grab the registers before the floats will. // CNC - TURNED OFF FOR non-SSE. // On Intel we have to round all doubles (and most floats) at // call sites by storing to the stack in any case. // UseSSE=0 ==> Don't Use ==> 9999+0 // UseSSE=1 ==> Floats only ==> 9999+1 // UseSSE>=2 ==> Floats or doubles ==> 9999+2 enum { fltarg_dontuse = 9999+0, fltarg_float_only = 9999+1, fltarg_flt_dbl = 9999+2 };
uint fargs = (UseSSE>=2) ? 2 : UseSSE;
uint freg_arg0 = 9999+fargs;
uint freg_arg1 = 9999+fargs;
// Pass doubles & longs aligned on the stack. First count stack slots for doubles int i; for( i = 0; i < total_args_passed; i++) { if( sig_bt[i] == T_DOUBLE ) { // first 2 doubles go in registers if( freg_arg0 == fltarg_flt_dbl ) freg_arg0 = i; elseif( freg_arg1 == fltarg_flt_dbl ) freg_arg1 = i; else// Else double is passed low on the stack to be aligned.
stack += 2;
} elseif( sig_bt[i] == T_LONG ) {
stack += 2;
}
} int dstack = 0; // Separate counter for placing doubles
// Now pick where all else goes. for( i = 0; i < total_args_passed; i++) { // From the type and the argument number (count) compute the location switch( sig_bt[i] ) { case T_SHORT: case T_CHAR: case T_BYTE: case T_BOOLEAN: case T_INT: case T_ARRAY: case T_OBJECT: case T_ADDRESS: if( reg_arg0 == 9999 ) {
reg_arg0 = i;
regs[i].set1(rcx->as_VMReg());
} elseif( reg_arg1 == 9999 ) {
reg_arg1 = i;
regs[i].set1(rdx->as_VMReg());
} else {
regs[i].set1(VMRegImpl::stack2reg(stack++));
} break; case T_FLOAT: if( freg_arg0 == fltarg_flt_dbl || freg_arg0 == fltarg_float_only ) {
freg_arg0 = i;
regs[i].set1(xmm0->as_VMReg());
} elseif( freg_arg1 == fltarg_flt_dbl || freg_arg1 == fltarg_float_only ) {
freg_arg1 = i;
regs[i].set1(xmm1->as_VMReg());
} else {
regs[i].set1(VMRegImpl::stack2reg(stack++));
} break; case T_LONG:
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
regs[i].set2(VMRegImpl::stack2reg(dstack));
dstack += 2; break; case T_DOUBLE:
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" ); if( freg_arg0 == (uint)i ) {
regs[i].set2(xmm0->as_VMReg());
} elseif( freg_arg1 == (uint)i ) {
regs[i].set2(xmm1->as_VMReg());
} else {
regs[i].set2(VMRegImpl::stack2reg(dstack));
dstack += 2;
} break; case T_VOID: regs[i].set_bad(); break; break; default:
ShouldNotReachHere(); break;
}
}
// return value can be odd number of VMRegImpl stack slots make multiple of 2 return align_up(stack, 2);
}
// Patch the callers callsite with entry to compiled code if it exists. staticvoid patch_callers_callsite(MacroAssembler *masm) {
Label L;
__ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
__ jcc(Assembler::equal, L); // Schedule the branch target address early. // Call into the VM to patch the caller, then jump to compiled callee // rax, isn't live so capture return address while we easily can
__ movptr(rax, Address(rsp, 0));
__ pusha();
__ pushf();
if (UseSSE == 1) {
__ subptr(rsp, 2*wordSize);
__ movflt(Address(rsp, 0), xmm0);
__ movflt(Address(rsp, wordSize), xmm1);
} if (UseSSE >= 2) {
__ subptr(rsp, 4*wordSize);
__ movdbl(Address(rsp, 0), xmm0);
__ movdbl(Address(rsp, 2*wordSize), xmm1);
} #ifdef COMPILER2 // C2 may leave the stack dirty if not in SSE2+ mode if (UseSSE >= 2) {
__ verify_FPU(0, "c2i transition should have clean FPU stack");
} else {
__ empty_FPU_stack();
} #endif/* COMPILER2 */
// VM needs caller's callsite
__ push(rax); // VM needs target method
__ push(rbx);
__ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
__ addptr(rsp, 2*wordSize);
staticvoid move_c2i_double(MacroAssembler *masm, XMMRegister r, int st_off) { int next_off = st_off - Interpreter::stackElementSize;
__ movdbl(Address(rsp, next_off), r);
}
staticvoid gen_c2i_adapter(MacroAssembler *masm, int total_args_passed, int comp_args_on_stack, const BasicType *sig_bt, const VMRegPair *regs,
Label& skip_fixup) { // Before we get into the guts of the C2I adapter, see if we should be here // at all. We've come from compiled code and are attempting to jump to the // interpreter, which means the caller made a static call to get here // (vcalls always get a compiled target if there is one). Check for a // compiled target. If there is one, we need to patch the caller's call.
patch_callers_callsite(masm);
__ bind(skip_fixup);
#ifdef COMPILER2 // C2 may leave the stack dirty if not in SSE2+ mode if (UseSSE >= 2) {
__ verify_FPU(0, "c2i transition should have clean FPU stack");
} else {
__ empty_FPU_stack();
} #endif/* COMPILER2 */
// Since all args are passed on the stack, total_args_passed * interpreter_ // stack_element_size is the // space we need. int extraspace = total_args_passed * Interpreter::stackElementSize;
// Get return address
__ pop(rax);
// set senderSP value
__ movptr(rsi, rsp);
__ subptr(rsp, extraspace);
// Now write the args into the outgoing interpreter space for (int i = 0; i < total_args_passed; i++) { if (sig_bt[i] == T_VOID) {
assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); continue;
}
// st_off points to lowest address on stack. int st_off = ((total_args_passed - 1) - i) * Interpreter::stackElementSize; int next_off = st_off - Interpreter::stackElementSize;
void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, int total_args_passed, int comp_args_on_stack, const BasicType *sig_bt, const VMRegPair *regs) { // Note: rsi contains the senderSP on entry. We must preserve it since // we may do a i2c -> c2i transition if we lose a race where compiled // code goes non-entrant while we get args ready.
// Adapters can be frameless because they do not require the caller // to perform additional cleanup work, such as correcting the stack pointer. // An i2c adapter is frameless because the *caller* frame, which is interpreted, // routinely repairs its own stack pointer (from interpreter_frame_last_sp), // even if a callee has modified the stack pointer. // A c2i adapter is frameless because the *callee* frame, which is interpreted, // routinely repairs its caller's stack pointer (from sender_sp, which is set // up via the senderSP register). // In other words, if *either* the caller or callee is interpreted, we can // get the stack pointer repaired after a call. // This is why c2i and i2c adapters cannot be indefinitely composed. // In particular, if a c2i adapter were to somehow call an i2c adapter, // both caller and callee would be compiled methods, and neither would // clean up the stack pointer changes performed by the two adapters. // If this happens, control eventually transfers back to the compiled // caller, but with an uncorrected stack, causing delayed havoc.
// Pick up the return address
__ movptr(rax, Address(rsp, 0));
if (VerifyAdapterCalls &&
(Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { // So, let's test for cascading c2i/i2c adapters right now. // assert(Interpreter::contains($return_addr) || // StubRoutines::contains($return_addr), // "i2c adapter must return to an interpreter frame");
__ block_comment("verify_i2c { ");
Label L_ok; if (Interpreter::code() != NULL)
range_check(masm, rax, rdi,
Interpreter::code()->code_start(), Interpreter::code()->code_end(),
L_ok); if (StubRoutines::code1() != NULL)
range_check(masm, rax, rdi,
StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
L_ok); if (StubRoutines::code2() != NULL)
range_check(masm, rax, rdi,
StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
L_ok); constchar* msg = "i2c adapter must return to an interpreter frame";
__ block_comment(msg);
__ stop(msg);
__ bind(L_ok);
__ block_comment("} verify_i2ce ");
}
// Must preserve original SP for loading incoming arguments because // we need to align the outgoing SP for compiled code.
__ movptr(rdi, rsp);
// Cut-out for having no stack args. Since up to 2 int/oop args are passed // in registers, we will occasionally have no stack args. int comp_words_on_stack = 0; if (comp_args_on_stack) { // Sig words on the stack are greater-than VMRegImpl::stack0. Those in // registers are below. By subtracting stack0, we either get a negative // number (all values in registers) or the maximum stack slot accessed. // int comp_args_on_stack = VMRegImpl::reg2stack(max_arg); // Convert 4-byte stack slots to words.
comp_words_on_stack = align_up(comp_args_on_stack*4, wordSize)>>LogBytesPerWord; // Round up to miminum stack alignment, in wordSize
comp_words_on_stack = align_up(comp_words_on_stack, 2);
__ subptr(rsp, comp_words_on_stack * wordSize);
}
// Align the outgoing SP
__ andptr(rsp, -(StackAlignmentInBytes));
// push the return address on the stack (note that pushing, rather // than storing it, yields the correct frame alignment for the callee)
__ push(rax);
// Put saved SP in another register constRegister saved_sp = rax;
__ movptr(saved_sp, rdi);
// Will jump to the compiled code just as if compiled code was doing it. // Pre-load the register-jump target early, to schedule it better.
__ movptr(rdi, Address(rbx, in_bytes(Method::from_compiled_offset())));
// Now generate the shuffle code. Pick up all register args and move the // rest through the floating point stack top. for (int i = 0; i < total_args_passed; i++) { if (sig_bt[i] == T_VOID) { // Longs and doubles are passed in native word order, but misaligned // in the 32-bit build.
assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); continue;
}
// Pick up 0, 1 or 2 words from SP+offset.
assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "scrambled load targets?"); // Load in argument order going down. int ld_off = (total_args_passed - i) * Interpreter::stackElementSize; // Point to interpreter value (vs. tag) int next_off = ld_off - Interpreter::stackElementSize; // // //
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second(); if (!r_1->is_valid()) {
assert(!r_2->is_valid(), ""); continue;
} if (r_1->is_stack()) { // Convert stack slot to an SP offset (+ wordSize to account for return address ) int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
// We can use rsi as a temp here because compiled code doesn't need rsi as an input // and if we end up going thru a c2i because of a miss a reasonable value of rsi // we be generated. if (!r_2->is_valid()) { // __ fld_s(Address(saved_sp, ld_off)); // __ fstp_s(Address(rsp, st_off));
__ movl(rsi, Address(saved_sp, ld_off));
__ movptr(Address(rsp, st_off), rsi);
} else { // Interpreter local[n] == MSW, local[n+1] == LSW however locals // are accessed as negative so LSW is at LOW address
// ld_off is MSW so get LSW // st_off is LSW (i.e. reg.first()) // __ fld_d(Address(saved_sp, next_off)); // __ fstp_d(Address(rsp, st_off)); // // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case // So we must adjust where to pick up the data to match the interpreter. // // Interpreter local[n] == MSW, local[n+1] == LSW however locals // are accessed as negative so LSW is at LOW address
// ld_off is MSW so get LSW
__ movptr(rsi, Address(saved_sp, next_off));
__ movptr(Address(rsp, st_off), rsi);
__ movptr(rsi, Address(saved_sp, ld_off));
__ movptr(Address(rsp, st_off + wordSize), rsi);
}
} elseif (r_1->is_Register()) { // Register argument Register r = r_1->as_Register();
assert(r != rax, "must be different"); if (r_2->is_valid()) { // // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case // So we must adjust where to pick up the data to match the interpreter.
// this can be a misaligned move
__ movptr(r, Address(saved_sp, next_off));
assert(r_2->as_Register() != rax, "need another temporary register"); // Remember r_1 is low address (and LSB on x86) // So r_2 gets loaded from high address regardless of the platform
__ movptr(r_2->as_Register(), Address(saved_sp, ld_off));
} else {
__ movl(r, Address(saved_sp, ld_off));
}
} else {
assert(r_1->is_XMMRegister(), ""); if (!r_2->is_valid()) {
__ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
} else {
move_i2c_double(masm, r_1->as_XMMRegister(), saved_sp, ld_off);
}
}
}
// 6243940 We might end up in handle_wrong_method if // the callee is deoptimized as we race thru here. If that // happens we don't want to take a safepoint because the // caller frame will look interpreted and arguments are now // "compiled" so it is much better to make this transition // invisible to the stack walking code. Unfortunately if // we try and find the callee by normal means a safepoint // is possible. So we stash the desired callee in the thread // and the vm will find there should this case occur.
// move Method* to rax, in case we end up in an c2i adapter. // the c2i adapters expect Method* in rax, (c2) because c2's // resolve stubs return the result (the method) in rax,. // I'd love to fix this.
__ mov(rax, rbx);
// ------------------------------------------------------------------------- // Generate a C2I adapter. On entry we know rbx, holds the Method* during calls // to the interpreter. The args start out packed in the compiled layout. They // need to be unpacked into the interpreter layout. This will almost always // require some stack space. We grow the current (compiled) stack, then repack // the args. We finally end in a jump to the generic interpreter entry point. // On exit from the interpreter, the interpreter will restore our SP (lest the // compiled code, which relies solely on SP and not EBP, get sick).
Label missed;
__ movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
__ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
__ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset()));
__ jcc(Assembler::notEqual, missed); // Method might have been compiled since the call site was patched to // interpreted if that is the case treat it as a miss so we can get // the call site corrected.
__ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
__ jcc(Assembler::equal, skip_fixup);
int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
VMRegPair *regs,
VMRegPair *regs2, int total_args_passed) {
assert(regs2 == NULL, "not needed on x86"); // We return the amount of VMRegImpl stack slots we need to reserve for all // the arguments NOT counting out_preserve_stack_slots.
uint stack = 0; // All arguments on stack
for( int i = 0; i < total_args_passed; i++) { // From the type and the argument number (count) compute the location switch( sig_bt[i] ) { case T_BOOLEAN: case T_CHAR: case T_FLOAT: case T_BYTE: case T_SHORT: case T_INT: case T_OBJECT: case T_ARRAY: case T_ADDRESS: case T_METADATA:
regs[i].set1(VMRegImpl::stack2reg(stack++)); break; case T_LONG: case T_DOUBLE: // The stack numbering is reversed from Java // Since C arguments do not get reversed, the ordering for // doubles on the stack must be opposite the Java convention
assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
regs[i].set2(VMRegImpl::stack2reg(stack));
stack += 2; break; case T_VOID: regs[i].set_bad(); break; default:
ShouldNotReachHere(); break;
}
} return stack;
}
// A simple move of integer like type staticvoid simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { if (src.first()->is_stack()) { if (dst.first()->is_stack()) { // stack to stack // __ ld(FP, reg2offset(src.first()), L5); // __ st(L5, SP, reg2offset(dst.first()));
__ movl2ptr(rax, Address(rbp, reg2offset_in(src.first())));
__ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
} else { // stack to reg
__ movl2ptr(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
}
} elseif (dst.first()->is_stack()) { // reg to stack // no need to sign extend on 64bit
__ movptr(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
} else { if (dst.first() != src.first()) {
__ mov(dst.first()->as_Register(), src.first()->as_Register());
}
}
}
// An oop arg. Must pass a handle not the oop itself staticvoid object_move(MacroAssembler* masm,
OopMap* map, int oop_handle_offset, int framesize_in_slots,
VMRegPair src,
VMRegPair dst, bool is_receiver, int* receiver_offset) {
// Because of the calling conventions we know that src can be a // register or a stack location. dst can only be a stack location.
assert(dst.first()->is_stack(), "must be stack"); // must pass a handle. First figure out the location we use as a handle
if (src.first()->is_stack()) { // Oop is already on the stack as an argument Register rHandle = rax;
Label nil;
__ xorptr(rHandle, rHandle);
__ cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
__ jcc(Assembler::equal, nil);
__ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
__ bind(nil);
__ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); if (is_receiver) {
*receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
}
} else { // Oop is in a register we must store it to the space we reserve // on the stack for oop_handles constRegister rOop = src.first()->as_Register(); constRegister rHandle = rax; int oop_slot = (rOop == rcx ? 0 : 1) * VMRegImpl::slots_per_word + oop_handle_offset; int offset = oop_slot*VMRegImpl::stack_slot_size;
Label skip;
__ movptr(Address(rsp, offset), rOop);
map->set_oop(VMRegImpl::stack2reg(oop_slot));
__ xorptr(rHandle, rHandle);
__ cmpptr(rOop, NULL_WORD);
__ jcc(Assembler::equal, skip);
__ lea(rHandle, Address(rsp, offset));
__ bind(skip); // Store the handle parameter
__ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle); if (is_receiver) {
*receiver_offset = offset;
}
}
}
// A float arg may have to do float reg int reg conversion staticvoid float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
// Because of the calling convention we know that src is either a stack location // or an xmm register. dst can only be a stack location.
// A long move staticvoid long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
// The only legal possibility for a long_move VMRegPair is: // 1: two stack slots (possibly unaligned) // as neither the java or C calling convention will use registers // for longs.
// The only legal possibilities for a double_move VMRegPair are: // The painful thing here is that like long_move a VMRegPair might be
// Because of the calling convention we know that src is either // 1: a single physical register (xmm registers only) // 2: two stack slots (possibly unaligned) // dst can only be a pair of stack slots.
if (src.first()->is_stack()) { // source is all stack
__ movptr(rax, Address(rbp, reg2offset_in(src.first())));
__ movptr(rbx, Address(rbp, reg2offset_in(src.second())));
__ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
__ movptr(Address(rsp, reg2offset_out(dst.second())), rbx);
} else { // reg to stack // No worries about stack alignment
__ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
}
}
void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { // We always ignore the frame_slots arg and just use the space just below frame pointer // which by this time is free to use switch (ret_type) { case T_FLOAT:
__ fstp_s(Address(rbp, -wordSize)); break; case T_DOUBLE:
__ fstp_d(Address(rbp, -2*wordSize)); break; case T_VOID: break; case T_LONG:
__ movptr(Address(rbp, -wordSize), rax);
__ movptr(Address(rbp, -2*wordSize), rdx); break; default: {
__ movptr(Address(rbp, -wordSize), rax);
}
}
}
void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { // We always ignore the frame_slots arg and just use the space just below frame pointer // which by this time is free to use switch (ret_type) { case T_FLOAT:
__ fld_s(Address(rbp, -wordSize)); break; case T_DOUBLE:
__ fld_d(Address(rbp, -2*wordSize)); break; case T_LONG:
__ movptr(rax, Address(rbp, -wordSize));
__ movptr(rdx, Address(rbp, -2*wordSize)); break; case T_VOID: break; default: {
__ movptr(rax, Address(rbp, -wordSize));
}
}
}
staticvoid verify_oop_args(MacroAssembler* masm, const methodHandle& method, const BasicType* sig_bt, const VMRegPair* regs) { Register temp_reg = rbx; // not part of any compiled calling seq if (VerifyOops) { for (int i = 0; i < method->size_of_parameters(); i++) { if (is_reference_type(sig_bt[i])) {
VMReg r = regs[i].first();
assert(r->is_valid(), "bad oop arg"); if (r->is_stack()) {
__ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
__ verify_oop(temp_reg);
} else {
__ verify_oop(r->as_Register());
}
}
}
}
}
// Now write the args into the outgoing interpreter space bool has_receiver = false; Register receiver_reg = noreg; int member_arg_pos = -1; Register member_reg = noreg; int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); if (ref_kind != 0) {
member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
member_reg = rbx; // known to be free at this point
has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
} elseif (iid == vmIntrinsics::_invokeBasic) {
has_receiver = true;
} else {
fatal("unexpected intrinsic id %d", vmIntrinsics::as_int(iid));
}
if (member_reg != noreg) { // Load the member_arg into register, if necessary.
SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
VMReg r = regs[member_arg_pos].first(); if (r->is_stack()) {
__ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
} else { // no data motion is needed
member_reg = r->as_Register();
}
}
if (has_receiver) { // Make sure the receiver is loaded into a register.
assert(method->size_of_parameters() > 0, "oob");
assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
VMReg r = regs[0].first();
assert(r->is_valid(), "bad receiver arg"); if (r->is_stack()) { // Porting note: This assumes that compiled calling conventions always // pass the receiver oop in a register. If this is not true on some // platform, pick a temp and load the receiver from stack.
fatal("receiver always in a register");
receiver_reg = rcx; // known to be free at this point
__ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
} else { // no data motion is needed
receiver_reg = r->as_Register();
}
}
// Figure out which address we are really jumping to:
MethodHandles::generate_method_handle_dispatch(masm, iid,
receiver_reg, member_reg, /*for_compiler_entry:*/ true);
}
// --------------------------------------------------------------------------- // Generate a native wrapper for a given method. The method takes arguments // in the Java compiled code convention, marshals them to the native // convention (handlizes oops, etc), transitions to native, makes the call, // returns to java state (possibly blocking), unhandlizes any result and // returns. // // Critical native functions are a shorthand for the use of // GetPrimtiveArrayCritical and disallow the use of any other JNI // functions. The wrapper is expected to unpack the arguments before // passing them to the callee. Critical native functions leave the state _in_Java, // since they cannot stop for GC. // Some other parts of JNI setup are skipped like the tear down of the JNI handle // block and the check for pending exceptions it's impossible for them // to be thrown. // //
nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, const methodHandle& method, int compile_id,
BasicType* in_sig_bt,
VMRegPair* in_regs,
BasicType ret_type) { if (method->is_method_handle_intrinsic()) {
vmIntrinsics::ID iid = method->intrinsic_id();
intptr_t start = (intptr_t)__ pc(); int vep_offset = ((intptr_t)__ pc()) - start;
gen_special_dispatch(masm,
method,
in_sig_bt,
in_regs); int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
__ flush(); int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually return nmethod::new_native_nmethod(method,
compile_id,
masm->code(),
vep_offset,
frame_complete,
stack_slots / VMRegImpl::slots_per_word,
in_ByteSize(-1),
in_ByteSize(-1),
(OopMapSet*)NULL);
}
address native_func = method->native_function();
assert(native_func != NULL, "must have function");
// An OopMap for lock (and class if static)
OopMapSet *oop_maps = new OopMapSet();
// We have received a description of where all the java arg are located // on entry to the wrapper. We need to convert these args to where // the jni function will expect them. To figure out where they go // we convert the java signature to a C signature by inserting // the hidden arguments as arg[0] and possibly arg[1] (static method)
int argc = 0;
out_sig_bt[argc++] = T_ADDRESS; if (method->is_static()) {
out_sig_bt[argc++] = T_OBJECT;
}
for (int i = 0; i < total_in_args ; i++ ) {
out_sig_bt[argc++] = in_sig_bt[i];
}
// Now figure out where the args must be stored and how much stack space // they require. int out_arg_slots;
out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
// Compute framesize for the wrapper. We need to handlize all oops in // registers a max of 2 on x86.
// Calculate the total number of stack slots we will need.
// First count the abi requirement plus all of the outgoing args int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
// Now the space for the inbound oop handle area int total_save_slots = 2 * VMRegImpl::slots_per_word; // 2 arguments passed in registers
int oop_handle_offset = stack_slots;
stack_slots += total_save_slots;
// Now any space we need for handlizing a klass if static method
int klass_slot_offset = 0; int klass_offset = -1; int lock_slot_offset = 0; bool is_static = false;
if (method->is_synchronized()) {
lock_slot_offset = stack_slots;
stack_slots += VMRegImpl::slots_per_word;
}
// Now a place (+2) to save return values or temp during shuffling // + 2 for return address (which we own) and saved rbp,
stack_slots += 4;
// Ok The space we have allocated will look like: // // // FP-> | | // |---------------------| // | 2 slots for moves | // |---------------------| // | lock box (if sync) | // |---------------------| <- lock_slot_offset (-lock_slot_rbp_offset) // | klass (if static) | // |---------------------| <- klass_slot_offset // | oopHandle area | // |---------------------| <- oop_handle_offset (a max of 2 registers) // | outbound memory | // | based arguments | // | | // |---------------------| // | | // SP-> | out_preserved_slots | // // // **************************************************************************** // WARNING - on Windows Java Natives use pascal calling convention and pop the // arguments off of the stack after the jni call. Before the call we can use // instructions that are SP relative. After the jni call we switch to FP // relative instructions instead of re-adjusting the stack on windows. // ****************************************************************************
// Now compute actual number of stack words we need rounding to make // stack properly aligned.
stack_slots = align_up(stack_slots, StackAlignmentInSlots);
int stack_size = stack_slots * VMRegImpl::stack_slot_size;
intptr_t start = (intptr_t)__ pc();
// First thing make an ic check to see if we should even be here
// We are free to use all registers as temps without saving them and // restoring them except rbp. rbp is the only callee save register // as far as the interpreter and the compiler(s) are concerned.
// verified entry must be aligned for code patching. // and the first 5 bytes must be in the same cache line // if we align at 8 then we will be sure 5 bytes are in the same line
__ align(8);
__ bind(hit);
int vep_offset = ((intptr_t)__ pc()) - start;
#ifdef COMPILER1 // For Object.hashCode, System.identityHashCode try to pull hashCode from object header if available. if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) {
inline_check_hashcode_from_object_header(masm, method, rcx /*obj_reg*/, rax /*result*/);
} #endif// COMPILER1
// The instruction at the verified entry point must be 5 bytes or longer // because it can be patched on the fly by make_non_entrant. The stack bang // instruction fits that requirement.
// Generate a new frame for the wrapper.
__ enter(); // -2 because return address is already present and so is saved rbp
__ subptr(rsp, stack_size - 2*wordSize);
// Frame is now completed as far as size and linkage. int frame_complete = ((intptr_t)__ pc()) - start;
if (UseRTMLocking) { // Abort RTM transaction before calling JNI // because critical section will be large and will be // aborted anyway. Also nmethod could be deoptimized.
__ xabort(0);
}
// Calculate the difference between rsp and rbp,. We need to know it // after the native call because on windows Java Natives will pop // the arguments and it is painful to do rsp relative addressing // in a platform independent way. So after the call we switch to // rbp, relative addressing.
int fp_adjustment = stack_size - 2*wordSize;
#ifdef COMPILER2 // C2 may leave the stack dirty if not in SSE2+ mode if (UseSSE >= 2) {
__ verify_FPU(0, "c2i transition should have clean FPU stack");
} else {
__ empty_FPU_stack();
} #endif/* COMPILER2 */
// Compute the rbp, offset for any slots used after the jni call
int lock_slot_rbp_offset = (lock_slot_offset*VMRegImpl::stack_slot_size) - fp_adjustment;
// We use rdi as a thread pointer because it is callee save and // if we load it once it is usable thru the entire wrapper constRegister thread = rdi;
// We use rsi as the oop handle for the receiver/klass // It is callee save so it survives the call to native
constRegister oop_handle_reg = rsi;
__ get_thread(thread);
// // We immediately shuffle the arguments so that any vm call we have to // make from here on out (sync slow path, jvmti, etc.) we will have // captured the oops from our caller and have a valid oopMap for // them.
// ----------------- // The Grand Shuffle // // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv* // and, if static, the class mirror instead of a receiver. This pretty much // guarantees that register layout will not match (and x86 doesn't use reg // parms though amd does). Since the native abi doesn't use register args // and the java conventions does we don't have to worry about collisions. // All of our moved are reg->stack or stack->stack. // We ignore the extra arguments during the shuffle and handle them at the // last moment. The shuffle is described by the two calling convention // vectors we have in our possession. We simply walk the java vector to // get the source locations and the c vector to get the destinations.
int c_arg = method->is_static() ? 2 : 1;
// Record rsp-based slot for receiver on stack for non-static methods int receiver_offset = -1;
// This is a trick. We double the stack slots so we can claim // the oops in the caller's frame. Since we are sure to have // more args than the caller doubling is enough to make // sure we can capture all the incoming oop args from the // caller. //
OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
// Mark location of rbp, // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, rbp->as_VMReg());
// We know that we only have args in at most two integer registers (rcx, rdx). So rax, rbx // Are free to temporaries if we have to do stack to steck moves. // All inbound args are referenced based on rbp, and all outbound args via rsp.
for (int i = 0; i < total_in_args ; i++, c_arg++ ) { switch (in_sig_bt[i]) { case T_ARRAY: case T_OBJECT:
object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
((i == 0) && (!is_static)),
&receiver_offset); break; case T_VOID: break;
case T_FLOAT:
float_move(masm, in_regs[i], out_regs[c_arg]); break;
// Pre-load a static method's oop into rsi. Used both by locking code and // the normal JNI call code. if (method->is_static()) {
// load opp into a register
__ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror()));
// Now handlize the static class mirror it's known not-null.
__ movptr(Address(rsp, klass_offset), oop_handle_reg);
map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
// Now get the handle
__ lea(oop_handle_reg, Address(rsp, klass_offset)); // store the klass handle as second argument
__ movptr(Address(rsp, wordSize), oop_handle_reg);
}
// Change state to native (we save the return address in the thread, since it might not // be pushed on the stack when we do a stack traversal). It is enough that the pc() // points into the right code segment. It does not have to be the correct return pc. // We use the same pc/oopMap repeatedly when we call out
// We have all of the arguments setup at this point. We must not touch any register // argument registers at this point (what if we save/restore them there are no oop?
// RedefineClasses() tracing support for obsolete method entry if (log_is_enabled(Trace, redefine, class, obsolete)) {
__ mov_metadata(rax, method());
__ call_VM_leaf(
CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
thread, rax);
}
// These are register definitions we need for locking/unlocking constRegister swap_reg = rax; // Must use rax, for cmpxchg instruction constRegister obj_reg = rcx; // Will contain the oop constRegister lock_reg = rdx; // Address of compiler lock object (BasicLock)
Label slow_path_lock;
Label lock_done;
// Lock a synchronized method if (method->is_synchronized()) {
Label count_mon;
// Test if the oopMark is an obvious stack pointer, i.e., // 1) (mark & 3) == 0, and // 2) rsp <= mark < mark + os::pagesize() // These 3 tests can be done by evaluating the following // expression: ((mark - rsp) & (3 - os::vm_page_size())), // assuming both stack pointer and pagesize have their // least significant 2 bits clear. // NOTE: the oopMark is in swap_reg %rax, as the result of cmpxchg
// Save the test result, for recursive case, the result is zero
__ movptr(Address(lock_reg, mark_word_offset), swap_reg);
__ jcc(Assembler::notEqual, slow_path_lock);
} else {
__ jmp(slow_path_lock);
}
__ bind(count_mon);
__ inc_held_monitor_count();
// Slow path will re-enter here
__ bind(lock_done);
}
// Finally just about ready to make the JNI call
// get JNIEnv* which is first argument to native
__ lea(rdx, Address(thread, in_bytes(JavaThread::jni_environment_offset())));
__ movptr(Address(rsp, 0), rdx);
// Now set thread in native
__ movl(Address(thread, JavaThread::thread_state_offset()), _thread_in_native);
__ call(RuntimeAddress(native_func));
--> --------------------
--> maximum size reached
--> --------------------
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